1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
31 class TargetRegisterClass;
33 /// TargetRegisterDesc - This record contains all of the information known about
34 /// a particular register. The AliasSet field (if not null) contains a pointer
35 /// to a Zero terminated array of registers that this register aliases. This is
36 /// needed for architectures like X86 which have AL alias AX alias EAX.
37 /// Registers that this does not apply to simply should set this to null.
39 struct TargetRegisterDesc {
40 const char *Name; // Assembly language name for the register
41 const unsigned *AliasSet; // Register Alias Set, described above
44 class TargetRegisterClass {
46 typedef const unsigned* iterator;
47 typedef const unsigned* const_iterator;
49 typedef const MVT::ValueType* vt_iterator;
50 typedef const TargetRegisterClass* const * sc_iterator;
54 const vt_iterator VTs;
55 const sc_iterator SubClasses;
56 const sc_iterator SuperClasses;
57 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
58 const iterator RegsBegin, RegsEnd;
60 TargetRegisterClass(unsigned id,
61 const MVT::ValueType *vts,
62 const TargetRegisterClass * const *subcs,
63 const TargetRegisterClass * const *supcs,
64 unsigned RS, unsigned Al, iterator RB, iterator RE)
65 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
66 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
67 virtual ~TargetRegisterClass() {} // Allow subclasses
69 /// getID() - Return the register class ID number.
71 unsigned getID() const { return ID; }
73 /// begin/end - Return all of the registers in this class.
75 iterator begin() const { return RegsBegin; }
76 iterator end() const { return RegsEnd; }
78 /// getNumRegs - Return the number of registers in this class.
80 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
82 /// getRegister - Return the specified register in the class.
84 unsigned getRegister(unsigned i) const {
85 assert(i < getNumRegs() && "Register number out of range!");
89 /// contains - Return true if the specified register is included in this
91 bool contains(unsigned Reg) const {
92 for (iterator I = begin(), E = end(); I != E; ++I)
93 if (*I == Reg) return true;
97 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
99 bool hasType(MVT::ValueType vt) const {
100 for(int i = 0; VTs[i] != MVT::Other; ++i)
106 /// vt_begin / vt_end - Loop over all of the value types that can be
107 /// represented by values in this register class.
108 vt_iterator vt_begin() const {
112 vt_iterator vt_end() const {
114 while (*I != MVT::Other) ++I;
118 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
119 /// sub-register class of this TargetRegisterClass.
120 bool hasSubRegClass(const TargetRegisterClass *cs) const {
121 for (int i = 0; SubClasses[i] != NULL; ++i)
122 if (SubClasses[i] == cs)
127 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
128 /// this register class.
129 sc_iterator subclasses_begin() const {
133 sc_iterator subclasses_end() const {
134 sc_iterator I = SubClasses;
135 while (*I != NULL) ++I;
139 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
140 /// super-register class of this TargetRegisterClass.
141 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
142 for (int i = 0; SuperClasses[i] != NULL; ++i)
143 if (SuperClasses[i] == cs)
148 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
149 /// of this register class.
150 sc_iterator superclasses_begin() const {
154 sc_iterator superclasses_end() const {
155 sc_iterator I = SuperClasses;
156 while (*I != NULL) ++I;
160 /// allocation_order_begin/end - These methods define a range of registers
161 /// which specify the registers in this class that are valid to register
162 /// allocate, and the preferred order to allocate them in. For example,
163 /// callee saved registers should be at the end of the list, because it is
164 /// cheaper to allocate caller saved registers.
166 /// These methods take a MachineFunction argument, which can be used to tune
167 /// the allocatable registers based on the characteristics of the function.
168 /// One simple example is that the frame pointer register can be used if
169 /// frame-pointer-elimination is performed.
171 /// By default, these methods return all registers in the class.
173 virtual iterator allocation_order_begin(MachineFunction &MF) const {
176 virtual iterator allocation_order_end(MachineFunction &MF) const {
182 /// getSize - Return the size of the register in bytes, which is also the size
183 /// of a stack slot allocated to hold a spilled copy of this register.
184 unsigned getSize() const { return RegSize; }
186 /// getAlignment - Return the minimum required alignment for a register of
188 unsigned getAlignment() const { return Alignment; }
192 /// MRegisterInfo base class - We assume that the target defines a static array
193 /// of TargetRegisterDesc objects that represent all of the machine registers
194 /// that the target has. As such, we simply have to track a pointer to this
195 /// array so that we can turn register number into a register descriptor.
197 class MRegisterInfo {
199 typedef const TargetRegisterClass * const * regclass_iterator;
201 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
202 unsigned NumRegs; // Number of entries in the array
204 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
206 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
208 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
209 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
210 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
211 virtual ~MRegisterInfo();
214 enum { // Define some target independent constants
215 /// NoRegister - This physical register is not a real target register. It
216 /// is useful as a sentinal.
219 /// FirstVirtualRegister - This is the first register number that is
220 /// considered to be a 'virtual' register, which is part of the SSA
221 /// namespace. This must be the same for all targets, which means that each
222 /// target is limited to 1024 registers.
223 FirstVirtualRegister = 1024
226 /// isPhysicalRegister - Return true if the specified register number is in
227 /// the physical register namespace.
228 static bool isPhysicalRegister(unsigned Reg) {
229 assert(Reg && "this is not a register!");
230 return Reg < FirstVirtualRegister;
233 /// isVirtualRegister - Return true if the specified register number is in
234 /// the virtual register namespace.
235 static bool isVirtualRegister(unsigned Reg) {
236 assert(Reg && "this is not a register!");
237 return Reg >= FirstVirtualRegister;
240 /// getAllocatableSet - Returns a bitset indexed by register number
241 /// indicating if a register is allocatable or not.
242 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
244 const TargetRegisterDesc &operator[](unsigned RegNo) const {
245 assert(RegNo < NumRegs &&
246 "Attempting to access record for invalid register number!");
250 /// Provide a get method, equivalent to [], but more useful if we have a
251 /// pointer to this object.
253 const TargetRegisterDesc &get(unsigned RegNo) const {
254 return operator[](RegNo);
257 /// getAliasSet - Return the set of registers aliased by the specified
258 /// register, or a null list of there are none. The list returned is zero
261 const unsigned *getAliasSet(unsigned RegNo) const {
262 return get(RegNo).AliasSet;
265 /// getName - Return the symbolic target specific name for the specified
266 /// physical register.
267 const char *getName(unsigned RegNo) const {
268 return get(RegNo).Name;
271 /// getNumRegs - Return the number of registers this target has
272 /// (useful for sizing arrays holding per register information)
273 unsigned getNumRegs() const {
277 /// areAliases - Returns true if the two registers alias each other,
279 bool areAliases(unsigned regA, unsigned regB) const {
280 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
281 if (*Alias == regB) return true;
285 /// getCalleeSaveRegs - Return a null-terminated list of all of the
286 /// callee-save registers on this target.
287 virtual const unsigned* getCalleeSaveRegs() const = 0;
289 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
290 /// register classes to spill each callee-saved register with. The order and
291 /// length of this list match the getCalleeSaveRegs() list.
292 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
294 //===--------------------------------------------------------------------===//
295 // Register Class Information
298 /// Register class iterators
300 regclass_iterator regclass_begin() const { return RegClassBegin; }
301 regclass_iterator regclass_end() const { return RegClassEnd; }
303 unsigned getNumRegClasses() const {
304 return regclass_end()-regclass_begin();
307 /// getRegClass - Returns the register class associated with the enumeration
308 /// value. See class TargetOperandInfo.
309 const TargetRegisterClass *getRegClass(unsigned i) const {
310 assert(i <= getNumRegClasses() && "Register Class ID out of range");
311 return i ? RegClassBegin[i - 1] : NULL;
314 //===--------------------------------------------------------------------===//
315 // Interfaces used by the register allocator and stack frame
316 // manipulation passes to move data around between registers,
317 // immediates and memory. The return value is the number of
318 // instructions added to (negative if removed from) the basic block.
321 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
322 MachineBasicBlock::iterator MI,
323 unsigned SrcReg, int FrameIndex,
324 const TargetRegisterClass *RC) const = 0;
326 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator MI,
328 unsigned DestReg, int FrameIndex,
329 const TargetRegisterClass *RC) const = 0;
331 virtual void copyRegToReg(MachineBasicBlock &MBB,
332 MachineBasicBlock::iterator MI,
333 unsigned DestReg, unsigned SrcReg,
334 const TargetRegisterClass *RC) const = 0;
336 /// foldMemoryOperand - Attempt to fold a load or store of the
337 /// specified stack slot into the specified machine instruction for
338 /// the specified operand. If this is possible, a new instruction
339 /// is returned with the specified operand folded, otherwise NULL is
340 /// returned. The client is responsible for removing the old
341 /// instruction and adding the new one in the instruction stream
342 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
344 int FrameIndex) const {
348 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
349 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
350 /// targets use pseudo instructions in order to abstract away the difference
351 /// between operating with a frame pointer and operating without, through the
352 /// use of these two instructions.
354 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
355 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
358 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
359 /// code insertion to eliminate call frame setup and destroy pseudo
360 /// instructions (but only if the Target is using them). It is responsible
361 /// for eliminating these instructions, replacing them with concrete
362 /// instructions. This method need only be implemented if using call frame
363 /// setup/destroy pseudo instructions.
366 eliminateCallFramePseudoInstr(MachineFunction &MF,
367 MachineBasicBlock &MBB,
368 MachineBasicBlock::iterator MI) const {
369 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
370 "eliminateCallFramePseudoInstr must be implemented if using"
371 " call frame setup/destroy pseudo instructions!");
372 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
375 /// processFunctionBeforeFrameFinalized - This method is called immediately
376 /// before the specified functions frame layout (MF.getFrameInfo()) is
377 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
378 /// replaced with direct constants. This method is optional. The return value
379 /// is the number of instructions added to (negative if removed from) the
382 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
385 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
386 /// frame indices from instructions which may use them. The instruction
387 /// referenced by the iterator contains an MO_FrameIndex operand which must be
388 /// eliminated by this method. This method may modify or replace the
389 /// specified instruction, as long as it keeps the iterator pointing the the
390 /// finished product. The return value is the number of instructions
391 /// added to (negative if removed from) the basic block.
393 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
395 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
396 /// the function. The return value is the number of instructions
397 /// added to (negative if removed from) the basic block (entry for prologue).
399 virtual void emitPrologue(MachineFunction &MF) const = 0;
400 virtual void emitEpilogue(MachineFunction &MF,
401 MachineBasicBlock &MBB) const = 0;
403 //===--------------------------------------------------------------------===//
404 /// Debug information queries.
406 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
407 /// number. Returns -1 if there is no equivalent value.
408 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
410 /// getFrameRegister - This method should return the register used as a base
411 /// for values allocated in the current stack frame.
412 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
414 /// getRARegister - This method should return the register where the return
415 /// address can be found.
416 virtual unsigned getRARegister() const = 0;
418 /// getLocation - This method should return the actual location of a frame
419 /// variable given the frame index. The location is returned in ML.
420 /// Subclasses should override this method for special handling of frame
421 /// variables and call MRegisterInfo::getLocation for the default action.
422 virtual void getLocation(MachineFunction &MF, unsigned Index,
423 MachineLocation &ML) const;
425 /// getInitialFrameState - Returns a list of machine moves that are assumed
426 /// on entry to all functions. Note that LabelID is ignored (assumed to be
427 /// the beginning of the function.)
428 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const;
431 // This is useful when building DenseMaps keyed on virtual registers
432 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
433 unsigned operator()(unsigned Reg) const {
434 return Reg - MRegisterInfo::FirstVirtualRegister;
438 } // End llvm namespace