1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
23 class MachineFunction;
25 /// MRegisterDesc - This record contains all of the information known about a
26 /// particular register. The AliasSet field (if not null) contains a pointer to
27 /// a Zero terminated array of registers that this register aliases. This is
28 /// needed for architectures like X86 which have AL alias AX alias EAX.
29 /// Registers that this does not apply to simply should set this to null.
31 struct MRegisterDesc {
32 const char *Name; // Assembly language name for the register
33 const unsigned *AliasSet; // Register Alias Set, described above
34 unsigned Flags; // Flags identifying register properties (below)
35 unsigned TSFlags; // Target Specific Flags
38 class TargetRegisterClass {
40 typedef const unsigned* iterator;
41 typedef const unsigned* const_iterator;
44 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
45 const iterator RegsBegin, RegsEnd;
47 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
48 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
49 virtual ~TargetRegisterClass() {} // Allow subclasses
51 // begin/end - Return all of the registers in this class.
52 iterator begin() const { return RegsBegin; }
53 iterator end() const { return RegsEnd; }
55 // getNumRegs - Return the number of registers in this class
56 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
58 // getRegister - Return the specified register in the class
59 unsigned getRegister(unsigned i) const {
60 assert(i < getNumRegs() && "Register number out of range!");
64 /// allocation_order_begin/end - These methods define a range of registers
65 /// which specify the registers in this class that are valid to register
66 /// allocate, and the preferred order to allocate them in. For example,
67 /// callee saved registers should be at the end of the list, because it is
68 /// cheaper to allocate caller saved registers.
70 /// These methods take a MachineFunction argument, which can be used to tune
71 /// the allocatable registers based on the characteristics of the function.
72 /// One simple example is that the frame pointer register can be used if
73 /// frame-pointer-elimination is performed.
75 /// By default, these methods return all registers in the class.
77 virtual iterator allocation_order_begin(MachineFunction &MF) const {
80 virtual iterator allocation_order_end(MachineFunction &MF) const {
86 /// getSize - Return the size of the register in bytes, which is also the size
87 /// of a stack slot allocated to hold a spilled copy of this register.
88 unsigned getSize() const { return RegSize; }
90 /// getAlignment - Return the minimum required alignment for a register of
92 unsigned getAlignment() const { return Alignment; }
96 /// MRegisterInfo base class - We assume that the target defines a static array
97 /// of MRegisterDesc objects that represent all of the machine registers that
98 /// the target has. As such, we simply have to track a pointer to this array so
99 /// that we can turn register number into a register descriptor.
101 class MRegisterInfo {
103 typedef const TargetRegisterClass * const * regclass_iterator;
105 const MRegisterDesc *Desc; // Pointer to the descriptor array
106 unsigned NumRegs; // Number of entries in the array
108 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
110 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
111 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
113 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
114 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
115 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
116 virtual ~MRegisterInfo();
119 enum { // Define some target independent constants
120 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
121 /// This is used as the destination register for instructions that do not
122 /// produce a value. Some frontends may use this as an operand register to
123 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
124 /// which always PRODUCES the value 0. The X86 backend does not use this
125 /// value as an operand register, except for memory references.
129 /// FirstVirtualRegister - This is the first register number that is
130 /// considered to be a 'virtual' register, which is part of the SSA
131 /// namespace. This must be the same for all targets, which means that each
132 /// target is limited to 1024 registers.
134 FirstVirtualRegister = 1024,
137 const MRegisterDesc &operator[](unsigned RegNo) const {
138 assert(RegNo < NumRegs &&
139 "Attempting to access record for invalid register number!");
143 /// Provide a get method, equivalent to [], but more useful if we have a
144 /// pointer to this object.
146 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
148 /// getRegClass - Return the register class for the specified physical
151 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
152 assert(RegNo < NumRegs && "Register number out of range!");
153 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
154 return PhysRegClasses[RegNo];
157 /// getAliasSet - Return the set of registers aliased by the specified
158 /// register, or a null list of there are none. The list returned is zero
161 const unsigned *getAliasSet(unsigned RegNo) const {
162 return get(RegNo).AliasSet;
165 /// getName - Return the symbolic target specific name for the specified
166 /// physical register.
167 const char *getName(unsigned RegNo) const {
168 return get(RegNo).Name;
171 virtual const unsigned* getCalleeSaveRegs() const = 0;
174 //===--------------------------------------------------------------------===//
175 // Register Class Information
178 /// Register class iterators
180 regclass_iterator regclass_begin() const { return RegClassBegin; }
181 regclass_iterator regclass_end() const { return RegClassEnd; }
183 unsigned getNumRegClasses() const {
184 return regclass_end()-regclass_begin();
187 //===--------------------------------------------------------------------===//
188 // Interfaces used by the register allocator and stack frame manipulation
189 // passes to move data around between registers, immediates and memory.
192 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
193 MachineBasicBlock::iterator &MBBI,
194 unsigned SrcReg, int FrameIndex,
195 const TargetRegisterClass *RC) const = 0;
197 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
198 MachineBasicBlock::iterator &MBBI,
199 unsigned DestReg, int FrameIndex,
200 const TargetRegisterClass *RC) const = 0;
202 virtual void copyRegToReg(MachineBasicBlock &MBB,
203 MachineBasicBlock::iterator &MBBI,
204 unsigned DestReg, unsigned SrcReg,
205 const TargetRegisterClass *RC) const = 0;
208 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
209 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
210 /// targets use pseudo instructions in order to abstract away the difference
211 /// between operating with a frame pointer and operating without, through the
212 /// use of these two instructions.
214 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
215 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
218 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
219 /// code insertion to eliminate call frame setup and destroy pseudo
220 /// instructions (but only if the Target is using them). It is responsible
221 /// for eliminating these instructions, replacing them with concrete
222 /// instructions. This method need only be implemented if using call frame
223 /// setup/destroy pseudo instructions.
225 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
226 MachineBasicBlock &MBB,
227 MachineBasicBlock::iterator &I) const {
228 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
229 "eliminateCallFramePseudoInstr must be implemented if using"
230 " call frame setup/destroy pseudo instructions!");
231 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
234 /// processFunctionBeforeFrameFinalized - This method is called immediately
235 /// before the specified functions frame layout (MF.getFrameInfo()) is
236 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
237 /// replaced with direct constants. This method is optional.
239 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
241 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
242 /// frame indices from instructions which may use them. The instruction
243 /// referenced by the iterator contains an MO_FrameIndex operand which must be
244 /// eliminated by this method. This method may modify or replace the
245 /// specified instruction, as long as it keeps the iterator pointing the the
246 /// finished product.
248 virtual void eliminateFrameIndex(MachineFunction &MF,
249 MachineBasicBlock::iterator &II) const = 0;
251 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
253 virtual void emitPrologue(MachineFunction &MF) const = 0;
254 virtual void emitEpilogue(MachineFunction &MF,
255 MachineBasicBlock &MBB) const = 0;