1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
26 class MachineFunction;
29 /// MRegisterDesc - This record contains all of the information known about a
30 /// particular register. The AliasSet field (if not null) contains a pointer to
31 /// a Zero terminated array of registers that this register aliases. This is
32 /// needed for architectures like X86 which have AL alias AX alias EAX.
33 /// Registers that this does not apply to simply should set this to null.
35 struct MRegisterDesc {
36 const char *Name; // Assembly language name for the register
37 const unsigned *AliasSet; // Register Alias Set, described above
38 unsigned Flags; // Flags identifying register properties (below)
39 unsigned TSFlags; // Target Specific Flags
42 class TargetRegisterClass {
44 typedef const unsigned* iterator;
45 typedef const unsigned* const_iterator;
48 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
49 const iterator RegsBegin, RegsEnd;
51 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
52 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
53 virtual ~TargetRegisterClass() {} // Allow subclasses
55 // begin/end - Return all of the registers in this class.
56 iterator begin() const { return RegsBegin; }
57 iterator end() const { return RegsEnd; }
59 // getNumRegs - Return the number of registers in this class
60 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
62 // getRegister - Return the specified register in the class
63 unsigned getRegister(unsigned i) const {
64 assert(i < getNumRegs() && "Register number out of range!");
68 /// allocation_order_begin/end - These methods define a range of registers
69 /// which specify the registers in this class that are valid to register
70 /// allocate, and the preferred order to allocate them in. For example,
71 /// callee saved registers should be at the end of the list, because it is
72 /// cheaper to allocate caller saved registers.
74 /// These methods take a MachineFunction argument, which can be used to tune
75 /// the allocatable registers based on the characteristics of the function.
76 /// One simple example is that the frame pointer register can be used if
77 /// frame-pointer-elimination is performed.
79 /// By default, these methods return all registers in the class.
81 virtual iterator allocation_order_begin(MachineFunction &MF) const {
84 virtual iterator allocation_order_end(MachineFunction &MF) const {
90 /// getSize - Return the size of the register in bytes, which is also the size
91 /// of a stack slot allocated to hold a spilled copy of this register.
92 unsigned getSize() const { return RegSize; }
94 /// getAlignment - Return the minimum required alignment for a register of
96 unsigned getAlignment() const { return Alignment; }
100 /// MRegisterInfo base class - We assume that the target defines a static array
101 /// of MRegisterDesc objects that represent all of the machine registers that
102 /// the target has. As such, we simply have to track a pointer to this array so
103 /// that we can turn register number into a register descriptor.
105 class MRegisterInfo {
107 typedef const TargetRegisterClass * const * regclass_iterator;
109 const MRegisterDesc *Desc; // Pointer to the descriptor array
110 unsigned NumRegs; // Number of entries in the array
112 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
114 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
115 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
117 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
118 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
119 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
120 virtual ~MRegisterInfo();
123 enum { // Define some target independent constants
124 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
125 /// This is used as the destination register for instructions that do not
126 /// produce a value. Some frontends may use this as an operand register to
127 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
128 /// which always PRODUCES the value 0. The X86 backend does not use this
129 /// value as an operand register, except for memory references.
133 /// FirstVirtualRegister - This is the first register number that is
134 /// considered to be a 'virtual' register, which is part of the SSA
135 /// namespace. This must be the same for all targets, which means that each
136 /// target is limited to 1024 registers.
138 FirstVirtualRegister = 1024,
141 /// isPhysicalRegister - Return true if the specified register number is in
142 /// the physical register namespace.
143 static bool isPhysicalRegister(unsigned Reg) {
144 assert(Reg && "this is not a register!");
145 return Reg < FirstVirtualRegister;
148 /// isVirtualRegister - Return true if the specified register number is in
149 /// the virtual register namespace.
150 static bool isVirtualRegister(unsigned Reg) {
151 assert(Reg && "this is not a register!");
152 return Reg >= FirstVirtualRegister;
155 const MRegisterDesc &operator[](unsigned RegNo) const {
156 assert(RegNo < NumRegs &&
157 "Attempting to access record for invalid register number!");
161 /// Provide a get method, equivalent to [], but more useful if we have a
162 /// pointer to this object.
164 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
166 /// getRegClass - Return the register class for the specified physical
169 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
170 assert(RegNo < NumRegs && "Register number out of range!");
171 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
172 return PhysRegClasses[RegNo];
175 /// getAliasSet - Return the set of registers aliased by the specified
176 /// register, or a null list of there are none. The list returned is zero
179 const unsigned *getAliasSet(unsigned RegNo) const {
180 return get(RegNo).AliasSet;
183 /// getName - Return the symbolic target specific name for the specified
184 /// physical register.
185 const char *getName(unsigned RegNo) const {
186 return get(RegNo).Name;
189 /// getNumRegs - Return the number of registers this target has
190 /// (useful for sizing arrays holding per register information)
191 unsigned getNumRegs() const {
195 /// areAliases - Returns true if the two registers alias each other,
197 bool areAliases(unsigned regA, unsigned regB) const {
198 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
199 if (*Alias == regA) return true;
203 virtual const unsigned* getCalleeSaveRegs() const = 0;
206 //===--------------------------------------------------------------------===//
207 // Register Class Information
210 /// Register class iterators
212 regclass_iterator regclass_begin() const { return RegClassBegin; }
213 regclass_iterator regclass_end() const { return RegClassEnd; }
215 unsigned getNumRegClasses() const {
216 return regclass_end()-regclass_begin();
219 //===--------------------------------------------------------------------===//
220 // All basic block modifier functions below return the number of
221 // instructions added to (negative if removed from) the basic block
222 // passed as their first argument.
224 // FIXME: This is only needed because we use a std::vector instead
225 // of an ilist to keep MachineBasicBlock instructions. Inserting an
226 // instruction to a MachineBasicBlock invalidates all iterators to
227 // the basic block. The return value can be used to update an index
228 // to the machine basic block instruction vector and circumvent the
229 // iterator elimination problem but this is really not needed if we
230 // move to a better representation.
233 //===--------------------------------------------------------------------===//
234 // Interfaces used by the register allocator and stack frame
235 // manipulation passes to move data around between registers,
236 // immediates and memory. The return value is the number of
237 // instructions added to (negative if removed from) the basic block.
240 virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
241 MachineBasicBlock::iterator MI,
242 unsigned SrcReg, int FrameIndex,
243 const TargetRegisterClass *RC) const = 0;
245 virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
246 MachineBasicBlock::iterator MI,
247 unsigned DestReg, int FrameIndex,
248 const TargetRegisterClass *RC) const = 0;
250 virtual int copyRegToReg(MachineBasicBlock &MBB,
251 MachineBasicBlock::iterator MI,
252 unsigned DestReg, unsigned SrcReg,
253 const TargetRegisterClass *RC) const = 0;
256 /// foldMemoryOperand - Attempt to fold a load or store of the
257 /// specified stack slot into the specified machine instruction for
258 /// the specified operand. If this is possible, a new instruction
259 /// is returned with the specified operand folded, otherwise NULL is
260 /// returned. The client is responsible for removing the old
261 /// instruction and adding the new one in the instruction stream
262 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
264 int FrameIndex) const {
268 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
269 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
270 /// targets use pseudo instructions in order to abstract away the difference
271 /// between operating with a frame pointer and operating without, through the
272 /// use of these two instructions.
274 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
275 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
278 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
279 /// code insertion to eliminate call frame setup and destroy pseudo
280 /// instructions (but only if the Target is using them). It is responsible
281 /// for eliminating these instructions, replacing them with concrete
282 /// instructions. This method need only be implemented if using call frame
283 /// setup/destroy pseudo instructions. The return value is the number of
284 /// instructions added to (negative if removed from) the basic block.
287 eliminateCallFramePseudoInstr(MachineFunction &MF,
288 MachineBasicBlock &MBB,
289 MachineBasicBlock::iterator MI) const {
290 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
291 "eliminateCallFramePseudoInstr must be implemented if using"
292 " call frame setup/destroy pseudo instructions!");
293 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
296 /// processFunctionBeforeFrameFinalized - This method is called immediately
297 /// before the specified functions frame layout (MF.getFrameInfo()) is
298 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
299 /// replaced with direct constants. This method is optional. The return value
300 /// is the number of instructions added to (negative if removed from) the
303 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
306 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
307 /// frame indices from instructions which may use them. The instruction
308 /// referenced by the iterator contains an MO_FrameIndex operand which must be
309 /// eliminated by this method. This method may modify or replace the
310 /// specified instruction, as long as it keeps the iterator pointing the the
311 /// finished product. The return value is the number of instructions
312 /// added to (negative if removed from) the basic block.
314 virtual void eliminateFrameIndex(MachineFunction &MF,
315 MachineBasicBlock::iterator MI) const = 0;
317 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
318 /// the function. The return value is the number of instructions
319 /// added to (negative if removed from) the basic block (entry for prologue).
321 virtual void emitPrologue(MachineFunction &MF) const = 0;
322 virtual void emitEpilogue(MachineFunction &MF,
323 MachineBasicBlock &MBB) const = 0;
326 // This is useful when building DenseMap's keyed on virtual registers
327 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
328 unsigned operator()(unsigned Reg) const {
329 return Reg - MRegisterInfo::FirstVirtualRegister;
333 } // End llvm namespace