1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
41 /// The SubRegs field is a zero terminated array of registers that are
42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
44 struct TargetRegisterDesc {
45 const char *Name; // Assembly language name for the register
46 const unsigned *AliasSet; // Register Alias Set, described above
47 const unsigned *SubRegs; // Sub-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const MVT::ValueType* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
60 const vt_iterator VTs;
61 const sc_iterator SubClasses;
62 const sc_iterator SuperClasses;
63 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
64 const iterator RegsBegin, RegsEnd;
66 TargetRegisterClass(unsigned id,
67 const MVT::ValueType *vts,
68 const TargetRegisterClass * const *subcs,
69 const TargetRegisterClass * const *supcs,
70 unsigned RS, unsigned Al, iterator RB, iterator RE)
71 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
72 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
73 virtual ~TargetRegisterClass() {} // Allow subclasses
75 /// getID() - Return the register class ID number.
77 unsigned getID() const { return ID; }
79 /// begin/end - Return all of the registers in this class.
81 iterator begin() const { return RegsBegin; }
82 iterator end() const { return RegsEnd; }
84 /// getNumRegs - Return the number of registers in this class.
86 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
88 /// getRegister - Return the specified register in the class.
90 unsigned getRegister(unsigned i) const {
91 assert(i < getNumRegs() && "Register number out of range!");
95 /// contains - Return true if the specified register is included in this
97 bool contains(unsigned Reg) const {
98 for (iterator I = begin(), E = end(); I != E; ++I)
99 if (*I == Reg) return true;
103 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
105 bool hasType(MVT::ValueType vt) const {
106 for(int i = 0; VTs[i] != MVT::Other; ++i)
112 /// vt_begin / vt_end - Loop over all of the value types that can be
113 /// represented by values in this register class.
114 vt_iterator vt_begin() const {
118 vt_iterator vt_end() const {
120 while (*I != MVT::Other) ++I;
124 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
125 /// sub-register class of this TargetRegisterClass.
126 bool hasSubRegClass(const TargetRegisterClass *cs) const {
127 for (int i = 0; SubClasses[i] != NULL; ++i)
128 if (SubClasses[i] == cs)
133 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
134 /// this register class.
135 sc_iterator subclasses_begin() const {
139 sc_iterator subclasses_end() const {
140 sc_iterator I = SubClasses;
141 while (*I != NULL) ++I;
145 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
146 /// super-register class of this TargetRegisterClass.
147 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
148 for (int i = 0; SuperClasses[i] != NULL; ++i)
149 if (SuperClasses[i] == cs)
154 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
155 /// of this register class.
156 sc_iterator superclasses_begin() const {
160 sc_iterator superclasses_end() const {
161 sc_iterator I = SuperClasses;
162 while (*I != NULL) ++I;
166 /// allocation_order_begin/end - These methods define a range of registers
167 /// which specify the registers in this class that are valid to register
168 /// allocate, and the preferred order to allocate them in. For example,
169 /// callee saved registers should be at the end of the list, because it is
170 /// cheaper to allocate caller saved registers.
172 /// These methods take a MachineFunction argument, which can be used to tune
173 /// the allocatable registers based on the characteristics of the function.
174 /// One simple example is that the frame pointer register can be used if
175 /// frame-pointer-elimination is performed.
177 /// By default, these methods return all registers in the class.
179 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
182 virtual iterator allocation_order_end(const MachineFunction &MF) const {
188 /// getSize - Return the size of the register in bytes, which is also the size
189 /// of a stack slot allocated to hold a spilled copy of this register.
190 unsigned getSize() const { return RegSize; }
192 /// getAlignment - Return the minimum required alignment for a register of
194 unsigned getAlignment() const { return Alignment; }
198 /// MRegisterInfo base class - We assume that the target defines a static array
199 /// of TargetRegisterDesc objects that represent all of the machine registers
200 /// that the target has. As such, we simply have to track a pointer to this
201 /// array so that we can turn register number into a register descriptor.
203 class MRegisterInfo {
205 typedef const TargetRegisterClass * const * regclass_iterator;
207 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
208 unsigned NumRegs; // Number of entries in the array
210 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
212 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
214 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
215 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
216 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
217 virtual ~MRegisterInfo();
220 enum { // Define some target independent constants
221 /// NoRegister - This physical register is not a real target register. It
222 /// is useful as a sentinal.
225 /// FirstVirtualRegister - This is the first register number that is
226 /// considered to be a 'virtual' register, which is part of the SSA
227 /// namespace. This must be the same for all targets, which means that each
228 /// target is limited to 1024 registers.
229 FirstVirtualRegister = 1024
232 /// isPhysicalRegister - Return true if the specified register number is in
233 /// the physical register namespace.
234 static bool isPhysicalRegister(unsigned Reg) {
235 assert(Reg && "this is not a register!");
236 return Reg < FirstVirtualRegister;
239 /// isVirtualRegister - Return true if the specified register number is in
240 /// the virtual register namespace.
241 static bool isVirtualRegister(unsigned Reg) {
242 assert(Reg && "this is not a register!");
243 return Reg >= FirstVirtualRegister;
246 /// getAllocatableSet - Returns a bitset indexed by register number
247 /// indicating if a register is allocatable or not. If a register class is
248 /// specified, returns the subset for the class.
249 BitVector getAllocatableSet(MachineFunction &MF,
250 const TargetRegisterClass *RC = NULL) const;
252 const TargetRegisterDesc &operator[](unsigned RegNo) const {
253 assert(RegNo < NumRegs &&
254 "Attempting to access record for invalid register number!");
258 /// Provide a get method, equivalent to [], but more useful if we have a
259 /// pointer to this object.
261 const TargetRegisterDesc &get(unsigned RegNo) const {
262 return operator[](RegNo);
265 /// getAliasSet - Return the set of registers aliased by the specified
266 /// register, or a null list of there are none. The list returned is zero
269 const unsigned *getAliasSet(unsigned RegNo) const {
270 return get(RegNo).AliasSet;
273 /// getSubRegisters - Return the set of registers that are sub-registers of
274 // the specified register, or a null list of there are none. The list
275 /// returned is zero terminated.
277 const unsigned *getSubRegisters(unsigned RegNo) const {
278 return get(RegNo).SubRegs;
281 /// getName - Return the symbolic target specific name for the specified
282 /// physical register.
283 const char *getName(unsigned RegNo) const {
284 return get(RegNo).Name;
287 /// getNumRegs - Return the number of registers this target has
288 /// (useful for sizing arrays holding per register information)
289 unsigned getNumRegs() const {
293 /// areAliases - Returns true if the two registers alias each other,
295 bool areAliases(unsigned regA, unsigned regB) const {
296 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
297 if (*Alias == regB) return true;
301 /// regsOverlap - Returns true if the two registers are equal or alias
302 /// each other. The registers may be virtual register.
303 bool regsOverlap(unsigned regA, unsigned regB) const {
307 if (isVirtualRegister(regA) || isVirtualRegister(regB))
309 return areAliases(regA, regB);
312 /// getCalleeSavedRegs - Return a null-terminated list of all of the
313 /// callee saved registers on this target. The register should be in the
314 /// order of desired callee-save stack frame offset. The first register is
315 /// closed to the incoming stack pointer if stack grows down, and vice versa.
316 virtual const unsigned* getCalleeSavedRegs() const = 0;
318 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
319 /// register classes to spill each callee saved register with. The order and
320 /// length of this list match the getCalleeSaveRegs() list.
321 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
323 /// getReservedRegs - Returns a bitset indexed by physical register number
324 /// indicating if a register is a special register that has particular uses and
325 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
326 /// register scavenger to determine what registers are free.
327 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
329 //===--------------------------------------------------------------------===//
330 // Register Class Information
333 /// Register class iterators
335 regclass_iterator regclass_begin() const { return RegClassBegin; }
336 regclass_iterator regclass_end() const { return RegClassEnd; }
338 unsigned getNumRegClasses() const {
339 return regclass_end()-regclass_begin();
342 /// getRegClass - Returns the register class associated with the enumeration
343 /// value. See class TargetOperandInfo.
344 const TargetRegisterClass *getRegClass(unsigned i) const {
345 assert(i <= getNumRegClasses() && "Register Class ID out of range");
346 return i ? RegClassBegin[i - 1] : NULL;
349 //===--------------------------------------------------------------------===//
350 // Interfaces used by the register allocator and stack frame
351 // manipulation passes to move data around between registers,
352 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
355 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
356 /// registers and returns true if it isn't possible / profitable to do so by
357 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
359 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator MI,
361 const std::vector<CalleeSavedInfo> &CSI) const {
365 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
366 /// saved registers and returns true if it isn't possible / profitable to do
367 /// so by issuing a series of load instructions via loadRegToStackSlot().
368 /// Returns false otherwise.
369 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
370 MachineBasicBlock::iterator MI,
371 const std::vector<CalleeSavedInfo> &CSI) const {
375 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
376 MachineBasicBlock::iterator MI,
377 unsigned SrcReg, int FrameIndex,
378 const TargetRegisterClass *RC) const = 0;
380 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator MI,
382 unsigned DestReg, int FrameIndex,
383 const TargetRegisterClass *RC) const = 0;
385 virtual void copyRegToReg(MachineBasicBlock &MBB,
386 MachineBasicBlock::iterator MI,
387 unsigned DestReg, unsigned SrcReg,
388 const TargetRegisterClass *RC) const = 0;
390 /// reMaterialize - Re-issue the specified 'original' instruction at the
391 /// specific location targeting a new destination register.
392 virtual void reMaterialize(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MI,
395 const MachineInstr *Orig) const = 0;
397 /// foldMemoryOperand - Attempt to fold a load or store of the
398 /// specified stack slot into the specified machine instruction for
399 /// the specified operand. If this is possible, a new instruction
400 /// is returned with the specified operand folded, otherwise NULL is
401 /// returned. The client is responsible for removing the old
402 /// instruction and adding the new one in the instruction stream
403 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
405 int FrameIndex) const {
409 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
410 /// for rounding up the stack frame (probably at emitPrologue time).
411 virtual bool targetHandlesStackFrameRounding() const {
415 /// requiresRegisterScavenging - returns true if the target requires (and
416 /// can make use of) the register scavenger.
417 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
421 /// hasFP - Return true if the specified function should have a dedicated frame
422 /// pointer register. For most targets this is true only if the function has
423 /// variable sized allocas or if frame pointer elimination is disabled.
424 virtual bool hasFP(const MachineFunction &MF) const = 0;
426 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
427 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
428 /// targets use pseudo instructions in order to abstract away the difference
429 /// between operating with a frame pointer and operating without, through the
430 /// use of these two instructions.
432 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
433 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
436 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
437 /// code insertion to eliminate call frame setup and destroy pseudo
438 /// instructions (but only if the Target is using them). It is responsible
439 /// for eliminating these instructions, replacing them with concrete
440 /// instructions. This method need only be implemented if using call frame
441 /// setup/destroy pseudo instructions.
444 eliminateCallFramePseudoInstr(MachineFunction &MF,
445 MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator MI) const {
447 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
448 "eliminateCallFramePseudoInstr must be implemented if using"
449 " call frame setup/destroy pseudo instructions!");
450 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
453 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
454 /// before PrologEpilogInserter scans the physical registers used to determine
455 /// what callee saved registers should be spilled. This method is optional.
456 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
457 RegScavenger *RS = NULL) const {
461 /// processFunctionBeforeFrameFinalized - This method is called immediately
462 /// before the specified functions frame layout (MF.getFrameInfo()) is
463 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
464 /// replaced with direct constants. This method is optional.
466 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
469 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
470 /// frame indices from instructions which may use them. The instruction
471 /// referenced by the iterator contains an MO_FrameIndex operand which must be
472 /// eliminated by this method. This method may modify or replace the
473 /// specified instruction, as long as it keeps the iterator pointing the the
474 /// finished product. The return value is the number of instructions
475 /// added to (negative if removed from) the basic block.
477 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
478 RegScavenger *RS = NULL) const = 0;
480 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
481 /// the function. The return value is the number of instructions
482 /// added to (negative if removed from) the basic block (entry for prologue).
484 virtual void emitPrologue(MachineFunction &MF) const = 0;
485 virtual void emitEpilogue(MachineFunction &MF,
486 MachineBasicBlock &MBB) const = 0;
488 //===--------------------------------------------------------------------===//
489 /// Debug information queries.
491 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
492 /// number. Returns -1 if there is no equivalent value.
493 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
495 /// getFrameRegister - This method should return the register used as a base
496 /// for values allocated in the current stack frame.
497 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
499 /// getRARegister - This method should return the register where the return
500 /// address can be found.
501 virtual unsigned getRARegister() const = 0;
503 /// getLocation - This method should return the actual location of a frame
504 /// variable given the frame index. The location is returned in ML.
505 /// Subclasses should override this method for special handling of frame
506 /// variables and call MRegisterInfo::getLocation for the default action.
507 virtual void getLocation(MachineFunction &MF, unsigned Index,
508 MachineLocation &ML) const;
510 /// getInitialFrameState - Returns a list of machine moves that are assumed
511 /// on entry to all functions. Note that LabelID is ignored (assumed to be
512 /// the beginning of the function.)
513 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
516 // This is useful when building IndexedMaps keyed on virtual registers
517 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
518 unsigned operator()(unsigned Reg) const {
519 return Reg - MRegisterInfo::FirstVirtualRegister;
523 } // End llvm namespace