1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
26 class MachineFunction;
29 /// MRegisterDesc - This record contains all of the information known about a
30 /// particular register. The AliasSet field (if not null) contains a pointer to
31 /// a Zero terminated array of registers that this register aliases. This is
32 /// needed for architectures like X86 which have AL alias AX alias EAX.
33 /// Registers that this does not apply to simply should set this to null.
35 struct MRegisterDesc {
36 const char *Name; // Assembly language name for the register
37 const unsigned *AliasSet; // Register Alias Set, described above
38 unsigned Flags; // Flags identifying register properties (below)
39 unsigned TSFlags; // Target Specific Flags
42 class TargetRegisterClass {
44 typedef const unsigned* iterator;
45 typedef const unsigned* const_iterator;
48 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
49 const iterator RegsBegin, RegsEnd;
51 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
52 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
53 virtual ~TargetRegisterClass() {} // Allow subclasses
55 // begin/end - Return all of the registers in this class.
56 iterator begin() const { return RegsBegin; }
57 iterator end() const { return RegsEnd; }
59 // getNumRegs - Return the number of registers in this class
60 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
62 // getRegister - Return the specified register in the class
63 unsigned getRegister(unsigned i) const {
64 assert(i < getNumRegs() && "Register number out of range!");
68 /// contains - Return true if the specified register is included in this
70 bool contains(unsigned Reg) const {
71 for (iterator I = begin(), E = end(); I != E; ++I)
72 if (*I == Reg) return true;
76 /// allocation_order_begin/end - These methods define a range of registers
77 /// which specify the registers in this class that are valid to register
78 /// allocate, and the preferred order to allocate them in. For example,
79 /// callee saved registers should be at the end of the list, because it is
80 /// cheaper to allocate caller saved registers.
82 /// These methods take a MachineFunction argument, which can be used to tune
83 /// the allocatable registers based on the characteristics of the function.
84 /// One simple example is that the frame pointer register can be used if
85 /// frame-pointer-elimination is performed.
87 /// By default, these methods return all registers in the class.
89 virtual iterator allocation_order_begin(MachineFunction &MF) const {
92 virtual iterator allocation_order_end(MachineFunction &MF) const {
98 /// getSize - Return the size of the register in bytes, which is also the size
99 /// of a stack slot allocated to hold a spilled copy of this register.
100 unsigned getSize() const { return RegSize; }
102 /// getAlignment - Return the minimum required alignment for a register of
104 unsigned getAlignment() const { return Alignment; }
108 /// MRegisterInfo base class - We assume that the target defines a static array
109 /// of MRegisterDesc objects that represent all of the machine registers that
110 /// the target has. As such, we simply have to track a pointer to this array so
111 /// that we can turn register number into a register descriptor.
113 class MRegisterInfo {
115 typedef const TargetRegisterClass * const * regclass_iterator;
117 const MRegisterDesc *Desc; // Pointer to the descriptor array
118 unsigned NumRegs; // Number of entries in the array
120 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
122 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
123 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
125 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
126 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
127 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
128 virtual ~MRegisterInfo();
131 enum { // Define some target independent constants
132 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
133 /// This is used as the destination register for instructions that do not
134 /// produce a value. Some frontends may use this as an operand register to
135 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
136 /// which always PRODUCES the value 0. The X86 backend does not use this
137 /// value as an operand register, except for memory references.
141 /// FirstVirtualRegister - This is the first register number that is
142 /// considered to be a 'virtual' register, which is part of the SSA
143 /// namespace. This must be the same for all targets, which means that each
144 /// target is limited to 1024 registers.
146 FirstVirtualRegister = 1024,
149 /// isPhysicalRegister - Return true if the specified register number is in
150 /// the physical register namespace.
151 static bool isPhysicalRegister(unsigned Reg) {
152 assert(Reg && "this is not a register!");
153 return Reg < FirstVirtualRegister;
156 /// isVirtualRegister - Return true if the specified register number is in
157 /// the virtual register namespace.
158 static bool isVirtualRegister(unsigned Reg) {
159 assert(Reg && "this is not a register!");
160 return Reg >= FirstVirtualRegister;
163 const MRegisterDesc &operator[](unsigned RegNo) const {
164 assert(RegNo < NumRegs &&
165 "Attempting to access record for invalid register number!");
169 /// Provide a get method, equivalent to [], but more useful if we have a
170 /// pointer to this object.
172 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
174 /// getRegClass - Return the register class for the specified physical
177 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
178 assert(RegNo < NumRegs && "Register number out of range!");
179 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
180 return PhysRegClasses[RegNo];
183 /// getAliasSet - Return the set of registers aliased by the specified
184 /// register, or a null list of there are none. The list returned is zero
187 const unsigned *getAliasSet(unsigned RegNo) const {
188 return get(RegNo).AliasSet;
191 /// getName - Return the symbolic target specific name for the specified
192 /// physical register.
193 const char *getName(unsigned RegNo) const {
194 return get(RegNo).Name;
197 /// getNumRegs - Return the number of registers this target has
198 /// (useful for sizing arrays holding per register information)
199 unsigned getNumRegs() const {
203 /// areAliases - Returns true if the two registers alias each other,
205 bool areAliases(unsigned regA, unsigned regB) const {
206 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
207 if (*Alias == regB) return true;
211 virtual const unsigned* getCalleeSaveRegs() const = 0;
214 //===--------------------------------------------------------------------===//
215 // Register Class Information
218 /// Register class iterators
220 regclass_iterator regclass_begin() const { return RegClassBegin; }
221 regclass_iterator regclass_end() const { return RegClassEnd; }
223 unsigned getNumRegClasses() const {
224 return regclass_end()-regclass_begin();
227 //===--------------------------------------------------------------------===//
228 // Interfaces used by the register allocator and stack frame
229 // manipulation passes to move data around between registers,
230 // immediates and memory. The return value is the number of
231 // instructions added to (negative if removed from) the basic block.
234 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
235 MachineBasicBlock::iterator MI,
236 unsigned SrcReg, int FrameIndex) const = 0;
238 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
239 MachineBasicBlock::iterator MI,
240 unsigned DestReg, int FrameIndex) const = 0;
242 virtual void copyRegToReg(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator MI,
244 unsigned DestReg, unsigned SrcReg,
245 const TargetRegisterClass *RC) const = 0;
248 /// foldMemoryOperand - Attempt to fold a load or store of the
249 /// specified stack slot into the specified machine instruction for
250 /// the specified operand. If this is possible, a new instruction
251 /// is returned with the specified operand folded, otherwise NULL is
252 /// returned. The client is responsible for removing the old
253 /// instruction and adding the new one in the instruction stream
254 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
256 int FrameIndex) const {
260 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
261 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
262 /// targets use pseudo instructions in order to abstract away the difference
263 /// between operating with a frame pointer and operating without, through the
264 /// use of these two instructions.
266 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
267 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
270 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
271 /// code insertion to eliminate call frame setup and destroy pseudo
272 /// instructions (but only if the Target is using them). It is responsible
273 /// for eliminating these instructions, replacing them with concrete
274 /// instructions. This method need only be implemented if using call frame
275 /// setup/destroy pseudo instructions.
278 eliminateCallFramePseudoInstr(MachineFunction &MF,
279 MachineBasicBlock &MBB,
280 MachineBasicBlock::iterator MI) const {
281 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
282 "eliminateCallFramePseudoInstr must be implemented if using"
283 " call frame setup/destroy pseudo instructions!");
284 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
287 /// processFunctionBeforeFrameFinalized - This method is called immediately
288 /// before the specified functions frame layout (MF.getFrameInfo()) is
289 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
290 /// replaced with direct constants. This method is optional. The return value
291 /// is the number of instructions added to (negative if removed from) the
294 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
297 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
298 /// frame indices from instructions which may use them. The instruction
299 /// referenced by the iterator contains an MO_FrameIndex operand which must be
300 /// eliminated by this method. This method may modify or replace the
301 /// specified instruction, as long as it keeps the iterator pointing the the
302 /// finished product. The return value is the number of instructions
303 /// added to (negative if removed from) the basic block.
305 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
307 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
308 /// the function. The return value is the number of instructions
309 /// added to (negative if removed from) the basic block (entry for prologue).
311 virtual void emitPrologue(MachineFunction &MF) const = 0;
312 virtual void emitEpilogue(MachineFunction &MF,
313 MachineBasicBlock &MBB) const = 0;
316 // This is useful when building DenseMaps keyed on virtual registers
317 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
318 unsigned operator()(unsigned Reg) const {
319 return Reg - MRegisterInfo::FirstVirtualRegister;
323 } // End llvm namespace