1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
30 class TargetRegisterClass;
32 /// TargetRegisterDesc - This record contains all of the information known about
33 /// a particular register. The AliasSet field (if not null) contains a pointer
34 /// to a Zero terminated array of registers that this register aliases. This is
35 /// needed for architectures like X86 which have AL alias AX alias EAX.
36 /// Registers that this does not apply to simply should set this to null.
38 struct TargetRegisterDesc {
39 const char *Name; // Assembly language name for the register
40 const unsigned *AliasSet; // Register Alias Set, described above
43 class TargetRegisterClass {
45 typedef const unsigned* iterator;
46 typedef const unsigned* const_iterator;
48 typedef const MVT::ValueType* vt_iterator;
50 const vt_iterator VTs;
51 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
52 const iterator RegsBegin, RegsEnd;
54 TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
55 iterator RB, iterator RE)
56 : VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
57 virtual ~TargetRegisterClass() {} // Allow subclasses
59 // begin/end - Return all of the registers in this class.
60 iterator begin() const { return RegsBegin; }
61 iterator end() const { return RegsEnd; }
63 // getNumRegs - Return the number of registers in this class
64 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
66 // getRegister - Return the specified register in the class
67 unsigned getRegister(unsigned i) const {
68 assert(i < getNumRegs() && "Register number out of range!");
72 /// contains - Return true if the specified register is included in this
74 bool contains(unsigned Reg) const {
75 for (iterator I = begin(), E = end(); I != E; ++I)
76 if (*I == Reg) return true;
80 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
82 bool hasType(MVT::ValueType vt) const {
83 for(int i = 0; VTs[i] != MVT::Other; ++i)
89 /// vt_begin - Loop over all of the value types that can be represented by
90 /// values in this register class.
91 vt_iterator vt_begin() const {
95 /// vt_begin - Loop over all of the value types that can be represented by
96 /// values in this register class.
97 vt_iterator vt_end() const {
99 while (*I != MVT::Other) ++I;
104 /// allocation_order_begin/end - These methods define a range of registers
105 /// which specify the registers in this class that are valid to register
106 /// allocate, and the preferred order to allocate them in. For example,
107 /// callee saved registers should be at the end of the list, because it is
108 /// cheaper to allocate caller saved registers.
110 /// These methods take a MachineFunction argument, which can be used to tune
111 /// the allocatable registers based on the characteristics of the function.
112 /// One simple example is that the frame pointer register can be used if
113 /// frame-pointer-elimination is performed.
115 /// By default, these methods return all registers in the class.
117 virtual iterator allocation_order_begin(MachineFunction &MF) const {
120 virtual iterator allocation_order_end(MachineFunction &MF) const {
126 /// getSize - Return the size of the register in bytes, which is also the size
127 /// of a stack slot allocated to hold a spilled copy of this register.
128 unsigned getSize() const { return RegSize; }
130 /// getAlignment - Return the minimum required alignment for a register of
132 unsigned getAlignment() const { return Alignment; }
136 /// MRegisterInfo base class - We assume that the target defines a static array
137 /// of TargetRegisterDesc objects that represent all of the machine registers
138 /// that the target has. As such, we simply have to track a pointer to this
139 /// array so that we can turn register number into a register descriptor.
141 class MRegisterInfo {
143 typedef const TargetRegisterClass * const * regclass_iterator;
145 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
146 unsigned NumRegs; // Number of entries in the array
148 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
150 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
152 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
153 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
154 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
155 virtual ~MRegisterInfo();
158 enum { // Define some target independent constants
159 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
160 /// This is used as the destination register for instructions that do not
161 /// produce a value. Some frontends may use this as an operand register to
162 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
163 /// which always PRODUCES the value 0. The X86 backend does not use this
164 /// value as an operand register, except for memory references.
168 /// FirstVirtualRegister - This is the first register number that is
169 /// considered to be a 'virtual' register, which is part of the SSA
170 /// namespace. This must be the same for all targets, which means that each
171 /// target is limited to 1024 registers.
173 FirstVirtualRegister = 1024
176 /// isPhysicalRegister - Return true if the specified register number is in
177 /// the physical register namespace.
178 static bool isPhysicalRegister(unsigned Reg) {
179 assert(Reg && "this is not a register!");
180 return Reg < FirstVirtualRegister;
183 /// isVirtualRegister - Return true if the specified register number is in
184 /// the virtual register namespace.
185 static bool isVirtualRegister(unsigned Reg) {
186 assert(Reg && "this is not a register!");
187 return Reg >= FirstVirtualRegister;
190 /// getAllocatableSet - Returns a bitset indexed by register number
191 /// indicating if a register is allocatable or not.
192 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
194 const TargetRegisterDesc &operator[](unsigned RegNo) const {
195 assert(RegNo < NumRegs &&
196 "Attempting to access record for invalid register number!");
200 /// Provide a get method, equivalent to [], but more useful if we have a
201 /// pointer to this object.
203 const TargetRegisterDesc &get(unsigned RegNo) const {
204 return operator[](RegNo);
207 /// getAliasSet - Return the set of registers aliased by the specified
208 /// register, or a null list of there are none. The list returned is zero
211 const unsigned *getAliasSet(unsigned RegNo) const {
212 return get(RegNo).AliasSet;
215 /// getName - Return the symbolic target specific name for the specified
216 /// physical register.
217 const char *getName(unsigned RegNo) const {
218 return get(RegNo).Name;
221 /// getNumRegs - Return the number of registers this target has
222 /// (useful for sizing arrays holding per register information)
223 unsigned getNumRegs() const {
227 /// areAliases - Returns true if the two registers alias each other,
229 bool areAliases(unsigned regA, unsigned regB) const {
230 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
231 if (*Alias == regB) return true;
235 /// getCalleeSaveRegs - Return a null-terminated list of all of the
236 /// callee-save registers on this target.
237 virtual const unsigned* getCalleeSaveRegs() const = 0;
239 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
240 /// register classes to spill each callee-saved register with. The order and
241 /// length of this list match the getCalleeSaveRegs() list.
242 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
244 //===--------------------------------------------------------------------===//
245 // Register Class Information
248 /// Register class iterators
250 regclass_iterator regclass_begin() const { return RegClassBegin; }
251 regclass_iterator regclass_end() const { return RegClassEnd; }
253 unsigned getNumRegClasses() const {
254 return regclass_end()-regclass_begin();
257 //===--------------------------------------------------------------------===//
258 // Interfaces used by the register allocator and stack frame
259 // manipulation passes to move data around between registers,
260 // immediates and memory. The return value is the number of
261 // instructions added to (negative if removed from) the basic block.
264 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
265 MachineBasicBlock::iterator MI,
266 unsigned SrcReg, int FrameIndex,
267 const TargetRegisterClass *RC) const = 0;
269 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator MI,
271 unsigned DestReg, int FrameIndex,
272 const TargetRegisterClass *RC) const = 0;
274 virtual void copyRegToReg(MachineBasicBlock &MBB,
275 MachineBasicBlock::iterator MI,
276 unsigned DestReg, unsigned SrcReg,
277 const TargetRegisterClass *RC) const = 0;
279 /// foldMemoryOperand - Attempt to fold a load or store of the
280 /// specified stack slot into the specified machine instruction for
281 /// the specified operand. If this is possible, a new instruction
282 /// is returned with the specified operand folded, otherwise NULL is
283 /// returned. The client is responsible for removing the old
284 /// instruction and adding the new one in the instruction stream
285 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
287 int FrameIndex) const {
291 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
292 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
293 /// targets use pseudo instructions in order to abstract away the difference
294 /// between operating with a frame pointer and operating without, through the
295 /// use of these two instructions.
297 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
298 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
301 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
302 /// code insertion to eliminate call frame setup and destroy pseudo
303 /// instructions (but only if the Target is using them). It is responsible
304 /// for eliminating these instructions, replacing them with concrete
305 /// instructions. This method need only be implemented if using call frame
306 /// setup/destroy pseudo instructions.
309 eliminateCallFramePseudoInstr(MachineFunction &MF,
310 MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator MI) const {
312 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
313 "eliminateCallFramePseudoInstr must be implemented if using"
314 " call frame setup/destroy pseudo instructions!");
315 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
318 /// processFunctionBeforeFrameFinalized - This method is called immediately
319 /// before the specified functions frame layout (MF.getFrameInfo()) is
320 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
321 /// replaced with direct constants. This method is optional. The return value
322 /// is the number of instructions added to (negative if removed from) the
325 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
328 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
329 /// frame indices from instructions which may use them. The instruction
330 /// referenced by the iterator contains an MO_FrameIndex operand which must be
331 /// eliminated by this method. This method may modify or replace the
332 /// specified instruction, as long as it keeps the iterator pointing the the
333 /// finished product. The return value is the number of instructions
334 /// added to (negative if removed from) the basic block.
336 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
338 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
339 /// the function. The return value is the number of instructions
340 /// added to (negative if removed from) the basic block (entry for prologue).
342 virtual void emitPrologue(MachineFunction &MF) const = 0;
343 virtual void emitEpilogue(MachineFunction &MF,
344 MachineBasicBlock &MBB) const = 0;
346 /// getLocation - This method should return the actual location of a frame
347 /// variable given the frame index.
348 virtual void getLocation(MachineFunction &MF, unsigned Index,
349 MachineLocation &ML) const = 0;
352 // This is useful when building DenseMaps keyed on virtual registers
353 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
354 unsigned operator()(unsigned Reg) const {
355 return Reg - MRegisterInfo::FirstVirtualRegister;
359 } // End llvm namespace