1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "llvm/Target/TargetMachine.h"
11 #include "llvm/Support/DataTypes.h"
14 class MachineInstrDescriptor;
21 typedef int InstrSchedClass;
23 // Global variable holding an array of descriptors for machine instructions.
24 // The actual object needs to be created separately for each target machine.
25 // This variable is initialized and reset by class MachineInstrInfo.
27 // FIXME: This should be a property of the target so that more than one target
28 // at a time can be active...
30 extern const MachineInstrDescriptor *TargetInstrDescriptors;
33 //---------------------------------------------------------------------------
34 // struct MachineInstrDescriptor:
35 // Predefined information about each machine instruction.
36 // Designed to initialized statically.
38 // class MachineInstructionInfo
39 // Interface to description of machine instructions
41 //---------------------------------------------------------------------------
44 const unsigned int M_NOP_FLAG = 1;
45 const unsigned int M_BRANCH_FLAG = 1 << 1;
46 const unsigned int M_CALL_FLAG = 1 << 2;
47 const unsigned int M_RET_FLAG = 1 << 3;
48 const unsigned int M_ARITH_FLAG = 1 << 4;
49 const unsigned int M_CC_FLAG = 1 << 6;
50 const unsigned int M_LOGICAL_FLAG = 1 << 6;
51 const unsigned int M_INT_FLAG = 1 << 7;
52 const unsigned int M_FLOAT_FLAG = 1 << 8;
53 const unsigned int M_CONDL_FLAG = 1 << 9;
54 const unsigned int M_LOAD_FLAG = 1 << 10;
55 const unsigned int M_PREFETCH_FLAG = 1 << 11;
56 const unsigned int M_STORE_FLAG = 1 << 12;
57 const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
60 struct MachineInstrDescriptor {
61 string opCodeString; // Assembly language mnemonic for the opcode.
62 int numOperands; // Number of args; -1 if variable #args
63 int resultPos; // Position of the result; -1 if no result
64 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
65 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
66 // smallest -ve value is -(maxImmedConst+1).
67 unsigned int numDelaySlots; // Number of delay slots after instruction
68 unsigned int latency; // Latency in machine cycles
69 InstrSchedClass schedClass; // enum identifying instr sched class
70 unsigned int iclass; // flags identifying machine instr class
74 class MachineInstrInfo : public NonCopyableV {
76 const MachineInstrDescriptor* desc; // raw array to allow static init'n
77 unsigned int descSize; // number of entries in the desc array
78 unsigned int numRealOpCodes; // number of non-dummy op codes
81 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
82 unsigned numRealOpCodes);
83 virtual ~MachineInstrInfo();
85 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
86 unsigned getNumTotalOpCodes() const { return descSize; }
88 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
89 assert(opCode >= 0 && opCode < (int)descSize);
93 int getNumOperands(MachineOpCode opCode) const {
94 return getDescriptor(opCode).numOperands;
97 int getResultPos(MachineOpCode opCode) const {
98 return getDescriptor(opCode).resultPos;
101 unsigned getNumDelaySlots(MachineOpCode opCode) const {
102 return getDescriptor(opCode).numDelaySlots;
105 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
106 return getDescriptor(opCode).schedClass;
110 // Query instruction class flags according to the machine-independent
111 // flags listed above.
113 unsigned int getIClass(MachineOpCode opCode) const {
114 return getDescriptor(opCode).iclass;
116 bool isNop(MachineOpCode opCode) const {
117 return getDescriptor(opCode).iclass & M_NOP_FLAG;
119 bool isBranch(MachineOpCode opCode) const {
120 return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
122 bool isCall(MachineOpCode opCode) const {
123 return getDescriptor(opCode).iclass & M_CALL_FLAG;
125 bool isReturn(MachineOpCode opCode) const {
126 return getDescriptor(opCode).iclass & M_RET_FLAG;
128 bool isControlFlow(MachineOpCode opCode) const {
129 return getDescriptor(opCode).iclass & M_BRANCH_FLAG
130 || getDescriptor(opCode).iclass & M_CALL_FLAG
131 || getDescriptor(opCode).iclass & M_RET_FLAG;
133 bool isArith(MachineOpCode opCode) const {
134 return getDescriptor(opCode).iclass & M_RET_FLAG;
136 bool isCCInstr(MachineOpCode opCode) const {
137 return getDescriptor(opCode).iclass & M_CC_FLAG;
139 bool isLogical(MachineOpCode opCode) const {
140 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
142 bool isIntInstr(MachineOpCode opCode) const {
143 return getDescriptor(opCode).iclass & M_INT_FLAG;
145 bool isFloatInstr(MachineOpCode opCode) const {
146 return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
148 bool isConditional(MachineOpCode opCode) const {
149 return getDescriptor(opCode).iclass & M_CONDL_FLAG;
151 bool isLoad(MachineOpCode opCode) const {
152 return getDescriptor(opCode).iclass & M_LOAD_FLAG;
154 bool isPrefetch(MachineOpCode opCode) const {
155 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
157 bool isLoadOrPrefetch(MachineOpCode opCode) const {
158 return getDescriptor(opCode).iclass & M_LOAD_FLAG
159 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
161 bool isStore(MachineOpCode opCode) const {
162 return getDescriptor(opCode).iclass & M_STORE_FLAG;
164 bool isMemoryAccess(MachineOpCode opCode) const {
165 return getDescriptor(opCode).iclass & M_LOAD_FLAG
166 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG
167 || getDescriptor(opCode).iclass & M_STORE_FLAG;
169 bool isDummyPhiInstr(MachineOpCode opCode) const {
170 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
174 // delete this later *******
175 bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
178 // Check if an instruction can be issued before its operands are ready,
179 // or if a subsequent instruction that uses its result can be issued
180 // before the results are ready.
181 // Default to true since most instructions on many architectures allow this.
183 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
187 virtual bool hasResultInterlock(MachineOpCode opCode) const {
192 // Latencies for individual instructions and instruction pairs
194 virtual int minLatency(MachineOpCode opCode) const {
195 return getDescriptor(opCode).latency;
198 virtual int maxLatency(MachineOpCode opCode) const {
199 return getDescriptor(opCode).latency;
202 // Check if the specified constant fits in the immediate field
203 // of this machine instruction
205 virtual bool constantFitsInImmedField(MachineOpCode opCode,
206 int64_t intValue) const;
208 // Return the largest +ve constant that can be held in the IMMMED field
209 // of this machine instruction.
210 // isSignExtended is set to true if the value is sign-extended before use
211 // (this is true for all immediate fields in SPARC instructions).
212 // Return 0 if the instruction has no IMMED field.
214 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
215 bool &isSignExtended) const {
216 isSignExtended = getDescriptor(opCode).immedIsSignExtended;
217 return getDescriptor(opCode).maxImmedConst;
220 //-------------------------------------------------------------------------
221 // Code generation support for creating individual machine instructions
222 //-------------------------------------------------------------------------
224 // Create an instruction sequence to put the constant `val' into
225 // the virtual register `dest'. `val' may be a ConstPoolVal or a
226 // GlobalValue, viz., the constant address of a global variable or function.
227 // The generated instructions are returned in `minstrVec'.
228 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
230 virtual void CreateCodeToLoadConst(Value* val,
232 vector<MachineInstr*>& minstrVec,
233 vector<TmpInstruction*>& temps) const =0;