1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "Support/NonCopyable.h"
11 #include "Support/DataTypes.h"
15 class MachineInstrDescriptor;
22 class MachineCodeForInstruction;
24 //---------------------------------------------------------------------------
25 // Data types used to define information about a single machine instruction
26 //---------------------------------------------------------------------------
28 typedef int MachineOpCode;
29 typedef int OpCodeMask;
30 typedef int InstrSchedClass;
32 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
35 // Global variable holding an array of descriptors for machine instructions.
36 // The actual object needs to be created separately for each target machine.
37 // This variable is initialized and reset by class MachineInstrInfo.
39 // FIXME: This should be a property of the target so that more than one target
40 // at a time can be active...
42 extern const MachineInstrDescriptor *TargetInstrDescriptors;
45 //---------------------------------------------------------------------------
46 // struct MachineInstrDescriptor:
47 // Predefined information about each machine instruction.
48 // Designed to initialized statically.
50 // class MachineInstructionInfo
51 // Interface to description of machine instructions
53 //---------------------------------------------------------------------------
56 const unsigned int M_NOP_FLAG = 1;
57 const unsigned int M_BRANCH_FLAG = 1 << 1;
58 const unsigned int M_CALL_FLAG = 1 << 2;
59 const unsigned int M_RET_FLAG = 1 << 3;
60 const unsigned int M_ARITH_FLAG = 1 << 4;
61 const unsigned int M_CC_FLAG = 1 << 6;
62 const unsigned int M_LOGICAL_FLAG = 1 << 6;
63 const unsigned int M_INT_FLAG = 1 << 7;
64 const unsigned int M_FLOAT_FLAG = 1 << 8;
65 const unsigned int M_CONDL_FLAG = 1 << 9;
66 const unsigned int M_LOAD_FLAG = 1 << 10;
67 const unsigned int M_PREFETCH_FLAG = 1 << 11;
68 const unsigned int M_STORE_FLAG = 1 << 12;
69 const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
70 const unsigned int M_PSEUDO_FLAG = 1 << 14;
73 struct MachineInstrDescriptor {
74 std::string opCodeString; // Assembly language mnemonic for the opcode.
75 int numOperands; // Number of args; -1 if variable #args
76 int resultPos; // Position of the result; -1 if no result
77 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
78 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
79 // smallest -ve value is -(maxImmedConst+1).
80 unsigned int numDelaySlots; // Number of delay slots after instruction
81 unsigned int latency; // Latency in machine cycles
82 InstrSchedClass schedClass; // enum identifying instr sched class
83 unsigned int iclass; // flags identifying machine instr class
87 class MachineInstrInfo : public NonCopyableV {
89 const TargetMachine& target;
92 const MachineInstrDescriptor* desc; // raw array to allow static init'n
93 unsigned int descSize; // number of entries in the desc array
94 unsigned int numRealOpCodes; // number of non-dummy op codes
97 MachineInstrInfo(const TargetMachine& tgt,
98 const MachineInstrDescriptor *desc, unsigned descSize,
99 unsigned numRealOpCodes);
100 virtual ~MachineInstrInfo();
102 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
103 unsigned getNumTotalOpCodes() const { return descSize; }
105 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
106 assert(opCode >= 0 && opCode < (int)descSize);
110 int getNumOperands(MachineOpCode opCode) const {
111 return getDescriptor(opCode).numOperands;
114 int getResultPos(MachineOpCode opCode) const {
115 return getDescriptor(opCode).resultPos;
118 unsigned getNumDelaySlots(MachineOpCode opCode) const {
119 return getDescriptor(opCode).numDelaySlots;
122 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
123 return getDescriptor(opCode).schedClass;
127 // Query instruction class flags according to the machine-independent
128 // flags listed above.
130 unsigned int getIClass(MachineOpCode opCode) const {
131 return getDescriptor(opCode).iclass;
133 bool isNop(MachineOpCode opCode) const {
134 return getDescriptor(opCode).iclass & M_NOP_FLAG;
136 bool isBranch(MachineOpCode opCode) const {
137 return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
139 bool isCall(MachineOpCode opCode) const {
140 return getDescriptor(opCode).iclass & M_CALL_FLAG;
142 bool isReturn(MachineOpCode opCode) const {
143 return getDescriptor(opCode).iclass & M_RET_FLAG;
145 bool isControlFlow(MachineOpCode opCode) const {
146 return getDescriptor(opCode).iclass & M_BRANCH_FLAG
147 || getDescriptor(opCode).iclass & M_CALL_FLAG
148 || getDescriptor(opCode).iclass & M_RET_FLAG;
150 bool isArith(MachineOpCode opCode) const {
151 return getDescriptor(opCode).iclass & M_RET_FLAG;
153 bool isCCInstr(MachineOpCode opCode) const {
154 return getDescriptor(opCode).iclass & M_CC_FLAG;
156 bool isLogical(MachineOpCode opCode) const {
157 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
159 bool isIntInstr(MachineOpCode opCode) const {
160 return getDescriptor(opCode).iclass & M_INT_FLAG;
162 bool isFloatInstr(MachineOpCode opCode) const {
163 return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
165 bool isConditional(MachineOpCode opCode) const {
166 return getDescriptor(opCode).iclass & M_CONDL_FLAG;
168 bool isLoad(MachineOpCode opCode) const {
169 return getDescriptor(opCode).iclass & M_LOAD_FLAG;
171 bool isPrefetch(MachineOpCode opCode) const {
172 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
174 bool isLoadOrPrefetch(MachineOpCode opCode) const {
175 return getDescriptor(opCode).iclass & M_LOAD_FLAG
176 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
178 bool isStore(MachineOpCode opCode) const {
179 return getDescriptor(opCode).iclass & M_STORE_FLAG;
181 bool isMemoryAccess(MachineOpCode opCode) const {
182 return getDescriptor(opCode).iclass & M_LOAD_FLAG
183 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG
184 || getDescriptor(opCode).iclass & M_STORE_FLAG;
186 bool isDummyPhiInstr(const MachineOpCode opCode) const {
187 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
189 bool isPseudoInstr(const MachineOpCode opCode) const {
190 return getDescriptor(opCode).iclass & M_PSEUDO_FLAG;
193 // Check if an instruction can be issued before its operands are ready,
194 // or if a subsequent instruction that uses its result can be issued
195 // before the results are ready.
196 // Default to true since most instructions on many architectures allow this.
198 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
202 virtual bool hasResultInterlock(MachineOpCode opCode) const {
207 // Latencies for individual instructions and instruction pairs
209 virtual int minLatency(MachineOpCode opCode) const {
210 return getDescriptor(opCode).latency;
213 virtual int maxLatency(MachineOpCode opCode) const {
214 return getDescriptor(opCode).latency;
218 // Which operand holds an immediate constant? Returns -1 if none
220 virtual int getImmedConstantPos(MachineOpCode opCode) const {
221 return -1; // immediate position is machine specific, so say -1 == "none"
224 // Check if the specified constant fits in the immediate field
225 // of this machine instruction
227 virtual bool constantFitsInImmedField(MachineOpCode opCode,
228 int64_t intValue) const;
230 // Return the largest +ve constant that can be held in the IMMMED field
231 // of this machine instruction.
232 // isSignExtended is set to true if the value is sign-extended before use
233 // (this is true for all immediate fields in SPARC instructions).
234 // Return 0 if the instruction has no IMMED field.
236 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
237 bool &isSignExtended) const {
238 isSignExtended = getDescriptor(opCode).immedIsSignExtended;
239 return getDescriptor(opCode).maxImmedConst;
242 //-------------------------------------------------------------------------
243 // Code generation support for creating individual machine instructions
244 //-------------------------------------------------------------------------
246 // Create an instruction sequence to put the constant `val' into
247 // the virtual register `dest'. `val' may be a Constant or a
248 // GlobalValue, viz., the constant address of a global variable or function.
249 // The generated instructions are returned in `mvec'.
250 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
251 // Symbolic constants or constants that must be accessed from memory
252 // are added to the constant pool via MachineCodeForMethod::get(F).
254 virtual void CreateCodeToLoadConst(const TargetMachine& target,
258 std::vector<MachineInstr*>& mvec,
259 MachineCodeForInstruction& mcfi) const=0;
261 // Create an instruction sequence to copy an integer value `val'
262 // to a floating point value `dest' by copying to memory and back.
263 // val must be an integral type. dest must be a Float or Double.
264 // The generated instructions are returned in `mvec'.
265 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
266 // Any stack space required is allocated via mcff.
268 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
272 std::vector<MachineInstr*>& mvec,
273 MachineCodeForInstruction& mcfi)const=0;
275 // Similarly, create an instruction sequence to copy an FP value
276 // `val' to an integer value `dest' by copying to memory and back.
277 // The generated instructions are returned in `mvec'.
278 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
279 // Any stack space required is allocated via mcff.
281 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
285 std::vector<MachineInstr*>& mvec,
286 MachineCodeForInstruction& mcfi)const=0;
288 // Create instruction(s) to copy src to dest, for arbitrary types
289 // The generated instructions are returned in `mvec'.
290 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
291 // Any stack space required is allocated via mcff.
293 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
297 std::vector<MachineInstr*>& mvec,
298 MachineCodeForInstruction& mcfi)const=0;
300 // Create instruction sequence to produce a sign-extended register value
301 // from an arbitrary sized value (sized in bits, not bytes).
302 // The generated instructions are appended to `mvec'.
303 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
304 // Any stack space required is allocated via mcff.
306 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
309 unsigned int srcSizeInBits,
311 std::vector<MachineInstr*>& mvec,
312 MachineCodeForInstruction& mcfi) const=0;
314 // Create instruction sequence to produce a zero-extended register value
315 // from an arbitrary sized value (sized in bits, not bytes).
316 // The generated instructions are appended to `mvec'.
317 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
318 // Any stack space required is allocated via mcff.
320 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
323 unsigned int srcSizeInBits,
325 std::vector<MachineInstr*>& mvec,
326 MachineCodeForInstruction& mcfi) const=0;