1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<int size, int offset = 0> {
26 string Namespace = "";
28 // Size - Size (in bits) of the sub-registers represented by this index.
31 // Offset - Offset of the first bit that is part of this sub-register index.
32 // Set it to -1 if the same index is used to represent sub-registers that can
33 // be at different offsets (for example when using an index to access an
34 // element in a register tuple).
37 // ComposedOf - A list of two SubRegIndex instances, [A, B].
38 // This indicates that this SubRegIndex is the result of composing A and B.
39 // See ComposedSubRegIndex.
40 list<SubRegIndex> ComposedOf = [];
42 // CoveringSubRegIndices - A list of two or more sub-register indexes that
43 // cover this sub-register.
45 // This field should normally be left blank as TableGen can infer it.
47 // TableGen automatically detects sub-registers that straddle the registers
48 // in the SubRegs field of a Register definition. For example:
50 // Q0 = dsub_0 -> D0, dsub_1 -> D1
51 // Q1 = dsub_0 -> D2, dsub_1 -> D3
52 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
53 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
55 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
57 // CoveringSubRegIndices = [dsub_1, dsub_2].
58 list<SubRegIndex> CoveringSubRegIndices = [];
61 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
62 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
63 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
65 !if(!eq(B.Offset, -1), -1,
66 !add(A.Offset, B.Offset)))> {
68 let ComposedOf = [A, B];
71 // RegAltNameIndex - The alternate name set to use for register operands of
72 // this register class when printing.
73 class RegAltNameIndex {
74 string Namespace = "";
76 def NoRegAltName : RegAltNameIndex;
78 // Register - You should define one instance of this class for each register
79 // in the target machine. String n will become the "name" of the register.
80 class Register<string n, list<string> altNames = []> {
81 string Namespace = "";
83 list<string> AltNames = altNames;
85 // Aliases - A list of registers that this register overlaps with. A read or
86 // modification of this register can potentially read or modify the aliased
88 list<Register> Aliases = [];
90 // SubRegs - A list of registers that are parts of this register. Note these
91 // are "immediate" sub-registers and the registers within the list do not
92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
94 list<Register> SubRegs = [];
96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
97 // to address it. Sub-sub-register indices are automatically inherited from
99 list<SubRegIndex> SubRegIndices = [];
101 // RegAltNameIndices - The alternate name indices which are valid for this
103 list<RegAltNameIndex> RegAltNameIndices = [];
105 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
106 // These values can be determined by locating the <target>.h file in the
107 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
108 // order of these names correspond to the enumeration used by gcc. A value of
109 // -1 indicates that the gcc number is undefined and -2 that register number
110 // is invalid for this mode/flavour.
111 list<int> DwarfNumbers = [];
113 // CostPerUse - Additional cost of instructions using this register compared
114 // to other registers in its class. The register allocator will try to
115 // minimize the number of instructions using a register with a CostPerUse.
116 // This is used by the x86-64 and ARM Thumb targets where some registers
117 // require larger instruction encodings.
120 // CoveredBySubRegs - When this bit is set, the value of this register is
121 // completely determined by the value of its sub-registers. For example, the
122 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
123 // covered by its sub-register AX.
124 bit CoveredBySubRegs = 0;
126 // HWEncoding - The target specific hardware encoding for this register.
127 bits<16> HWEncoding = 0;
130 // RegisterWithSubRegs - This can be used to define instances of Register which
131 // need to specify sub-registers.
132 // List "subregs" specifies which registers are sub-registers to this one. This
133 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
134 // This allows the code generator to be careful not to put two values with
135 // overlapping live ranges into registers which alias.
136 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
137 let SubRegs = subregs;
140 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
141 // of Operand's that are legal as type qualifiers in DAG patterns. This should
142 // only ever be used for defining multiclasses that are polymorphic over both
143 // RegisterClass's and other Operand's.
146 // RegisterClass - Now that all of the registers are defined, and aliases
147 // between registers are defined, specify which registers belong to which
148 // register classes. This also defines the default allocation order of
149 // registers by register allocators.
151 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
152 dag regList, RegAltNameIndex idx = NoRegAltName>
154 string Namespace = namespace;
156 // RegType - Specify the list ValueType of the registers in this register
157 // class. Note that all registers in a register class must have the same
158 // ValueTypes. This is a list because some targets permit storing different
159 // types in same register, for example vector values with 128-bit total size,
160 // but different count/size of items, like SSE on x86.
162 list<ValueType> RegTypes = regTypes;
164 // Size - Specify the spill size in bits of the registers. A default value of
165 // zero lets tablgen pick an appropriate size.
168 // Alignment - Specify the alignment required of the registers when they are
169 // stored or loaded to memory.
171 int Alignment = alignment;
173 // CopyCost - This value is used to specify the cost of copying a value
174 // between two registers in this register class. The default value is one
175 // meaning it takes a single instruction to perform the copying. A negative
176 // value means copying is extremely expensive or impossible.
179 // MemberList - Specify which registers are in this class. If the
180 // allocation_order_* method are not specified, this also defines the order of
181 // allocation used by the register allocator.
183 dag MemberList = regList;
185 // AltNameIndex - The alternate register name to use when printing operands
186 // of this register class. Every register in the register class must have
187 // a valid alternate name for the given index.
188 RegAltNameIndex altNameIndex = idx;
190 // isAllocatable - Specify that the register class can be used for virtual
191 // registers and register allocation. Some register classes are only used to
192 // model instruction operand constraints, and should have isAllocatable = 0.
193 bit isAllocatable = 1;
195 // AltOrders - List of alternative allocation orders. The default order is
196 // MemberList itself, and that is good enough for most targets since the
197 // register allocators automatically remove reserved registers and move
198 // callee-saved registers to the end.
199 list<dag> AltOrders = [];
201 // AltOrderSelect - The body of a function that selects the allocation order
202 // to use in a given machine function. The code will be inserted in a
203 // function like this:
205 // static inline unsigned f(const MachineFunction &MF) { ... }
207 // The function should return 0 to select the default order defined by
208 // MemberList, 1 to select the first AltOrders entry and so on.
209 code AltOrderSelect = [{}];
211 // Specify allocation priority for register allocators using a greedy
212 // heuristic. Classes with higher priority values are assigned first. This is
213 // useful as it is sometimes beneficial to assign registers to highly
214 // constrained classes first. The value has to be in the range [0,63].
215 int AllocationPriority = 0;
218 // The memberList in a RegisterClass is a dag of set operations. TableGen
219 // evaluates these set operations and expand them into register lists. These
220 // are the most common operation, see test/TableGen/SetTheory.td for more
221 // examples of what is possible:
223 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
224 // register class, or a sub-expression. This is also the way to simply list
227 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
229 // (and GPR, CSR) - Set intersection. All registers from the first set that are
230 // also in the second set.
232 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
233 // numbered registers. Takes an optional 4th operand which is a stride to use
234 // when generating the sequence.
236 // (shl GPR, 4) - Remove the first N elements.
238 // (trunc GPR, 4) - Truncate after the first N elements.
240 // (rotl GPR, 1) - Rotate N places to the left.
242 // (rotr GPR, 1) - Rotate N places to the right.
244 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
246 // (interleave A, B, ...) - Interleave the elements from each argument list.
248 // All of these operators work on ordered sets, not lists. That means
249 // duplicates are removed from sub-expressions.
251 // Set operators. The rest is defined in TargetSelectionDAG.td.
256 // RegisterTuples - Automatically generate super-registers by forming tuples of
257 // sub-registers. This is useful for modeling register sequence constraints
258 // with pseudo-registers that are larger than the architectural registers.
260 // The sub-register lists are zipped together:
262 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
264 // Generates the same registers as:
266 // let SubRegIndices = [sube, subo] in {
267 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
268 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
271 // The generated pseudo-registers inherit super-classes and fields from their
272 // first sub-register. Most fields from the Register class are inferred, and
273 // the AsmName and Dwarf numbers are cleared.
275 // RegisterTuples instances can be used in other set operations to form
276 // register classes and so on. This is the only way of using the generated
278 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
279 // SubRegs - N lists of registers to be zipped up. Super-registers are
280 // synthesized from the first element of each SubRegs list, the second
281 // element and so on.
282 list<dag> SubRegs = Regs;
284 // SubRegIndices - N SubRegIndex instances. This provides the names of the
285 // sub-registers in the synthesized super-registers.
286 list<SubRegIndex> SubRegIndices = Indices;
290 //===----------------------------------------------------------------------===//
291 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
292 // to the register numbering used by gcc and gdb. These values are used by a
293 // debug information writer to describe where values may be located during
295 class DwarfRegNum<list<int> Numbers> {
296 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
297 // These values can be determined by locating the <target>.h file in the
298 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
299 // order of these names correspond to the enumeration used by gcc. A value of
300 // -1 indicates that the gcc number is undefined and -2 that register number
301 // is invalid for this mode/flavour.
302 list<int> DwarfNumbers = Numbers;
305 // DwarfRegAlias - This class declares that a given register uses the same dwarf
306 // numbers as another one. This is useful for making it clear that the two
307 // registers do have the same number. It also lets us build a mapping
308 // from dwarf register number to llvm register.
309 class DwarfRegAlias<Register reg> {
310 Register DwarfAlias = reg;
313 //===----------------------------------------------------------------------===//
314 // Pull in the common support for scheduling
316 include "llvm/Target/TargetSchedule.td"
318 class Predicate; // Forward def
320 //===----------------------------------------------------------------------===//
321 // Instruction set description - These classes correspond to the C++ classes in
322 // the Target/TargetInstrInfo.h file.
325 string Namespace = "";
327 dag OutOperandList; // An dag containing the MI def operand list.
328 dag InOperandList; // An dag containing the MI use operand list.
329 string AsmString = ""; // The .s format to print the instruction with.
331 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
332 // otherwise, uninitialized.
335 // The follow state will eventually be inferred automatically from the
336 // instruction pattern.
338 list<Register> Uses = []; // Default to using no non-operand registers
339 list<Register> Defs = []; // Default to modifying no non-operand registers
341 // Predicates - List of predicates which will be turned into isel matching
343 list<Predicate> Predicates = [];
345 // Size - Size of encoded instruction, or zero if the size cannot be determined
349 // DecoderNamespace - The "namespace" in which this instruction exists, on
350 // targets like ARM which multiple ISA namespaces exist.
351 string DecoderNamespace = "";
353 // Code size, for instruction selection.
354 // FIXME: What does this actually mean?
357 // Added complexity passed onto matching pattern.
358 int AddedComplexity = 0;
360 // These bits capture information about the high-level semantics of the
362 bit isReturn = 0; // Is this instruction a return instruction?
363 bit isBranch = 0; // Is this instruction a branch instruction?
364 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
365 bit isCompare = 0; // Is this instruction a comparison instruction?
366 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
367 bit isBitcast = 0; // Is this instruction a bitcast instruction?
368 bit isSelect = 0; // Is this instruction a select instruction?
369 bit isBarrier = 0; // Can control flow fall through this instruction?
370 bit isCall = 0; // Is this instruction a call instruction?
371 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
372 bit mayLoad = ?; // Is it possible for this inst to read memory?
373 bit mayStore = ?; // Is it possible for this inst to write memory?
374 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
375 bit isCommutable = 0; // Is this 3 operand instruction commutable?
376 bit isTerminator = 0; // Is this part of the terminator for a basic block?
377 bit isReMaterializable = 0; // Is this instruction re-materializable?
378 bit isPredicable = 0; // Is this instruction predicable?
379 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
380 bit usesCustomInserter = 0; // Pseudo instr needing special help.
381 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
382 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
383 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
384 bit isConvergent = 0; // Is this instruction convergent?
385 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
386 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
387 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
388 bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
389 // If so, make sure to override
390 // TargetInstrInfo::getRegSequenceLikeInputs.
391 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
392 // If so, won't have encoding information for
393 // the [MC]CodeEmitter stuff.
394 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
395 // If so, make sure to override
396 // TargetInstrInfo::getExtractSubregLikeInputs.
397 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
398 // If so, make sure to override
399 // TargetInstrInfo::getInsertSubregLikeInputs.
401 // Side effect flags - When set, the flags have these meanings:
403 // hasSideEffects - The instruction has side effects that are not
404 // captured by any operands of the instruction or other flags.
406 bit hasSideEffects = ?;
408 // Is this instruction a "real" instruction (with a distinct machine
409 // encoding), or is it a pseudo instruction used for codegen modeling
411 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
412 // instructions can (and often do) still have encoding information
413 // associated with them. Once we've migrated all of them over to true
414 // pseudo-instructions that are lowered to real instructions prior to
415 // the printer/emitter, we can remove this attribute and just use isPseudo.
417 // The intended use is:
418 // isPseudo: Does not have encoding information and should be expanded,
419 // at the latest, during lowering to MCInst.
421 // isCodeGenOnly: Does have encoding information and can go through to the
422 // CodeEmitter unchanged, but duplicates a canonical instruction
423 // definition's encoding and should be ignored when constructing the
424 // assembler match tables.
425 bit isCodeGenOnly = 0;
427 // Is this instruction a pseudo instruction for use by the assembler parser.
428 bit isAsmParserOnly = 0;
430 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
432 // Scheduling information from TargetSchedule.td.
433 list<SchedReadWrite> SchedRW;
435 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
437 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
438 /// be encoded into the output machineinstr.
439 string DisableEncoding = "";
441 string PostEncoderMethod = "";
442 string DecoderMethod = "";
444 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
445 bits<64> TSFlags = 0;
447 ///@name Assembler Parser Support
450 string AsmMatchConverter = "";
452 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
453 /// two-operand matcher inst-alias for a three operand instruction.
454 /// For example, the arm instruction "add r3, r3, r5" can be written
455 /// as "add r3, r5". The constraint is of the same form as a tied-operand
456 /// constraint. For example, "$Rn = $Rd".
457 string TwoOperandAliasConstraint = "";
461 /// UseNamedOperandTable - If set, the operand indices of this instruction
462 /// can be queried via the getNamedOperandIdx() function which is generated
464 bit UseNamedOperandTable = 0;
467 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
468 /// Which instruction it expands to and how the operands map from the
470 class PseudoInstExpansion<dag Result> {
471 dag ResultInst = Result; // The instruction to generate.
475 /// Predicates - These are extra conditionals which are turned into instruction
476 /// selector matching code. Currently each predicate is just a string.
477 class Predicate<string cond> {
478 string CondString = cond;
480 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
481 /// matcher, this is true. Targets should set this by inheriting their
482 /// feature from the AssemblerPredicate class in addition to Predicate.
483 bit AssemblerMatcherPredicate = 0;
485 /// AssemblerCondString - Name of the subtarget feature being tested used
486 /// as alternative condition string used for assembler matcher.
487 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
488 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
489 /// It can also list multiple features separated by ",".
490 /// e.g. "ModeThumb,FeatureThumb2" is translated to
491 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
492 string AssemblerCondString = "";
494 /// PredicateName - User-level name to use for the predicate. Mainly for use
495 /// in diagnostics such as missing feature errors in the asm matcher.
496 string PredicateName = "";
499 /// NoHonorSignDependentRounding - This predicate is true if support for
500 /// sign-dependent-rounding is not enabled.
501 def NoHonorSignDependentRounding
502 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
504 class Requires<list<Predicate> preds> {
505 list<Predicate> Predicates = preds;
508 /// ops definition - This is just a simple marker used to identify the operand
509 /// list for an instruction. outs and ins are identical both syntactically and
510 /// semantically; they are used to define def operands and use operands to
511 /// improve readibility. This should be used like this:
512 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
517 /// variable_ops definition - Mark this instruction as taking a variable number
522 /// PointerLikeRegClass - Values that are designed to have pointer width are
523 /// derived from this. TableGen treats the register class as having a symbolic
524 /// type that it doesn't know, and resolves the actual regclass to use by using
525 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
526 class PointerLikeRegClass<int Kind> {
527 int RegClassKind = Kind;
531 /// ptr_rc definition - Mark this operand as being a pointer value whose
532 /// register class is resolved dynamically via a callback to TargetInstrInfo.
533 /// FIXME: We should probably change this to a class which contain a list of
534 /// flags. But currently we have but one flag.
535 def ptr_rc : PointerLikeRegClass<0>;
537 /// unknown definition - Mark this operand as being of unknown type, causing
538 /// it to be resolved by inference in the context it is used.
540 def unknown : unknown_class;
542 /// AsmOperandClass - Representation for the kinds of operands which the target
543 /// specific parser can create and the assembly matcher may need to distinguish.
545 /// Operand classes are used to define the order in which instructions are
546 /// matched, to ensure that the instruction which gets matched for any
547 /// particular list of operands is deterministic.
549 /// The target specific parser must be able to classify a parsed operand into a
550 /// unique class which does not partially overlap with any other classes. It can
551 /// match a subset of some other class, in which case the super class field
552 /// should be defined.
553 class AsmOperandClass {
554 /// The name to use for this class, which should be usable as an enum value.
557 /// The super classes of this operand.
558 list<AsmOperandClass> SuperClasses = [];
560 /// The name of the method on the target specific operand to call to test
561 /// whether the operand is an instance of this class. If not set, this will
562 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
563 /// signature should be:
564 /// bool isFoo() const;
565 string PredicateMethod = ?;
567 /// The name of the method on the target specific operand to call to add the
568 /// target specific operand to an MCInst. If not set, this will default to
569 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
570 /// signature should be:
571 /// void addFooOperands(MCInst &Inst, unsigned N) const;
572 string RenderMethod = ?;
574 /// The name of the method on the target specific operand to call to custom
575 /// handle the operand parsing. This is useful when the operands do not relate
576 /// to immediates or registers and are very instruction specific (as flags to
577 /// set in a processor register, coprocessor number, ...).
578 string ParserMethod = ?;
580 // The diagnostic type to present when referencing this operand in a
581 // match failure error message. By default, use a generic "invalid operand"
582 // diagnostic. The target AsmParser maps these codes to text.
583 string DiagnosticType = "";
586 def ImmAsmOperand : AsmOperandClass {
590 /// Operand Types - These provide the built-in operand types that may be used
591 /// by a target. Targets can optionally provide their own operand types as
592 /// needed, though this should not be needed for RISC targets.
593 class Operand<ValueType ty> : DAGOperand {
595 string PrintMethod = "printOperand";
596 string EncoderMethod = "";
597 string DecoderMethod = "";
598 string OperandType = "OPERAND_UNKNOWN";
599 dag MIOperandInfo = (ops);
601 // MCOperandPredicate - Optionally, a code fragment operating on
602 // const MCOperand &MCOp, and returning a bool, to indicate if
603 // the value of MCOp is valid for the specific subclass of Operand
604 code MCOperandPredicate;
606 // ParserMatchClass - The "match class" that operands of this type fit
607 // in. Match classes are used to define the order in which instructions are
608 // match, to ensure that which instructions gets matched is deterministic.
610 // The target specific parser must be able to classify an parsed operand into
611 // a unique class, which does not partially overlap with any other classes. It
612 // can match a subset of some other class, in which case the AsmOperandClass
613 // should declare the other operand as one of its super classes.
614 AsmOperandClass ParserMatchClass = ImmAsmOperand;
617 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
619 // RegClass - The register class of the operand.
620 RegisterClass RegClass = regclass;
621 // PrintMethod - The target method to call to print register operands of
622 // this type. The method normally will just use an alt-name index to look
623 // up the name to print. Default to the generic printOperand().
624 string PrintMethod = pm;
625 // ParserMatchClass - The "match class" that operands of this type fit
626 // in. Match classes are used to define the order in which instructions are
627 // match, to ensure that which instructions gets matched is deterministic.
629 // The target specific parser must be able to classify an parsed operand into
630 // a unique class, which does not partially overlap with any other classes. It
631 // can match a subset of some other class, in which case the AsmOperandClass
632 // should declare the other operand as one of its super classes.
633 AsmOperandClass ParserMatchClass;
635 string OperandNamespace = "MCOI";
636 string OperandType = "OPERAND_REGISTER";
639 let OperandType = "OPERAND_IMMEDIATE" in {
640 def i1imm : Operand<i1>;
641 def i8imm : Operand<i8>;
642 def i16imm : Operand<i16>;
643 def i32imm : Operand<i32>;
644 def i64imm : Operand<i64>;
646 def f32imm : Operand<f32>;
647 def f64imm : Operand<f64>;
650 /// zero_reg definition - Special node to stand for the zero register.
654 /// All operands which the MC layer classifies as predicates should inherit from
655 /// this class in some manner. This is already handled for the most commonly
656 /// used PredicateOperand, but may be useful in other circumstances.
659 /// OperandWithDefaultOps - This Operand class can be used as the parent class
660 /// for an Operand that needs to be initialized with a default value if
661 /// no value is supplied in a pattern. This class can be used to simplify the
662 /// pattern definitions for instructions that have target specific flags
663 /// encoded as immediate operands.
664 class OperandWithDefaultOps<ValueType ty, dag defaultops>
666 dag DefaultOps = defaultops;
669 /// PredicateOperand - This can be used to define a predicate operand for an
670 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
671 /// AlwaysVal specifies the value of this predicate when set to "always
673 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
674 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
675 let MIOperandInfo = OpTypes;
678 /// OptionalDefOperand - This is used to define a optional definition operand
679 /// for an instruction. DefaultOps is the register the operand represents if
680 /// none is supplied, e.g. zero_reg.
681 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
682 : OperandWithDefaultOps<ty, defaultops> {
683 let MIOperandInfo = OpTypes;
687 // InstrInfo - This class should only be instantiated once to provide parameters
688 // which are global to the target machine.
691 // Target can specify its instructions in either big or little-endian formats.
692 // For instance, while both Sparc and PowerPC are big-endian platforms, the
693 // Sparc manual specifies its instructions in the format [31..0] (big), while
694 // PowerPC specifies them using the format [0..31] (little).
695 bit isLittleEndianEncoding = 0;
697 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
698 // by default, and TableGen will infer their value from the instruction
699 // pattern when possible.
701 // Normally, TableGen will issue an error it it can't infer the value of a
702 // property that hasn't been set explicitly. When guessInstructionProperties
703 // is set, it will guess a safe value instead.
705 // This option is a temporary migration help. It will go away.
706 bit guessInstructionProperties = 1;
708 // TableGen's instruction encoder generator has support for matching operands
709 // to bit-field variables both by name and by position. While matching by
710 // name is preferred, this is currently not possible for complex operands,
711 // and some targets still reply on the positional encoding rules. When
712 // generating a decoder for such targets, the positional encoding rules must
713 // be used by the decoder generator as well.
715 // This option is temporary; it will go away once the TableGen decoder
716 // generator has better support for complex operands and targets have
717 // migrated away from using positionally encoded operands.
718 bit decodePositionallyEncodedOperands = 0;
720 // When set, this indicates that there will be no overlap between those
721 // operands that are matched by ordering (positional operands) and those
724 // This option is temporary; it will go away once the TableGen decoder
725 // generator has better support for complex operands and targets have
726 // migrated away from using positionally encoded operands.
727 bit noNamedPositionallyEncodedOperands = 0;
730 // Standard Pseudo Instructions.
731 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
732 // Only these instructions are allowed in the TargetOpcode namespace.
733 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
734 def PHI : Instruction {
735 let OutOperandList = (outs);
736 let InOperandList = (ins variable_ops);
737 let AsmString = "PHINODE";
739 def INLINEASM : Instruction {
740 let OutOperandList = (outs);
741 let InOperandList = (ins variable_ops);
743 let hasSideEffects = 0; // Note side effect is encoded in an operand.
745 def CFI_INSTRUCTION : Instruction {
746 let OutOperandList = (outs);
747 let InOperandList = (ins i32imm:$id);
750 let isNotDuplicable = 1;
752 def EH_LABEL : Instruction {
753 let OutOperandList = (outs);
754 let InOperandList = (ins i32imm:$id);
757 let isNotDuplicable = 1;
759 def GC_LABEL : Instruction {
760 let OutOperandList = (outs);
761 let InOperandList = (ins i32imm:$id);
764 let isNotDuplicable = 1;
766 def KILL : Instruction {
767 let OutOperandList = (outs);
768 let InOperandList = (ins variable_ops);
770 let hasSideEffects = 0;
772 def EXTRACT_SUBREG : Instruction {
773 let OutOperandList = (outs unknown:$dst);
774 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
776 let hasSideEffects = 0;
778 def INSERT_SUBREG : Instruction {
779 let OutOperandList = (outs unknown:$dst);
780 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
782 let hasSideEffects = 0;
783 let Constraints = "$supersrc = $dst";
785 def IMPLICIT_DEF : Instruction {
786 let OutOperandList = (outs unknown:$dst);
787 let InOperandList = (ins);
789 let hasSideEffects = 0;
790 let isReMaterializable = 1;
791 let isAsCheapAsAMove = 1;
793 def SUBREG_TO_REG : Instruction {
794 let OutOperandList = (outs unknown:$dst);
795 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
797 let hasSideEffects = 0;
799 def COPY_TO_REGCLASS : Instruction {
800 let OutOperandList = (outs unknown:$dst);
801 let InOperandList = (ins unknown:$src, i32imm:$regclass);
803 let hasSideEffects = 0;
804 let isAsCheapAsAMove = 1;
806 def DBG_VALUE : Instruction {
807 let OutOperandList = (outs);
808 let InOperandList = (ins variable_ops);
809 let AsmString = "DBG_VALUE";
810 let hasSideEffects = 0;
812 def REG_SEQUENCE : Instruction {
813 let OutOperandList = (outs unknown:$dst);
814 let InOperandList = (ins unknown:$supersrc, variable_ops);
816 let hasSideEffects = 0;
817 let isAsCheapAsAMove = 1;
819 def COPY : Instruction {
820 let OutOperandList = (outs unknown:$dst);
821 let InOperandList = (ins unknown:$src);
823 let hasSideEffects = 0;
824 let isAsCheapAsAMove = 1;
826 def BUNDLE : Instruction {
827 let OutOperandList = (outs);
828 let InOperandList = (ins variable_ops);
829 let AsmString = "BUNDLE";
831 def LIFETIME_START : Instruction {
832 let OutOperandList = (outs);
833 let InOperandList = (ins i32imm:$id);
834 let AsmString = "LIFETIME_START";
835 let hasSideEffects = 0;
837 def LIFETIME_END : Instruction {
838 let OutOperandList = (outs);
839 let InOperandList = (ins i32imm:$id);
840 let AsmString = "LIFETIME_END";
841 let hasSideEffects = 0;
843 def STACKMAP : Instruction {
844 let OutOperandList = (outs);
845 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
848 let usesCustomInserter = 1;
850 def PATCHPOINT : Instruction {
851 let OutOperandList = (outs unknown:$dst);
852 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
853 i32imm:$nargs, i32imm:$cc, variable_ops);
856 let usesCustomInserter = 1;
858 def STATEPOINT : Instruction {
859 let OutOperandList = (outs);
860 let InOperandList = (ins variable_ops);
861 let usesCustomInserter = 1;
864 let hasSideEffects = 1;
867 def LOAD_STACK_GUARD : Instruction {
868 let OutOperandList = (outs ptr_rc:$dst);
869 let InOperandList = (ins);
871 bit isReMaterializable = 1;
872 let hasSideEffects = 0;
875 def FRAME_ALLOC : Instruction {
876 // This instruction is really just a label. It has to be part of the chain so
877 // that it doesn't get dropped from the DAG, but it produces nothing and has
879 let OutOperandList = (outs);
880 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
881 let hasSideEffects = 0;
884 def FAULTING_LOAD_OP : Instruction {
885 let OutOperandList = (outs unknown:$dst);
886 let InOperandList = (ins variable_ops);
887 let usesCustomInserter = 1;
892 //===----------------------------------------------------------------------===//
893 // AsmParser - This class can be implemented by targets that wish to implement
896 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
897 // syntax on X86 for example).
900 // AsmParserClassName - This specifies the suffix to use for the asmparser
901 // class. Generated AsmParser classes are always prefixed with the target
903 string AsmParserClassName = "AsmParser";
905 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
906 // function of the AsmParser class to call on every matched instruction.
907 // This can be used to perform target specific instruction post-processing.
908 string AsmParserInstCleanup = "";
910 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
911 // written register name matcher
912 bit ShouldEmitMatchRegisterName = 1;
914 /// Does the instruction mnemonic allow '.'
915 bit MnemonicContainsDot = 0;
917 def DefaultAsmParser : AsmParser;
919 //===----------------------------------------------------------------------===//
920 // AsmParserVariant - Subtargets can have multiple different assembly parsers
921 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
922 // implemented by targets to describe such variants.
924 class AsmParserVariant {
925 // Variant - AsmParsers can be of multiple different variants. Variants are
926 // used to support targets that need to parser multiple formats for the
927 // assembly language.
930 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
933 // CommentDelimiter - If given, the delimiter string used to recognize
934 // comments which are hard coded in the .td assembler strings for individual
936 string CommentDelimiter = "";
938 // RegisterPrefix - If given, the token prefix which indicates a register
939 // token. This is used by the matcher to automatically recognize hard coded
940 // register tokens as constrained registers, instead of tokens, for the
941 // purposes of matching.
942 string RegisterPrefix = "";
944 def DefaultAsmParserVariant : AsmParserVariant;
946 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
947 /// matches instructions and aliases.
948 class AssemblerPredicate<string cond, string name = ""> {
949 bit AssemblerMatcherPredicate = 1;
950 string AssemblerCondString = cond;
951 string PredicateName = name;
954 /// TokenAlias - This class allows targets to define assembler token
955 /// operand aliases. That is, a token literal operand which is equivalent
956 /// to another, canonical, token literal. For example, ARM allows:
957 /// vmov.u32 s4, #0 -> vmov.i32, #0
958 /// 'u32' is a more specific designator for the 32-bit integer type specifier
959 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
960 /// def : TokenAlias<".u32", ".i32">;
962 /// This works by marking the match class of 'From' as a subclass of the
963 /// match class of 'To'.
964 class TokenAlias<string From, string To> {
965 string FromToken = From;
969 /// MnemonicAlias - This class allows targets to define assembler mnemonic
970 /// aliases. This should be used when all forms of one mnemonic are accepted
971 /// with a different mnemonic. For example, X86 allows:
972 /// sal %al, 1 -> shl %al, 1
973 /// sal %ax, %cl -> shl %ax, %cl
974 /// sal %eax, %cl -> shl %eax, %cl
975 /// etc. Though "sal" is accepted with many forms, all of them are directly
976 /// translated to a shl, so it can be handled with (in the case of X86, it
977 /// actually has one for each suffix as well):
978 /// def : MnemonicAlias<"sal", "shl">;
980 /// Mnemonic aliases are mapped before any other translation in the match phase,
981 /// and do allow Requires predicates, e.g.:
983 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
984 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
986 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
988 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
990 /// If no variant (e.g., "att" or "intel") is specified then the alias is
991 /// applied unconditionally.
992 class MnemonicAlias<string From, string To, string VariantName = ""> {
993 string FromMnemonic = From;
994 string ToMnemonic = To;
995 string AsmVariantName = VariantName;
997 // Predicates - Predicates that must be true for this remapping to happen.
998 list<Predicate> Predicates = [];
1001 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1002 /// match an instruction that has a different (more canonical) assembly
1004 class InstAlias<string Asm, dag Result, int Emit = 1> {
1005 string AsmString = Asm; // The .s format to match the instruction with.
1006 dag ResultInst = Result; // The MCInst to generate.
1008 // This determines which order the InstPrinter detects aliases for
1009 // printing. A larger value makes the alias more likely to be
1010 // emitted. The Instruction's own definition is notionally 0.5, so 0
1011 // disables printing and 1 enables it if there are no conflicting aliases.
1012 int EmitPriority = Emit;
1014 // Predicates - Predicates that must be true for this to match.
1015 list<Predicate> Predicates = [];
1017 // If the instruction specified in Result has defined an AsmMatchConverter
1018 // then setting this to 1 will cause the alias to use the AsmMatchConverter
1019 // function when converting the OperandVector into an MCInst instead of the
1020 // function that is generated by the dag Result.
1021 // Setting this to 0 will cause the alias to ignore the Result instruction's
1022 // defined AsmMatchConverter and instead use the function generated by the
1024 bit UseInstAsmMatchConverter = 1;
1027 //===----------------------------------------------------------------------===//
1028 // AsmWriter - This class can be implemented by targets that need to customize
1029 // the format of the .s file writer.
1031 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1032 // on X86 for example).
1035 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
1036 // class. Generated AsmWriter classes are always prefixed with the target
1038 string AsmWriterClassName = "InstPrinter";
1040 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1041 // the various print methods.
1042 // FIXME: Remove after all ports are updated.
1043 int PassSubtarget = 0;
1045 // Variant - AsmWriters can be of multiple different variants. Variants are
1046 // used to support targets that need to emit assembly code in ways that are
1047 // mostly the same for different targets, but have minor differences in
1048 // syntax. If the asmstring contains {|} characters in them, this integer
1049 // will specify which alternative to use. For example "{x|y|z}" with Variant
1050 // == 1, will expand to "y".
1053 def DefaultAsmWriter : AsmWriter;
1056 //===----------------------------------------------------------------------===//
1057 // Target - This class contains the "global" target information
1060 // InstructionSet - Instruction set description for this target.
1061 InstrInfo InstructionSet;
1063 // AssemblyParsers - The AsmParser instances available for this target.
1064 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1066 /// AssemblyParserVariants - The AsmParserVariant instances available for
1068 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1070 // AssemblyWriters - The AsmWriter instances available for this target.
1071 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1074 //===----------------------------------------------------------------------===//
1075 // SubtargetFeature - A characteristic of the chip set.
1077 class SubtargetFeature<string n, string a, string v, string d,
1078 list<SubtargetFeature> i = []> {
1079 // Name - Feature name. Used by command line (-mattr=) to determine the
1080 // appropriate target chip.
1084 // Attribute - Attribute to be set by feature.
1086 string Attribute = a;
1088 // Value - Value the attribute to be set to by feature.
1092 // Desc - Feature description. Used by command line (-mattr=) to display help
1097 // Implies - Features that this feature implies are present. If one of those
1098 // features isn't set, then this one shouldn't be set either.
1100 list<SubtargetFeature> Implies = i;
1103 /// Specifies a Subtarget feature that this instruction is deprecated on.
1104 class Deprecated<SubtargetFeature dep> {
1105 SubtargetFeature DeprecatedFeatureMask = dep;
1108 /// A custom predicate used to determine if an instruction is
1109 /// deprecated or not.
1110 class ComplexDeprecationPredicate<string dep> {
1111 string ComplexDeprecationPredicate = dep;
1114 //===----------------------------------------------------------------------===//
1115 // Processor chip sets - These values represent each of the chip sets supported
1116 // by the scheduler. Each Processor definition requires corresponding
1117 // instruction itineraries.
1119 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1120 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1121 // appropriate target chip.
1125 // SchedModel - The machine model for scheduling and instruction cost.
1127 SchedMachineModel SchedModel = NoSchedModel;
1129 // ProcItin - The scheduling information for the target processor.
1131 ProcessorItineraries ProcItin = pi;
1133 // Features - list of
1134 list<SubtargetFeature> Features = f;
1137 // ProcessorModel allows subtargets to specify the more general
1138 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1139 // gradually move to this newer form.
1141 // Although this class always passes NoItineraries to the Processor
1142 // class, the SchedMachineModel may still define valid Itineraries.
1143 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1144 : Processor<n, NoItineraries, f> {
1148 //===----------------------------------------------------------------------===//
1149 // InstrMapping - This class is used to create mapping tables to relate
1150 // instructions with each other based on the values specified in RowFields,
1151 // ColFields, KeyCol and ValueCols.
1153 class InstrMapping {
1154 // FilterClass - Used to limit search space only to the instructions that
1155 // define the relationship modeled by this InstrMapping record.
1158 // RowFields - List of fields/attributes that should be same for all the
1159 // instructions in a row of the relation table. Think of this as a set of
1160 // properties shared by all the instructions related by this relationship
1161 // model and is used to categorize instructions into subgroups. For instance,
1162 // if we want to define a relation that maps 'Add' instruction to its
1163 // predicated forms, we can define RowFields like this:
1165 // let RowFields = BaseOp
1166 // All add instruction predicated/non-predicated will have to set their BaseOp
1167 // to the same value.
1169 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1170 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1171 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1172 list<string> RowFields = [];
1174 // List of fields/attributes that are same for all the instructions
1175 // in a column of the relation table.
1176 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1177 // based on the 'predSense' values. All the instruction in a specific
1178 // column have the same value and it is fixed for the column according
1179 // to the values set in 'ValueCols'.
1180 list<string> ColFields = [];
1182 // Values for the fields/attributes listed in 'ColFields'.
1183 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1184 // that models this relation) should be non-predicated.
1185 // In the example above, 'Add' is the key instruction.
1186 list<string> KeyCol = [];
1188 // List of values for the fields/attributes listed in 'ColFields', one for
1189 // each column in the relation table.
1191 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1192 // table. First column requires all the instructions to have predSense
1193 // set to 'true' and second column requires it to be 'false'.
1194 list<list<string> > ValueCols = [];
1197 //===----------------------------------------------------------------------===//
1198 // Pull in the common support for calling conventions.
1200 include "llvm/Target/TargetCallingConv.td"
1202 //===----------------------------------------------------------------------===//
1203 // Pull in the common support for DAG isel generation.
1205 include "llvm/Target/TargetSelectionDAG.td"