1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // Register - You should define one instance of this class for each register
30 // in the target machine. String n will become the "name" of the register.
31 class Register<string n> {
32 string Namespace = "";
35 // SpillSize - If this value is set to a non-zero value, it is the size in
36 // bits of the spill slot required to hold this register. If this value is
37 // set to zero, the information is inferred from any register classes the
38 // register belongs to.
41 // SpillAlignment - This value is used to specify the alignment required for
42 // spilling the register. Like SpillSize, this should only be explicitly
43 // specified if the register is not in a register class.
44 int SpillAlignment = 0;
46 // Aliases - A list of registers that this register overlaps with. A read or
47 // modification of this register can potentially read or modify the aliased
49 list<Register> Aliases = [];
51 // SubRegs - A list of registers that are parts of this register. Note these
52 // are "immediate" sub-registers and the registers within the list do not
53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
55 list<Register> SubRegs = [];
57 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
58 // to address it. Sub-sub-register indices are automatically inherited from
60 list<SubRegIndex> SubRegIndices = [];
62 // CompositeIndices - Specify subreg indices that don't correspond directly to
63 // a register in SubRegs and are not inherited. The following formats are
66 // (a) Identity - Reg:a == Reg
67 // (a b) Alias - Reg:a == Reg:b
68 // (a b,c) Composite - Reg:a == (Reg:b):c
70 // This can be used to disambiguate a sub-sub-register that exists in more
71 // than one subregister and other weird stuff.
72 list<dag> CompositeIndices = [];
74 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
75 // These values can be determined by locating the <target>.h file in the
76 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
77 // order of these names correspond to the enumeration used by gcc. A value of
78 // -1 indicates that the gcc number is undefined and -2 that register number
79 // is invalid for this mode/flavour.
80 list<int> DwarfNumbers = [];
83 // RegisterWithSubRegs - This can be used to define instances of Register which
84 // need to specify sub-registers.
85 // List "subregs" specifies which registers are sub-registers to this one. This
86 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
87 // This allows the code generator to be careful not to put two values with
88 // overlapping live ranges into registers which alias.
89 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
90 let SubRegs = subregs;
93 // RegisterClass - Now that all of the registers are defined, and aliases
94 // between registers are defined, specify which registers belong to which
95 // register classes. This also defines the default allocation order of
96 // registers by register allocators.
98 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
99 list<Register> regList> {
100 string Namespace = namespace;
102 // RegType - Specify the list ValueType of the registers in this register
103 // class. Note that all registers in a register class must have the same
104 // ValueTypes. This is a list because some targets permit storing different
105 // types in same register, for example vector values with 128-bit total size,
106 // but different count/size of items, like SSE on x86.
108 list<ValueType> RegTypes = regTypes;
110 // Size - Specify the spill size in bits of the registers. A default value of
111 // zero lets tablgen pick an appropriate size.
114 // Alignment - Specify the alignment required of the registers when they are
115 // stored or loaded to memory.
117 int Alignment = alignment;
119 // CopyCost - This value is used to specify the cost of copying a value
120 // between two registers in this register class. The default value is one
121 // meaning it takes a single instruction to perform the copying. A negative
122 // value means copying is extremely expensive or impossible.
125 // MemberList - Specify which registers are in this class. If the
126 // allocation_order_* method are not specified, this also defines the order of
127 // allocation used by the register allocator.
129 list<Register> MemberList = regList;
131 // SubRegClasses - Specify the register class of subregisters as a list of
132 // dags: (RegClass SubRegIndex, SubRegindex, ...)
133 list<dag> SubRegClasses = [];
135 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
136 // code into a generated register class. The normal usage of this is to
137 // overload virtual methods.
138 code MethodProtos = [{}];
139 code MethodBodies = [{}];
143 //===----------------------------------------------------------------------===//
144 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
145 // to the register numbering used by gcc and gdb. These values are used by a
146 // debug information writer to describe where values may be located during
148 class DwarfRegNum<list<int> Numbers> {
149 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
150 // These values can be determined by locating the <target>.h file in the
151 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
152 // order of these names correspond to the enumeration used by gcc. A value of
153 // -1 indicates that the gcc number is undefined and -2 that register number is
154 // invalid for this mode/flavour.
155 list<int> DwarfNumbers = Numbers;
158 //===----------------------------------------------------------------------===//
159 // Pull in the common support for scheduling
161 include "llvm/Target/TargetSchedule.td"
163 class Predicate; // Forward def
165 //===----------------------------------------------------------------------===//
166 // Instruction set description - These classes correspond to the C++ classes in
167 // the Target/TargetInstrInfo.h file.
170 string Namespace = "";
172 dag OutOperandList; // An dag containing the MI def operand list.
173 dag InOperandList; // An dag containing the MI use operand list.
174 string AsmString = ""; // The .s format to print the instruction with.
176 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
177 // otherwise, uninitialized.
180 // The follow state will eventually be inferred automatically from the
181 // instruction pattern.
183 list<Register> Uses = []; // Default to using no non-operand registers
184 list<Register> Defs = []; // Default to modifying no non-operand registers
186 // Predicates - List of predicates which will be turned into isel matching
188 list<Predicate> Predicates = [];
193 // Added complexity passed onto matching pattern.
194 int AddedComplexity = 0;
196 // These bits capture information about the high-level semantics of the
198 bit isReturn = 0; // Is this instruction a return instruction?
199 bit isBranch = 0; // Is this instruction a branch instruction?
200 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
201 bit isBarrier = 0; // Can control flow fall through this instruction?
202 bit isCall = 0; // Is this instruction a call instruction?
203 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
204 bit mayLoad = 0; // Is it possible for this inst to read memory?
205 bit mayStore = 0; // Is it possible for this inst to write memory?
206 bit isTwoAddress = 0; // Is this a two address instruction?
207 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
208 bit isCommutable = 0; // Is this 3 operand instruction commutable?
209 bit isTerminator = 0; // Is this part of the terminator for a basic block?
210 bit isReMaterializable = 0; // Is this instruction re-materializable?
211 bit isPredicable = 0; // Is this instruction predicable?
212 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
213 bit usesCustomInserter = 0; // Pseudo instr needing special help.
214 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
215 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
216 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
217 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
218 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
220 // Side effect flags - When set, the flags have these meanings:
222 // hasSideEffects - The instruction has side effects that are not
223 // captured by any operands of the instruction or other flags.
225 // neverHasSideEffects - Set on an instruction with no pattern if it has no
227 bit hasSideEffects = 0;
228 bit neverHasSideEffects = 0;
230 // Is this instruction a "real" instruction (with a distinct machine
231 // encoding), or is it a pseudo instruction used for codegen modeling
233 bit isCodeGenOnly = 0;
235 // Is this instruction a pseudo instruction for use by the assembler parser.
236 bit isAsmParserOnly = 0;
238 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
240 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
242 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
243 /// be encoded into the output machineinstr.
244 string DisableEncoding = "";
246 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
247 bits<64> TSFlags = 0;
250 /// Predicates - These are extra conditionals which are turned into instruction
251 /// selector matching code. Currently each predicate is just a string.
252 class Predicate<string cond> {
253 string CondString = cond;
256 /// NoHonorSignDependentRounding - This predicate is true if support for
257 /// sign-dependent-rounding is not enabled.
258 def NoHonorSignDependentRounding
259 : Predicate<"!HonorSignDependentRoundingFPMath()">;
261 class Requires<list<Predicate> preds> {
262 list<Predicate> Predicates = preds;
265 /// ops definition - This is just a simple marker used to identify the operands
266 /// list for an instruction. outs and ins are identical both syntatically and
267 /// semantically, they are used to define def operands and use operands to
268 /// improve readibility. This should be used like this:
269 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
274 /// variable_ops definition - Mark this instruction as taking a variable number
279 /// PointerLikeRegClass - Values that are designed to have pointer width are
280 /// derived from this. TableGen treats the register class as having a symbolic
281 /// type that it doesn't know, and resolves the actual regclass to use by using
282 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
283 class PointerLikeRegClass<int Kind> {
284 int RegClassKind = Kind;
288 /// ptr_rc definition - Mark this operand as being a pointer value whose
289 /// register class is resolved dynamically via a callback to TargetInstrInfo.
290 /// FIXME: We should probably change this to a class which contain a list of
291 /// flags. But currently we have but one flag.
292 def ptr_rc : PointerLikeRegClass<0>;
294 /// unknown definition - Mark this operand as being of unknown type, causing
295 /// it to be resolved by inference in the context it is used.
298 /// AsmOperandClass - Representation for the kinds of operands which the target
299 /// specific parser can create and the assembly matcher may need to distinguish.
301 /// Operand classes are used to define the order in which instructions are
302 /// matched, to ensure that the instruction which gets matched for any
303 /// particular list of operands is deterministic.
305 /// The target specific parser must be able to classify a parsed operand into a
306 /// unique class which does not partially overlap with any other classes. It can
307 /// match a subset of some other class, in which case the super class field
308 /// should be defined.
309 class AsmOperandClass {
310 /// The name to use for this class, which should be usable as an enum value.
313 /// The super classes of this operand.
314 list<AsmOperandClass> SuperClasses = [];
316 /// The name of the method on the target specific operand to call to test
317 /// whether the operand is an instance of this class. If not set, this will
318 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
319 /// signature should be:
320 /// bool isFoo() const;
321 string PredicateMethod = ?;
323 /// The name of the method on the target specific operand to call to add the
324 /// target specific operand to an MCInst. If not set, this will default to
325 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
326 /// signature should be:
327 /// void addFooOperands(MCInst &Inst, unsigned N) const;
328 string RenderMethod = ?;
331 def ImmAsmOperand : AsmOperandClass {
335 /// Operand Types - These provide the built-in operand types that may be used
336 /// by a target. Targets can optionally provide their own operand types as
337 /// needed, though this should not be needed for RISC targets.
338 class Operand<ValueType ty> {
340 string PrintMethod = "printOperand";
341 string AsmOperandLowerMethod = ?;
342 dag MIOperandInfo = (ops);
344 // ParserMatchClass - The "match class" that operands of this type fit
345 // in. Match classes are used to define the order in which instructions are
346 // match, to ensure that which instructions gets matched is deterministic.
348 // The target specific parser must be able to classify an parsed operand into
349 // a unique class, which does not partially overlap with any other classes. It
350 // can match a subset of some other class, in which case the AsmOperandClass
351 // should declare the other operand as one of its super classes.
352 AsmOperandClass ParserMatchClass = ImmAsmOperand;
355 def i1imm : Operand<i1>;
356 def i8imm : Operand<i8>;
357 def i16imm : Operand<i16>;
358 def i32imm : Operand<i32>;
359 def i64imm : Operand<i64>;
361 def f32imm : Operand<f32>;
362 def f64imm : Operand<f64>;
364 /// zero_reg definition - Special node to stand for the zero register.
368 /// PredicateOperand - This can be used to define a predicate operand for an
369 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
370 /// AlwaysVal specifies the value of this predicate when set to "always
372 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
374 let MIOperandInfo = OpTypes;
375 dag DefaultOps = AlwaysVal;
378 /// OptionalDefOperand - This is used to define a optional definition operand
379 /// for an instruction. DefaultOps is the register the operand represents if
380 /// none is supplied, e.g. zero_reg.
381 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
383 let MIOperandInfo = OpTypes;
384 dag DefaultOps = defaultops;
388 // InstrInfo - This class should only be instantiated once to provide parameters
389 // which are global to the target machine.
392 // Target can specify its instructions in either big or little-endian formats.
393 // For instance, while both Sparc and PowerPC are big-endian platforms, the
394 // Sparc manual specifies its instructions in the format [31..0] (big), while
395 // PowerPC specifies them using the format [0..31] (little).
396 bit isLittleEndianEncoding = 0;
399 // Standard Pseudo Instructions.
400 let isCodeGenOnly = 1 in {
401 def PHI : Instruction {
402 let OutOperandList = (outs);
403 let InOperandList = (ins variable_ops);
404 let AsmString = "PHINODE";
405 let Namespace = "TargetOpcode";
407 def INLINEASM : Instruction {
408 let OutOperandList = (outs);
409 let InOperandList = (ins variable_ops);
411 let Namespace = "TargetOpcode";
413 def DBG_LABEL : Instruction {
414 let OutOperandList = (outs);
415 let InOperandList = (ins i32imm:$id);
417 let Namespace = "TargetOpcode";
419 let isNotDuplicable = 1;
421 def EH_LABEL : Instruction {
422 let OutOperandList = (outs);
423 let InOperandList = (ins i32imm:$id);
425 let Namespace = "TargetOpcode";
427 let isNotDuplicable = 1;
429 def GC_LABEL : Instruction {
430 let OutOperandList = (outs);
431 let InOperandList = (ins i32imm:$id);
433 let Namespace = "TargetOpcode";
435 let isNotDuplicable = 1;
437 def KILL : Instruction {
438 let OutOperandList = (outs);
439 let InOperandList = (ins variable_ops);
441 let Namespace = "TargetOpcode";
442 let neverHasSideEffects = 1;
444 def EXTRACT_SUBREG : Instruction {
445 let OutOperandList = (outs unknown:$dst);
446 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
448 let Namespace = "TargetOpcode";
449 let neverHasSideEffects = 1;
451 def INSERT_SUBREG : Instruction {
452 let OutOperandList = (outs unknown:$dst);
453 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
455 let Namespace = "TargetOpcode";
456 let neverHasSideEffects = 1;
457 let Constraints = "$supersrc = $dst";
459 def IMPLICIT_DEF : Instruction {
460 let OutOperandList = (outs unknown:$dst);
461 let InOperandList = (ins);
463 let Namespace = "TargetOpcode";
464 let neverHasSideEffects = 1;
465 let isReMaterializable = 1;
466 let isAsCheapAsAMove = 1;
468 def SUBREG_TO_REG : Instruction {
469 let OutOperandList = (outs unknown:$dst);
470 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
472 let Namespace = "TargetOpcode";
473 let neverHasSideEffects = 1;
475 def COPY_TO_REGCLASS : Instruction {
476 let OutOperandList = (outs unknown:$dst);
477 let InOperandList = (ins unknown:$src, i32imm:$regclass);
479 let Namespace = "TargetOpcode";
480 let neverHasSideEffects = 1;
481 let isAsCheapAsAMove = 1;
483 def DBG_VALUE : Instruction {
484 let OutOperandList = (outs);
485 let InOperandList = (ins variable_ops);
486 let AsmString = "DBG_VALUE";
487 let Namespace = "TargetOpcode";
488 let isAsCheapAsAMove = 1;
491 def REG_SEQUENCE : Instruction {
492 let OutOperandList = (outs unknown:$dst);
493 let InOperandList = (ins variable_ops);
495 let Namespace = "TargetOpcode";
496 let neverHasSideEffects = 1;
497 let isAsCheapAsAMove = 1;
501 //===----------------------------------------------------------------------===//
502 // AsmParser - This class can be implemented by targets that wish to implement
505 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
506 // syntax on X86 for example).
509 // AsmParserClassName - This specifies the suffix to use for the asmparser
510 // class. Generated AsmParser classes are always prefixed with the target
512 string AsmParserClassName = "AsmParser";
514 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the
515 // AsmParser class to call on every matched instruction. This can be used to
516 // perform target specific instruction post-processing.
517 string AsmParserInstCleanup = "";
519 // MatchInstructionName - The name of the instruction matching function to
521 string MatchInstructionName = "MatchInstruction";
523 // Variant - AsmParsers can be of multiple different variants. Variants are
524 // used to support targets that need to parser multiple formats for the
525 // assembly language.
528 // CommentDelimiter - If given, the delimiter string used to recognize
529 // comments which are hard coded in the .td assembler strings for individual
531 string CommentDelimiter = "";
533 // RegisterPrefix - If given, the token prefix which indicates a register
534 // token. This is used by the matcher to automatically recognize hard coded
535 // register tokens as constrained registers, instead of tokens, for the
536 // purposes of matching.
537 string RegisterPrefix = "";
539 def DefaultAsmParser : AsmParser;
542 //===----------------------------------------------------------------------===//
543 // AsmWriter - This class can be implemented by targets that need to customize
544 // the format of the .s file writer.
546 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
547 // on X86 for example).
550 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
551 // class. Generated AsmWriter classes are always prefixed with the target
553 string AsmWriterClassName = "AsmPrinter";
555 // InstFormatName - AsmWriters can specify the name of the format string to
556 // print instructions with.
557 string InstFormatName = "AsmString";
559 // Variant - AsmWriters can be of multiple different variants. Variants are
560 // used to support targets that need to emit assembly code in ways that are
561 // mostly the same for different targets, but have minor differences in
562 // syntax. If the asmstring contains {|} characters in them, this integer
563 // will specify which alternative to use. For example "{x|y|z}" with Variant
564 // == 1, will expand to "y".
568 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
569 // layout, the asmwriter can actually generate output in this columns (in
570 // verbose-asm mode). These two values indicate the width of the first column
571 // (the "opcode" area) and the width to reserve for subsequent operands. When
572 // verbose asm mode is enabled, operands will be indented to respect this.
573 int FirstOperandColumn = -1;
575 // OperandSpacing - Space between operand columns.
576 int OperandSpacing = -1;
578 def DefaultAsmWriter : AsmWriter;
581 //===----------------------------------------------------------------------===//
582 // Target - This class contains the "global" target information
585 // InstructionSet - Instruction set description for this target.
586 InstrInfo InstructionSet;
588 // AssemblyParsers - The AsmParser instances available for this target.
589 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
591 // AssemblyWriters - The AsmWriter instances available for this target.
592 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
595 //===----------------------------------------------------------------------===//
596 // SubtargetFeature - A characteristic of the chip set.
598 class SubtargetFeature<string n, string a, string v, string d,
599 list<SubtargetFeature> i = []> {
600 // Name - Feature name. Used by command line (-mattr=) to determine the
601 // appropriate target chip.
605 // Attribute - Attribute to be set by feature.
607 string Attribute = a;
609 // Value - Value the attribute to be set to by feature.
613 // Desc - Feature description. Used by command line (-mattr=) to display help
618 // Implies - Features that this feature implies are present. If one of those
619 // features isn't set, then this one shouldn't be set either.
621 list<SubtargetFeature> Implies = i;
624 //===----------------------------------------------------------------------===//
625 // Processor chip sets - These values represent each of the chip sets supported
626 // by the scheduler. Each Processor definition requires corresponding
627 // instruction itineraries.
629 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
630 // Name - Chip set name. Used by command line (-mcpu=) to determine the
631 // appropriate target chip.
635 // ProcItin - The scheduling information for the target processor.
637 ProcessorItineraries ProcItin = pi;
639 // Features - list of
640 list<SubtargetFeature> Features = f;
643 //===----------------------------------------------------------------------===//
644 // Pull in the common support for calling conventions.
646 include "llvm/Target/TargetCallingConv.td"
648 //===----------------------------------------------------------------------===//
649 // Pull in the common support for DAG isel generation.
651 include "llvm/Target/TargetSelectionDAG.td"