1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // Register - You should define one instance of this class for each register
25 // in the target machine. String n will become the "name" of the register.
26 class Register<string n> {
27 string Namespace = "";
30 // SpillSize - If this value is set to a non-zero value, it is the size in
31 // bits of the spill slot required to hold this register. If this value is
32 // set to zero, the information is inferred from any register classes the
33 // register belongs to.
36 // SpillAlignment - This value is used to specify the alignment required for
37 // spilling the register. Like SpillSize, this should only be explicitly
38 // specified if the register is not in a register class.
39 int SpillAlignment = 0;
41 // Aliases - A list of registers that this register overlaps with. A read or
42 // modification of this register can potentially read or modify the aliased
44 list<Register> Aliases = [];
46 // SubRegs - A list of registers that are parts of this register. Note these
47 // are "immediate" sub-registers and the registers within the list do not
48 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
50 list<Register> SubRegs = [];
52 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
53 // These values can be determined by locating the <target>.h file in the
54 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
55 // order of these names correspond to the enumeration used by gcc. A value of
56 // -1 indicates that the gcc number is undefined and -2 that register number
57 // is invalid for this mode/flavour.
58 list<int> DwarfNumbers = [];
61 // RegisterWithSubRegs - This can be used to define instances of Register which
62 // need to specify sub-registers.
63 // List "subregs" specifies which registers are sub-registers to this one. This
64 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
65 // This allows the code generator to be careful not to put two values with
66 // overlapping live ranges into registers which alias.
67 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
68 let SubRegs = subregs;
71 // SubRegSet - This can be used to define a specific mapping of registers to
72 // indices, for use as named subregs of a particular physical register. Each
73 // register in 'subregs' becomes an addressable subregister at index 'n' of the
74 // corresponding register in 'regs'.
75 class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
78 list<Register> From = regs;
79 list<Register> To = subregs;
82 // RegisterClass - Now that all of the registers are defined, and aliases
83 // between registers are defined, specify which registers belong to which
84 // register classes. This also defines the default allocation order of
85 // registers by register allocators.
87 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
88 list<Register> regList> {
89 string Namespace = namespace;
91 // RegType - Specify the list ValueType of the registers in this register
92 // class. Note that all registers in a register class must have the same
93 // ValueTypes. This is a list because some targets permit storing different
94 // types in same register, for example vector values with 128-bit total size,
95 // but different count/size of items, like SSE on x86.
97 list<ValueType> RegTypes = regTypes;
99 // Size - Specify the spill size in bits of the registers. A default value of
100 // zero lets tablgen pick an appropriate size.
103 // Alignment - Specify the alignment required of the registers when they are
104 // stored or loaded to memory.
106 int Alignment = alignment;
108 // CopyCost - This value is used to specify the cost of copying a value
109 // between two registers in this register class. The default value is one
110 // meaning it takes a single instruction to perform the copying. A negative
111 // value means copying is extremely expensive or impossible.
114 // MemberList - Specify which registers are in this class. If the
115 // allocation_order_* method are not specified, this also defines the order of
116 // allocation used by the register allocator.
118 list<Register> MemberList = regList;
120 // SubClassList - Specify which register classes correspond to subregisters
121 // of this class. The order should be by subregister set index.
122 list<RegisterClass> SubRegClassList = [];
124 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
125 // code into a generated register class. The normal usage of this is to
126 // overload virtual methods.
127 code MethodProtos = [{}];
128 code MethodBodies = [{}];
132 //===----------------------------------------------------------------------===//
133 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
134 // to the register numbering used by gcc and gdb. These values are used by a
135 // debug information writer (ex. DwarfWriter) to describe where values may be
136 // located during execution.
137 class DwarfRegNum<list<int> Numbers> {
138 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
139 // These values can be determined by locating the <target>.h file in the
140 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
141 // order of these names correspond to the enumeration used by gcc. A value of
142 // -1 indicates that the gcc number is undefined and -2 that register number is
143 // invalid for this mode/flavour.
144 list<int> DwarfNumbers = Numbers;
147 //===----------------------------------------------------------------------===//
148 // Pull in the common support for scheduling
150 include "llvm/Target/TargetSchedule.td"
152 class Predicate; // Forward def
154 //===----------------------------------------------------------------------===//
155 // Instruction set description - These classes correspond to the C++ classes in
156 // the Target/TargetInstrInfo.h file.
159 string Namespace = "";
161 dag OutOperandList; // An dag containing the MI def operand list.
162 dag InOperandList; // An dag containing the MI use operand list.
163 string AsmString = ""; // The .s format to print the instruction with.
165 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
166 // otherwise, uninitialized.
169 // The follow state will eventually be inferred automatically from the
170 // instruction pattern.
172 list<Register> Uses = []; // Default to using no non-operand registers
173 list<Register> Defs = []; // Default to modifying no non-operand registers
175 // Predicates - List of predicates which will be turned into isel matching
177 list<Predicate> Predicates = [];
182 // Added complexity passed onto matching pattern.
183 int AddedComplexity = 0;
185 // These bits capture information about the high-level semantics of the
187 bit isReturn = 0; // Is this instruction a return instruction?
188 bit isBranch = 0; // Is this instruction a branch instruction?
189 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
190 bit isBarrier = 0; // Can control flow fall through this instruction?
191 bit isCall = 0; // Is this instruction a call instruction?
192 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
193 bit mayLoad = 0; // Is it possible for this inst to read memory?
194 bit mayStore = 0; // Is it possible for this inst to write memory?
195 bit isTwoAddress = 0; // Is this a two address instruction?
196 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
197 bit isCommutable = 0; // Is this 3 operand instruction commutable?
198 bit isTerminator = 0; // Is this part of the terminator for a basic block?
199 bit isReMaterializable = 0; // Is this instruction re-materializable?
200 bit isPredicable = 0; // Is this instruction predicable?
201 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
202 bit usesCustomInserter = 0; // Pseudo instr needing special help.
203 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
204 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
205 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
206 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
207 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
209 // Side effect flags - When set, the flags have these meanings:
211 // hasSideEffects - The instruction has side effects that are not
212 // captured by any operands of the instruction or other flags.
214 // mayHaveSideEffects - Some instances of the instruction can have side
215 // effects. The virtual method "isReallySideEffectFree" is called to
216 // determine this. Load instructions are an example of where this is
217 // useful. In general, loads always have side effects. However, loads from
218 // constant pools don't. Individual back ends make this determination.
220 // neverHasSideEffects - Set on an instruction with no pattern if it has no
222 bit hasSideEffects = 0;
223 bit mayHaveSideEffects = 0;
224 bit neverHasSideEffects = 0;
226 // Is this instruction a "real" instruction (with a distinct machine
227 // encoding), or is it a pseudo instruction used for codegen modeling
229 bit isCodeGenOnly = 0;
231 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
233 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
235 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
236 /// be encoded into the output machineinstr.
237 string DisableEncoding = "";
240 /// Predicates - These are extra conditionals which are turned into instruction
241 /// selector matching code. Currently each predicate is just a string.
242 class Predicate<string cond> {
243 string CondString = cond;
246 /// NoHonorSignDependentRounding - This predicate is true if support for
247 /// sign-dependent-rounding is not enabled.
248 def NoHonorSignDependentRounding
249 : Predicate<"!HonorSignDependentRoundingFPMath()">;
251 class Requires<list<Predicate> preds> {
252 list<Predicate> Predicates = preds;
255 /// ops definition - This is just a simple marker used to identify the operands
256 /// list for an instruction. outs and ins are identical both syntatically and
257 /// semantically, they are used to define def operands and use operands to
258 /// improve readibility. This should be used like this:
259 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
264 /// variable_ops definition - Mark this instruction as taking a variable number
269 /// PointerLikeRegClass - Values that are designed to have pointer width are
270 /// derived from this. TableGen treats the register class as having a symbolic
271 /// type that it doesn't know, and resolves the actual regclass to use by using
272 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
273 class PointerLikeRegClass<int Kind> {
274 int RegClassKind = Kind;
278 /// ptr_rc definition - Mark this operand as being a pointer value whose
279 /// register class is resolved dynamically via a callback to TargetInstrInfo.
280 /// FIXME: We should probably change this to a class which contain a list of
281 /// flags. But currently we have but one flag.
282 def ptr_rc : PointerLikeRegClass<0>;
284 /// unknown definition - Mark this operand as being of unknown type, causing
285 /// it to be resolved by inference in the context it is used.
288 /// AsmOperandClass - Representation for the kinds of operands which the target
289 /// specific parser can create and the assembly matcher may need to distinguish.
291 /// Operand classes are used to define the order in which instructions are
292 /// matched, to ensure that the instruction which gets matched for any
293 /// particular list of operands is deterministic.
295 /// The target specific parser must be able to classify a parsed operand into a
296 /// unique class which does not partially overlap with any other classes. It can
297 /// match a subset of some other class, in which case the super class field
298 /// should be defined.
299 class AsmOperandClass {
300 /// The name to use for this class, which should be usable as an enum value.
303 /// The super class of this operand.
304 AsmOperandClass SuperClass = ?;
306 /// The name of the method on the target specific operand to call to test
307 /// whether the operand is an instance of this class. If not set, this will
308 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
309 /// signature should be:
310 /// bool isFoo() const;
311 string PredicateMethod = ?;
313 /// The name of the method on the target specific operand to call to add the
314 /// target specific operand to an MCInst. If not set, this will default to
315 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
316 /// signature should be:
317 /// void addFooOperands(MCInst &Inst, unsigned N) const;
318 string RenderMethod = ?;
321 def ImmAsmOperand : AsmOperandClass {
325 /// Operand Types - These provide the built-in operand types that may be used
326 /// by a target. Targets can optionally provide their own operand types as
327 /// needed, though this should not be needed for RISC targets.
328 class Operand<ValueType ty> {
330 string PrintMethod = "printOperand";
331 string AsmOperandLowerMethod = ?;
332 dag MIOperandInfo = (ops);
334 // ParserMatchClass - The "match class" that operands of this type fit
335 // in. Match classes are used to define the order in which instructions are
336 // match, to ensure that which instructions gets matched is deterministic.
338 // The target specific parser must be able to classify an parsed operand
339 // into a unique class, which does not partially overlap with any other
340 // classes. It can match a subset of some other class, in which case
341 // ParserMatchSuperClass should be set to the name of that class.
342 AsmOperandClass ParserMatchClass = ImmAsmOperand;
345 def i1imm : Operand<i1>;
346 def i8imm : Operand<i8>;
347 def i16imm : Operand<i16>;
348 def i32imm : Operand<i32>;
349 def i64imm : Operand<i64>;
351 def f32imm : Operand<f32>;
352 def f64imm : Operand<f64>;
354 /// zero_reg definition - Special node to stand for the zero register.
358 /// PredicateOperand - This can be used to define a predicate operand for an
359 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
360 /// AlwaysVal specifies the value of this predicate when set to "always
362 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
364 let MIOperandInfo = OpTypes;
365 dag DefaultOps = AlwaysVal;
368 /// OptionalDefOperand - This is used to define a optional definition operand
369 /// for an instruction. DefaultOps is the register the operand represents if
370 /// none is supplied, e.g. zero_reg.
371 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
373 let MIOperandInfo = OpTypes;
374 dag DefaultOps = defaultops;
378 // InstrInfo - This class should only be instantiated once to provide parameters
379 // which are global to the the target machine.
382 // If the target wants to associate some target-specific information with each
383 // instruction, it should provide these two lists to indicate how to assemble
384 // the target specific information into the 32 bits available.
386 list<string> TSFlagsFields = [];
387 list<int> TSFlagsShifts = [];
389 // Target can specify its instructions in either big or little-endian formats.
390 // For instance, while both Sparc and PowerPC are big-endian platforms, the
391 // Sparc manual specifies its instructions in the format [31..0] (big), while
392 // PowerPC specifies them using the format [0..31] (little).
393 bit isLittleEndianEncoding = 0;
396 // Standard Pseudo Instructions.
397 let isCodeGenOnly = 1 in {
398 def PHI : Instruction {
399 let OutOperandList = (ops);
400 let InOperandList = (ops variable_ops);
401 let AsmString = "PHINODE";
402 let Namespace = "TargetInstrInfo";
404 def INLINEASM : Instruction {
405 let OutOperandList = (ops);
406 let InOperandList = (ops variable_ops);
408 let Namespace = "TargetInstrInfo";
410 def DBG_LABEL : Instruction {
411 let OutOperandList = (ops);
412 let InOperandList = (ops i32imm:$id);
414 let Namespace = "TargetInstrInfo";
416 let isNotDuplicable = 1;
418 def EH_LABEL : Instruction {
419 let OutOperandList = (ops);
420 let InOperandList = (ops i32imm:$id);
422 let Namespace = "TargetInstrInfo";
424 let isNotDuplicable = 1;
426 def GC_LABEL : Instruction {
427 let OutOperandList = (ops);
428 let InOperandList = (ops i32imm:$id);
430 let Namespace = "TargetInstrInfo";
432 let isNotDuplicable = 1;
434 def KILL : Instruction {
435 let OutOperandList = (ops);
436 let InOperandList = (ops variable_ops);
438 let Namespace = "TargetInstrInfo";
439 let neverHasSideEffects = 1;
441 def EXTRACT_SUBREG : Instruction {
442 let OutOperandList = (ops unknown:$dst);
443 let InOperandList = (ops unknown:$supersrc, i32imm:$subidx);
445 let Namespace = "TargetInstrInfo";
446 let neverHasSideEffects = 1;
448 def INSERT_SUBREG : Instruction {
449 let OutOperandList = (ops unknown:$dst);
450 let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
452 let Namespace = "TargetInstrInfo";
453 let neverHasSideEffects = 1;
454 let Constraints = "$supersrc = $dst";
456 def IMPLICIT_DEF : Instruction {
457 let OutOperandList = (ops unknown:$dst);
458 let InOperandList = (ops);
460 let Namespace = "TargetInstrInfo";
461 let neverHasSideEffects = 1;
462 let isReMaterializable = 1;
463 let isAsCheapAsAMove = 1;
465 def SUBREG_TO_REG : Instruction {
466 let OutOperandList = (ops unknown:$dst);
467 let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
469 let Namespace = "TargetInstrInfo";
470 let neverHasSideEffects = 1;
472 def COPY_TO_REGCLASS : Instruction {
473 let OutOperandList = (ops unknown:$dst);
474 let InOperandList = (ops unknown:$src, i32imm:$regclass);
476 let Namespace = "TargetInstrInfo";
477 let neverHasSideEffects = 1;
478 let isAsCheapAsAMove = 1;
482 //===----------------------------------------------------------------------===//
483 // AsmParser - This class can be implemented by targets that wish to implement
486 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
487 // syntax on X86 for example).
490 // AsmParserClassName - This specifies the suffix to use for the asmparser
491 // class. Generated AsmParser classes are always prefixed with the target
493 string AsmParserClassName = "AsmParser";
495 // Variant - AsmParsers can be of multiple different variants. Variants are
496 // used to support targets that need to parser multiple formats for the
497 // assembly language.
500 // CommentDelimiter - If given, the delimiter string used to recognize
501 // comments which are hard coded in the .td assembler strings for individual
503 string CommentDelimiter = "";
505 // RegisterPrefix - If given, the token prefix which indicates a register
506 // token. This is used by the matcher to automatically recognize hard coded
507 // register tokens as constrained registers, instead of tokens, for the
508 // purposes of matching.
509 string RegisterPrefix = "";
511 def DefaultAsmParser : AsmParser;
514 //===----------------------------------------------------------------------===//
515 // AsmWriter - This class can be implemented by targets that need to customize
516 // the format of the .s file writer.
518 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
519 // on X86 for example).
522 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
523 // class. Generated AsmWriter classes are always prefixed with the target
525 string AsmWriterClassName = "AsmPrinter";
527 // InstFormatName - AsmWriters can specify the name of the format string to
528 // print instructions with.
529 string InstFormatName = "AsmString";
531 // Variant - AsmWriters can be of multiple different variants. Variants are
532 // used to support targets that need to emit assembly code in ways that are
533 // mostly the same for different targets, but have minor differences in
534 // syntax. If the asmstring contains {|} characters in them, this integer
535 // will specify which alternative to use. For example "{x|y|z}" with Variant
536 // == 1, will expand to "y".
540 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
541 // layout, the asmwriter can actually generate output in this columns (in
542 // verbose-asm mode). These two values indicate the width of the first column
543 // (the "opcode" area) and the width to reserve for subsequent operands. When
544 // verbose asm mode is enabled, operands will be indented to respect this.
545 int FirstOperandColumn = -1;
547 // OperandSpacing - Space between operand columns.
548 int OperandSpacing = -1;
550 def DefaultAsmWriter : AsmWriter;
553 //===----------------------------------------------------------------------===//
554 // Target - This class contains the "global" target information
557 // InstructionSet - Instruction set description for this target.
558 InstrInfo InstructionSet;
560 // AssemblyParsers - The AsmParser instances available for this target.
561 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
563 // AssemblyWriters - The AsmWriter instances available for this target.
564 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
567 //===----------------------------------------------------------------------===//
568 // SubtargetFeature - A characteristic of the chip set.
570 class SubtargetFeature<string n, string a, string v, string d,
571 list<SubtargetFeature> i = []> {
572 // Name - Feature name. Used by command line (-mattr=) to determine the
573 // appropriate target chip.
577 // Attribute - Attribute to be set by feature.
579 string Attribute = a;
581 // Value - Value the attribute to be set to by feature.
585 // Desc - Feature description. Used by command line (-mattr=) to display help
590 // Implies - Features that this feature implies are present. If one of those
591 // features isn't set, then this one shouldn't be set either.
593 list<SubtargetFeature> Implies = i;
596 //===----------------------------------------------------------------------===//
597 // Processor chip sets - These values represent each of the chip sets supported
598 // by the scheduler. Each Processor definition requires corresponding
599 // instruction itineraries.
601 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
602 // Name - Chip set name. Used by command line (-mcpu=) to determine the
603 // appropriate target chip.
607 // ProcItin - The scheduling information for the target processor.
609 ProcessorItineraries ProcItin = pi;
611 // Features - list of
612 list<SubtargetFeature> Features = f;
615 //===----------------------------------------------------------------------===//
616 // Pull in the common support for calling conventions.
618 include "llvm/Target/TargetCallingConv.td"
620 //===----------------------------------------------------------------------===//
621 // Pull in the common support for DAG isel generation.
623 include "llvm/Target/TargetSelectionDAG.td"