1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<int size, int offset = 0> {
26 string Namespace = "";
28 // Size - Size (in bits) of the sub-registers represented by this index.
31 // Offset - Offset of the first bit that is part of this sub-register index.
32 // Set it to -1 if the same index is used to represent sub-registers that can
33 // be at different offsets (for example when using an index to access an
34 // element in a register tuple).
37 // ComposedOf - A list of two SubRegIndex instances, [A, B].
38 // This indicates that this SubRegIndex is the result of composing A and B.
39 // See ComposedSubRegIndex.
40 list<SubRegIndex> ComposedOf = [];
42 // CoveringSubRegIndices - A list of two or more sub-register indexes that
43 // cover this sub-register.
45 // This field should normally be left blank as TableGen can infer it.
47 // TableGen automatically detects sub-registers that straddle the registers
48 // in the SubRegs field of a Register definition. For example:
50 // Q0 = dsub_0 -> D0, dsub_1 -> D1
51 // Q1 = dsub_0 -> D2, dsub_1 -> D3
52 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
53 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
55 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
57 // CoveringSubRegIndices = [dsub_1, dsub_2].
58 list<SubRegIndex> CoveringSubRegIndices = [];
61 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
62 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
63 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
65 !if(!eq(B.Offset, -1), -1,
66 !add(A.Offset, B.Offset)))> {
68 let ComposedOf = [A, B];
71 // RegAltNameIndex - The alternate name set to use for register operands of
72 // this register class when printing.
73 class RegAltNameIndex {
74 string Namespace = "";
76 def NoRegAltName : RegAltNameIndex;
78 // Register - You should define one instance of this class for each register
79 // in the target machine. String n will become the "name" of the register.
80 class Register<string n, list<string> altNames = []> {
81 string Namespace = "";
83 list<string> AltNames = altNames;
85 // Aliases - A list of registers that this register overlaps with. A read or
86 // modification of this register can potentially read or modify the aliased
88 list<Register> Aliases = [];
90 // SubRegs - A list of registers that are parts of this register. Note these
91 // are "immediate" sub-registers and the registers within the list do not
92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
94 list<Register> SubRegs = [];
96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
97 // to address it. Sub-sub-register indices are automatically inherited from
99 list<SubRegIndex> SubRegIndices = [];
101 // RegAltNameIndices - The alternate name indices which are valid for this
103 list<RegAltNameIndex> RegAltNameIndices = [];
105 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
106 // These values can be determined by locating the <target>.h file in the
107 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
108 // order of these names correspond to the enumeration used by gcc. A value of
109 // -1 indicates that the gcc number is undefined and -2 that register number
110 // is invalid for this mode/flavour.
111 list<int> DwarfNumbers = [];
113 // CostPerUse - Additional cost of instructions using this register compared
114 // to other registers in its class. The register allocator will try to
115 // minimize the number of instructions using a register with a CostPerUse.
116 // This is used by the x86-64 and ARM Thumb targets where some registers
117 // require larger instruction encodings.
120 // CoveredBySubRegs - When this bit is set, the value of this register is
121 // completely determined by the value of its sub-registers. For example, the
122 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
123 // covered by its sub-register AX.
124 bit CoveredBySubRegs = 0;
126 // HWEncoding - The target specific hardware encoding for this register.
127 bits<16> HWEncoding = 0;
130 // RegisterWithSubRegs - This can be used to define instances of Register which
131 // need to specify sub-registers.
132 // List "subregs" specifies which registers are sub-registers to this one. This
133 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
134 // This allows the code generator to be careful not to put two values with
135 // overlapping live ranges into registers which alias.
136 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
137 let SubRegs = subregs;
140 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
141 // of Operand's that are legal as type qualifiers in DAG patterns. This should
142 // only ever be used for defining multiclasses that are polymorphic over both
143 // RegisterClass's and other Operand's.
146 // RegisterClass - Now that all of the registers are defined, and aliases
147 // between registers are defined, specify which registers belong to which
148 // register classes. This also defines the default allocation order of
149 // registers by register allocators.
151 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
152 dag regList, RegAltNameIndex idx = NoRegAltName>
154 string Namespace = namespace;
156 // RegType - Specify the list ValueType of the registers in this register
157 // class. Note that all registers in a register class must have the same
158 // ValueTypes. This is a list because some targets permit storing different
159 // types in same register, for example vector values with 128-bit total size,
160 // but different count/size of items, like SSE on x86.
162 list<ValueType> RegTypes = regTypes;
164 // Size - Specify the spill size in bits of the registers. A default value of
165 // zero lets tablgen pick an appropriate size.
168 // Alignment - Specify the alignment required of the registers when they are
169 // stored or loaded to memory.
171 int Alignment = alignment;
173 // CopyCost - This value is used to specify the cost of copying a value
174 // between two registers in this register class. The default value is one
175 // meaning it takes a single instruction to perform the copying. A negative
176 // value means copying is extremely expensive or impossible.
179 // MemberList - Specify which registers are in this class. If the
180 // allocation_order_* method are not specified, this also defines the order of
181 // allocation used by the register allocator.
183 dag MemberList = regList;
185 // AltNameIndex - The alternate register name to use when printing operands
186 // of this register class. Every register in the register class must have
187 // a valid alternate name for the given index.
188 RegAltNameIndex altNameIndex = idx;
190 // isAllocatable - Specify that the register class can be used for virtual
191 // registers and register allocation. Some register classes are only used to
192 // model instruction operand constraints, and should have isAllocatable = 0.
193 bit isAllocatable = 1;
195 // AltOrders - List of alternative allocation orders. The default order is
196 // MemberList itself, and that is good enough for most targets since the
197 // register allocators automatically remove reserved registers and move
198 // callee-saved registers to the end.
199 list<dag> AltOrders = [];
201 // AltOrderSelect - The body of a function that selects the allocation order
202 // to use in a given machine function. The code will be inserted in a
203 // function like this:
205 // static inline unsigned f(const MachineFunction &MF) { ... }
207 // The function should return 0 to select the default order defined by
208 // MemberList, 1 to select the first AltOrders entry and so on.
209 code AltOrderSelect = [{}];
212 // The memberList in a RegisterClass is a dag of set operations. TableGen
213 // evaluates these set operations and expand them into register lists. These
214 // are the most common operation, see test/TableGen/SetTheory.td for more
215 // examples of what is possible:
217 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
218 // register class, or a sub-expression. This is also the way to simply list
221 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
223 // (and GPR, CSR) - Set intersection. All registers from the first set that are
224 // also in the second set.
226 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
227 // numbered registers. Takes an optional 4th operand which is a stride to use
228 // when generating the sequence.
230 // (shl GPR, 4) - Remove the first N elements.
232 // (trunc GPR, 4) - Truncate after the first N elements.
234 // (rotl GPR, 1) - Rotate N places to the left.
236 // (rotr GPR, 1) - Rotate N places to the right.
238 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
240 // (interleave A, B, ...) - Interleave the elements from each argument list.
242 // All of these operators work on ordered sets, not lists. That means
243 // duplicates are removed from sub-expressions.
245 // Set operators. The rest is defined in TargetSelectionDAG.td.
250 // RegisterTuples - Automatically generate super-registers by forming tuples of
251 // sub-registers. This is useful for modeling register sequence constraints
252 // with pseudo-registers that are larger than the architectural registers.
254 // The sub-register lists are zipped together:
256 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
258 // Generates the same registers as:
260 // let SubRegIndices = [sube, subo] in {
261 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
262 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
265 // The generated pseudo-registers inherit super-classes and fields from their
266 // first sub-register. Most fields from the Register class are inferred, and
267 // the AsmName and Dwarf numbers are cleared.
269 // RegisterTuples instances can be used in other set operations to form
270 // register classes and so on. This is the only way of using the generated
272 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
273 // SubRegs - N lists of registers to be zipped up. Super-registers are
274 // synthesized from the first element of each SubRegs list, the second
275 // element and so on.
276 list<dag> SubRegs = Regs;
278 // SubRegIndices - N SubRegIndex instances. This provides the names of the
279 // sub-registers in the synthesized super-registers.
280 list<SubRegIndex> SubRegIndices = Indices;
284 //===----------------------------------------------------------------------===//
285 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
286 // to the register numbering used by gcc and gdb. These values are used by a
287 // debug information writer to describe where values may be located during
289 class DwarfRegNum<list<int> Numbers> {
290 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
291 // These values can be determined by locating the <target>.h file in the
292 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
293 // order of these names correspond to the enumeration used by gcc. A value of
294 // -1 indicates that the gcc number is undefined and -2 that register number
295 // is invalid for this mode/flavour.
296 list<int> DwarfNumbers = Numbers;
299 // DwarfRegAlias - This class declares that a given register uses the same dwarf
300 // numbers as another one. This is useful for making it clear that the two
301 // registers do have the same number. It also lets us build a mapping
302 // from dwarf register number to llvm register.
303 class DwarfRegAlias<Register reg> {
304 Register DwarfAlias = reg;
307 //===----------------------------------------------------------------------===//
308 // Pull in the common support for scheduling
310 include "llvm/Target/TargetSchedule.td"
312 class Predicate; // Forward def
314 //===----------------------------------------------------------------------===//
315 // Instruction set description - These classes correspond to the C++ classes in
316 // the Target/TargetInstrInfo.h file.
319 string Namespace = "";
321 dag OutOperandList; // An dag containing the MI def operand list.
322 dag InOperandList; // An dag containing the MI use operand list.
323 string AsmString = ""; // The .s format to print the instruction with.
325 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
326 // otherwise, uninitialized.
329 // The follow state will eventually be inferred automatically from the
330 // instruction pattern.
332 list<Register> Uses = []; // Default to using no non-operand registers
333 list<Register> Defs = []; // Default to modifying no non-operand registers
335 // Predicates - List of predicates which will be turned into isel matching
337 list<Predicate> Predicates = [];
339 // Size - Size of encoded instruction, or zero if the size cannot be determined
343 // DecoderNamespace - The "namespace" in which this instruction exists, on
344 // targets like ARM which multiple ISA namespaces exist.
345 string DecoderNamespace = "";
347 // Code size, for instruction selection.
348 // FIXME: What does this actually mean?
351 // Added complexity passed onto matching pattern.
352 int AddedComplexity = 0;
354 // These bits capture information about the high-level semantics of the
356 bit isReturn = 0; // Is this instruction a return instruction?
357 bit isBranch = 0; // Is this instruction a branch instruction?
358 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
359 bit isCompare = 0; // Is this instruction a comparison instruction?
360 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
361 bit isBitcast = 0; // Is this instruction a bitcast instruction?
362 bit isSelect = 0; // Is this instruction a select instruction?
363 bit isBarrier = 0; // Can control flow fall through this instruction?
364 bit isCall = 0; // Is this instruction a call instruction?
365 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
366 bit mayLoad = ?; // Is it possible for this inst to read memory?
367 bit mayStore = ?; // Is it possible for this inst to write memory?
368 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
369 bit isCommutable = 0; // Is this 3 operand instruction commutable?
370 bit isTerminator = 0; // Is this part of the terminator for a basic block?
371 bit isReMaterializable = 0; // Is this instruction re-materializable?
372 bit isPredicable = 0; // Is this instruction predicable?
373 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
374 bit usesCustomInserter = 0; // Pseudo instr needing special help.
375 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
376 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
377 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
378 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
379 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
380 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
381 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
382 // If so, won't have encoding information for
383 // the [MC]CodeEmitter stuff.
385 // Side effect flags - When set, the flags have these meanings:
387 // hasSideEffects - The instruction has side effects that are not
388 // captured by any operands of the instruction or other flags.
390 // neverHasSideEffects (deprecated) - Set on an instruction with no pattern
391 // if it has no side effects. This is now equivalent to setting
392 // "hasSideEffects = 0".
393 bit hasSideEffects = ?;
394 bit neverHasSideEffects = 0;
396 // Is this instruction a "real" instruction (with a distinct machine
397 // encoding), or is it a pseudo instruction used for codegen modeling
399 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
400 // instructions can (and often do) still have encoding information
401 // associated with them. Once we've migrated all of them over to true
402 // pseudo-instructions that are lowered to real instructions prior to
403 // the printer/emitter, we can remove this attribute and just use isPseudo.
405 // The intended use is:
406 // isPseudo: Does not have encoding information and should be expanded,
407 // at the latest, during lowering to MCInst.
409 // isCodeGenOnly: Does have encoding information and can go through to the
410 // CodeEmitter unchanged, but duplicates a canonical instruction
411 // definition's encoding and should be ignored when constructing the
412 // assembler match tables.
413 bit isCodeGenOnly = 0;
415 // Is this instruction a pseudo instruction for use by the assembler parser.
416 bit isAsmParserOnly = 0;
418 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
420 // Scheduling information from TargetSchedule.td.
421 list<SchedReadWrite> SchedRW;
423 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
425 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
426 /// be encoded into the output machineinstr.
427 string DisableEncoding = "";
429 string PostEncoderMethod = "";
430 string DecoderMethod = "";
432 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
433 bits<64> TSFlags = 0;
435 ///@name Assembler Parser Support
438 string AsmMatchConverter = "";
440 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
441 /// two-operand matcher inst-alias for a three operand instruction.
442 /// For example, the arm instruction "add r3, r3, r5" can be written
443 /// as "add r3, r5". The constraint is of the same form as a tied-operand
444 /// constraint. For example, "$Rn = $Rd".
445 string TwoOperandAliasConstraint = "";
449 /// UseNamedOperandTable - If set, the operand indices of this instruction
450 /// can be queried via the getNamedOperandIdx() function which is generated
452 bit UseNamedOperandTable = 0;
455 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
456 /// Which instruction it expands to and how the operands map from the
458 class PseudoInstExpansion<dag Result> {
459 dag ResultInst = Result; // The instruction to generate.
463 /// Predicates - These are extra conditionals which are turned into instruction
464 /// selector matching code. Currently each predicate is just a string.
465 class Predicate<string cond> {
466 string CondString = cond;
468 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
469 /// matcher, this is true. Targets should set this by inheriting their
470 /// feature from the AssemblerPredicate class in addition to Predicate.
471 bit AssemblerMatcherPredicate = 0;
473 /// AssemblerCondString - Name of the subtarget feature being tested used
474 /// as alternative condition string used for assembler matcher.
475 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
476 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
477 /// It can also list multiple features separated by ",".
478 /// e.g. "ModeThumb,FeatureThumb2" is translated to
479 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
480 string AssemblerCondString = "";
482 /// PredicateName - User-level name to use for the predicate. Mainly for use
483 /// in diagnostics such as missing feature errors in the asm matcher.
484 string PredicateName = "";
487 /// NoHonorSignDependentRounding - This predicate is true if support for
488 /// sign-dependent-rounding is not enabled.
489 def NoHonorSignDependentRounding
490 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
492 class Requires<list<Predicate> preds> {
493 list<Predicate> Predicates = preds;
496 /// ops definition - This is just a simple marker used to identify the operand
497 /// list for an instruction. outs and ins are identical both syntactically and
498 /// semanticallyr; they are used to define def operands and use operands to
499 /// improve readibility. This should be used like this:
500 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
505 /// variable_ops definition - Mark this instruction as taking a variable number
510 /// PointerLikeRegClass - Values that are designed to have pointer width are
511 /// derived from this. TableGen treats the register class as having a symbolic
512 /// type that it doesn't know, and resolves the actual regclass to use by using
513 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
514 class PointerLikeRegClass<int Kind> {
515 int RegClassKind = Kind;
519 /// ptr_rc definition - Mark this operand as being a pointer value whose
520 /// register class is resolved dynamically via a callback to TargetInstrInfo.
521 /// FIXME: We should probably change this to a class which contain a list of
522 /// flags. But currently we have but one flag.
523 def ptr_rc : PointerLikeRegClass<0>;
525 /// unknown definition - Mark this operand as being of unknown type, causing
526 /// it to be resolved by inference in the context it is used.
528 def unknown : unknown_class;
530 /// AsmOperandClass - Representation for the kinds of operands which the target
531 /// specific parser can create and the assembly matcher may need to distinguish.
533 /// Operand classes are used to define the order in which instructions are
534 /// matched, to ensure that the instruction which gets matched for any
535 /// particular list of operands is deterministic.
537 /// The target specific parser must be able to classify a parsed operand into a
538 /// unique class which does not partially overlap with any other classes. It can
539 /// match a subset of some other class, in which case the super class field
540 /// should be defined.
541 class AsmOperandClass {
542 /// The name to use for this class, which should be usable as an enum value.
545 /// The super classes of this operand.
546 list<AsmOperandClass> SuperClasses = [];
548 /// The name of the method on the target specific operand to call to test
549 /// whether the operand is an instance of this class. If not set, this will
550 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
551 /// signature should be:
552 /// bool isFoo() const;
553 string PredicateMethod = ?;
555 /// The name of the method on the target specific operand to call to add the
556 /// target specific operand to an MCInst. If not set, this will default to
557 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
558 /// signature should be:
559 /// void addFooOperands(MCInst &Inst, unsigned N) const;
560 string RenderMethod = ?;
562 /// The name of the method on the target specific operand to call to custom
563 /// handle the operand parsing. This is useful when the operands do not relate
564 /// to immediates or registers and are very instruction specific (as flags to
565 /// set in a processor register, coprocessor number, ...).
566 string ParserMethod = ?;
568 // The diagnostic type to present when referencing this operand in a
569 // match failure error message. By default, use a generic "invalid operand"
570 // diagnostic. The target AsmParser maps these codes to text.
571 string DiagnosticType = "";
574 def ImmAsmOperand : AsmOperandClass {
578 /// Operand Types - These provide the built-in operand types that may be used
579 /// by a target. Targets can optionally provide their own operand types as
580 /// needed, though this should not be needed for RISC targets.
581 class Operand<ValueType ty> : DAGOperand {
583 string PrintMethod = "printOperand";
584 string EncoderMethod = "";
585 string DecoderMethod = "";
586 string AsmOperandLowerMethod = ?;
587 string OperandType = "OPERAND_UNKNOWN";
588 dag MIOperandInfo = (ops);
590 // ParserMatchClass - The "match class" that operands of this type fit
591 // in. Match classes are used to define the order in which instructions are
592 // match, to ensure that which instructions gets matched is deterministic.
594 // The target specific parser must be able to classify an parsed operand into
595 // a unique class, which does not partially overlap with any other classes. It
596 // can match a subset of some other class, in which case the AsmOperandClass
597 // should declare the other operand as one of its super classes.
598 AsmOperandClass ParserMatchClass = ImmAsmOperand;
601 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
603 // RegClass - The register class of the operand.
604 RegisterClass RegClass = regclass;
605 // PrintMethod - The target method to call to print register operands of
606 // this type. The method normally will just use an alt-name index to look
607 // up the name to print. Default to the generic printOperand().
608 string PrintMethod = pm;
609 // ParserMatchClass - The "match class" that operands of this type fit
610 // in. Match classes are used to define the order in which instructions are
611 // match, to ensure that which instructions gets matched is deterministic.
613 // The target specific parser must be able to classify an parsed operand into
614 // a unique class, which does not partially overlap with any other classes. It
615 // can match a subset of some other class, in which case the AsmOperandClass
616 // should declare the other operand as one of its super classes.
617 AsmOperandClass ParserMatchClass;
620 let OperandType = "OPERAND_IMMEDIATE" in {
621 def i1imm : Operand<i1>;
622 def i8imm : Operand<i8>;
623 def i16imm : Operand<i16>;
624 def i32imm : Operand<i32>;
625 def i64imm : Operand<i64>;
627 def f32imm : Operand<f32>;
628 def f64imm : Operand<f64>;
631 /// zero_reg definition - Special node to stand for the zero register.
635 /// OperandWithDefaultOps - This Operand class can be used as the parent class
636 /// for an Operand that needs to be initialized with a default value if
637 /// no value is supplied in a pattern. This class can be used to simplify the
638 /// pattern definitions for instructions that have target specific flags
639 /// encoded as immediate operands.
640 class OperandWithDefaultOps<ValueType ty, dag defaultops>
642 dag DefaultOps = defaultops;
645 /// PredicateOperand - This can be used to define a predicate operand for an
646 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
647 /// AlwaysVal specifies the value of this predicate when set to "always
649 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
650 : OperandWithDefaultOps<ty, AlwaysVal> {
651 let MIOperandInfo = OpTypes;
654 /// OptionalDefOperand - This is used to define a optional definition operand
655 /// for an instruction. DefaultOps is the register the operand represents if
656 /// none is supplied, e.g. zero_reg.
657 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
658 : OperandWithDefaultOps<ty, defaultops> {
659 let MIOperandInfo = OpTypes;
663 // InstrInfo - This class should only be instantiated once to provide parameters
664 // which are global to the target machine.
667 // Target can specify its instructions in either big or little-endian formats.
668 // For instance, while both Sparc and PowerPC are big-endian platforms, the
669 // Sparc manual specifies its instructions in the format [31..0] (big), while
670 // PowerPC specifies them using the format [0..31] (little).
671 bit isLittleEndianEncoding = 0;
673 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
674 // by default, and TableGen will infer their value from the instruction
675 // pattern when possible.
677 // Normally, TableGen will issue an error it it can't infer the value of a
678 // property that hasn't been set explicitly. When guessInstructionProperties
679 // is set, it will guess a safe value instead.
681 // This option is a temporary migration help. It will go away.
682 bit guessInstructionProperties = 1;
685 // Standard Pseudo Instructions.
686 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
687 // Only these instructions are allowed in the TargetOpcode namespace.
688 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
689 def PHI : Instruction {
690 let OutOperandList = (outs);
691 let InOperandList = (ins variable_ops);
692 let AsmString = "PHINODE";
694 def INLINEASM : Instruction {
695 let OutOperandList = (outs);
696 let InOperandList = (ins variable_ops);
698 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
700 def PROLOG_LABEL : Instruction {
701 let OutOperandList = (outs);
702 let InOperandList = (ins i32imm:$id);
705 let isNotDuplicable = 1;
707 def EH_LABEL : Instruction {
708 let OutOperandList = (outs);
709 let InOperandList = (ins i32imm:$id);
712 let isNotDuplicable = 1;
714 def GC_LABEL : Instruction {
715 let OutOperandList = (outs);
716 let InOperandList = (ins i32imm:$id);
719 let isNotDuplicable = 1;
721 def KILL : Instruction {
722 let OutOperandList = (outs);
723 let InOperandList = (ins variable_ops);
725 let neverHasSideEffects = 1;
727 def EXTRACT_SUBREG : Instruction {
728 let OutOperandList = (outs unknown:$dst);
729 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
731 let neverHasSideEffects = 1;
733 def INSERT_SUBREG : Instruction {
734 let OutOperandList = (outs unknown:$dst);
735 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
737 let neverHasSideEffects = 1;
738 let Constraints = "$supersrc = $dst";
740 def IMPLICIT_DEF : Instruction {
741 let OutOperandList = (outs unknown:$dst);
742 let InOperandList = (ins);
744 let neverHasSideEffects = 1;
745 let isReMaterializable = 1;
746 let isAsCheapAsAMove = 1;
748 def SUBREG_TO_REG : Instruction {
749 let OutOperandList = (outs unknown:$dst);
750 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
752 let neverHasSideEffects = 1;
754 def COPY_TO_REGCLASS : Instruction {
755 let OutOperandList = (outs unknown:$dst);
756 let InOperandList = (ins unknown:$src, i32imm:$regclass);
758 let neverHasSideEffects = 1;
759 let isAsCheapAsAMove = 1;
761 def DBG_VALUE : Instruction {
762 let OutOperandList = (outs);
763 let InOperandList = (ins variable_ops);
764 let AsmString = "DBG_VALUE";
765 let neverHasSideEffects = 1;
767 def REG_SEQUENCE : Instruction {
768 let OutOperandList = (outs unknown:$dst);
769 let InOperandList = (ins variable_ops);
771 let neverHasSideEffects = 1;
772 let isAsCheapAsAMove = 1;
774 def COPY : Instruction {
775 let OutOperandList = (outs unknown:$dst);
776 let InOperandList = (ins unknown:$src);
778 let neverHasSideEffects = 1;
779 let isAsCheapAsAMove = 1;
781 def BUNDLE : Instruction {
782 let OutOperandList = (outs);
783 let InOperandList = (ins variable_ops);
784 let AsmString = "BUNDLE";
786 def LIFETIME_START : Instruction {
787 let OutOperandList = (outs);
788 let InOperandList = (ins i32imm:$id);
789 let AsmString = "LIFETIME_START";
790 let neverHasSideEffects = 1;
792 def LIFETIME_END : Instruction {
793 let OutOperandList = (outs);
794 let InOperandList = (ins i32imm:$id);
795 let AsmString = "LIFETIME_END";
796 let neverHasSideEffects = 1;
800 //===----------------------------------------------------------------------===//
801 // AsmParser - This class can be implemented by targets that wish to implement
804 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
805 // syntax on X86 for example).
808 // AsmParserClassName - This specifies the suffix to use for the asmparser
809 // class. Generated AsmParser classes are always prefixed with the target
811 string AsmParserClassName = "AsmParser";
813 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
814 // function of the AsmParser class to call on every matched instruction.
815 // This can be used to perform target specific instruction post-processing.
816 string AsmParserInstCleanup = "";
818 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
819 // written register name matcher
820 bit ShouldEmitMatchRegisterName = 1;
822 def DefaultAsmParser : AsmParser;
824 //===----------------------------------------------------------------------===//
825 // AsmParserVariant - Subtargets can have multiple different assembly parsers
826 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
827 // implemented by targets to describe such variants.
829 class AsmParserVariant {
830 // Variant - AsmParsers can be of multiple different variants. Variants are
831 // used to support targets that need to parser multiple formats for the
832 // assembly language.
835 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
838 // CommentDelimiter - If given, the delimiter string used to recognize
839 // comments which are hard coded in the .td assembler strings for individual
841 string CommentDelimiter = "";
843 // RegisterPrefix - If given, the token prefix which indicates a register
844 // token. This is used by the matcher to automatically recognize hard coded
845 // register tokens as constrained registers, instead of tokens, for the
846 // purposes of matching.
847 string RegisterPrefix = "";
849 def DefaultAsmParserVariant : AsmParserVariant;
851 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
852 /// matches instructions and aliases.
853 class AssemblerPredicate<string cond, string name = ""> {
854 bit AssemblerMatcherPredicate = 1;
855 string AssemblerCondString = cond;
856 string PredicateName = name;
859 /// TokenAlias - This class allows targets to define assembler token
860 /// operand aliases. That is, a token literal operand which is equivalent
861 /// to another, canonical, token literal. For example, ARM allows:
862 /// vmov.u32 s4, #0 -> vmov.i32, #0
863 /// 'u32' is a more specific designator for the 32-bit integer type specifier
864 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
865 /// def : TokenAlias<".u32", ".i32">;
867 /// This works by marking the match class of 'From' as a subclass of the
868 /// match class of 'To'.
869 class TokenAlias<string From, string To> {
870 string FromToken = From;
874 /// MnemonicAlias - This class allows targets to define assembler mnemonic
875 /// aliases. This should be used when all forms of one mnemonic are accepted
876 /// with a different mnemonic. For example, X86 allows:
877 /// sal %al, 1 -> shl %al, 1
878 /// sal %ax, %cl -> shl %ax, %cl
879 /// sal %eax, %cl -> shl %eax, %cl
880 /// etc. Though "sal" is accepted with many forms, all of them are directly
881 /// translated to a shl, so it can be handled with (in the case of X86, it
882 /// actually has one for each suffix as well):
883 /// def : MnemonicAlias<"sal", "shl">;
885 /// Mnemonic aliases are mapped before any other translation in the match phase,
886 /// and do allow Requires predicates, e.g.:
888 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
889 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
891 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
893 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
895 /// If no variant (e.g., "att" or "intel") is specified then the alias is
896 /// applied unconditionally.
897 class MnemonicAlias<string From, string To, string VariantName = ""> {
898 string FromMnemonic = From;
899 string ToMnemonic = To;
900 string AsmVariantName = VariantName;
902 // Predicates - Predicates that must be true for this remapping to happen.
903 list<Predicate> Predicates = [];
906 /// InstAlias - This defines an alternate assembly syntax that is allowed to
907 /// match an instruction that has a different (more canonical) assembly
909 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
910 string AsmString = Asm; // The .s format to match the instruction with.
911 dag ResultInst = Result; // The MCInst to generate.
912 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
914 // Predicates - Predicates that must be true for this to match.
915 list<Predicate> Predicates = [];
918 //===----------------------------------------------------------------------===//
919 // AsmWriter - This class can be implemented by targets that need to customize
920 // the format of the .s file writer.
922 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
923 // on X86 for example).
926 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
927 // class. Generated AsmWriter classes are always prefixed with the target
929 string AsmWriterClassName = "AsmPrinter";
931 // Variant - AsmWriters can be of multiple different variants. Variants are
932 // used to support targets that need to emit assembly code in ways that are
933 // mostly the same for different targets, but have minor differences in
934 // syntax. If the asmstring contains {|} characters in them, this integer
935 // will specify which alternative to use. For example "{x|y|z}" with Variant
936 // == 1, will expand to "y".
940 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
941 // layout, the asmwriter can actually generate output in this columns (in
942 // verbose-asm mode). These two values indicate the width of the first column
943 // (the "opcode" area) and the width to reserve for subsequent operands. When
944 // verbose asm mode is enabled, operands will be indented to respect this.
945 int FirstOperandColumn = -1;
947 // OperandSpacing - Space between operand columns.
948 int OperandSpacing = -1;
950 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
951 // generation of the printInstruction() method. For MC printers, it takes
952 // an MCInstr* operand, otherwise it takes a MachineInstr*.
953 bit isMCAsmWriter = 0;
955 def DefaultAsmWriter : AsmWriter;
958 //===----------------------------------------------------------------------===//
959 // Target - This class contains the "global" target information
962 // InstructionSet - Instruction set description for this target.
963 InstrInfo InstructionSet;
965 // AssemblyParsers - The AsmParser instances available for this target.
966 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
968 /// AssemblyParserVariants - The AsmParserVariant instances available for
970 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
972 // AssemblyWriters - The AsmWriter instances available for this target.
973 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
976 //===----------------------------------------------------------------------===//
977 // SubtargetFeature - A characteristic of the chip set.
979 class SubtargetFeature<string n, string a, string v, string d,
980 list<SubtargetFeature> i = []> {
981 // Name - Feature name. Used by command line (-mattr=) to determine the
982 // appropriate target chip.
986 // Attribute - Attribute to be set by feature.
988 string Attribute = a;
990 // Value - Value the attribute to be set to by feature.
994 // Desc - Feature description. Used by command line (-mattr=) to display help
999 // Implies - Features that this feature implies are present. If one of those
1000 // features isn't set, then this one shouldn't be set either.
1002 list<SubtargetFeature> Implies = i;
1005 //===----------------------------------------------------------------------===//
1006 // Processor chip sets - These values represent each of the chip sets supported
1007 // by the scheduler. Each Processor definition requires corresponding
1008 // instruction itineraries.
1010 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1011 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1012 // appropriate target chip.
1016 // SchedModel - The machine model for scheduling and instruction cost.
1018 SchedMachineModel SchedModel = NoSchedModel;
1020 // ProcItin - The scheduling information for the target processor.
1022 ProcessorItineraries ProcItin = pi;
1024 // Features - list of
1025 list<SubtargetFeature> Features = f;
1028 // ProcessorModel allows subtargets to specify the more general
1029 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1030 // gradually move to this newer form.
1032 // Although this class always passes NoItineraries to the Processor
1033 // class, the SchedMachineModel may still define valid Itineraries.
1034 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1035 : Processor<n, NoItineraries, f> {
1039 //===----------------------------------------------------------------------===//
1040 // InstrMapping - This class is used to create mapping tables to relate
1041 // instructions with each other based on the values specified in RowFields,
1042 // ColFields, KeyCol and ValueCols.
1044 class InstrMapping {
1045 // FilterClass - Used to limit search space only to the instructions that
1046 // define the relationship modeled by this InstrMapping record.
1049 // RowFields - List of fields/attributes that should be same for all the
1050 // instructions in a row of the relation table. Think of this as a set of
1051 // properties shared by all the instructions related by this relationship
1052 // model and is used to categorize instructions into subgroups. For instance,
1053 // if we want to define a relation that maps 'Add' instruction to its
1054 // predicated forms, we can define RowFields like this:
1056 // let RowFields = BaseOp
1057 // All add instruction predicated/non-predicated will have to set their BaseOp
1058 // to the same value.
1060 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1061 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1062 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1063 list<string> RowFields = [];
1065 // List of fields/attributes that are same for all the instructions
1066 // in a column of the relation table.
1067 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1068 // based on the 'predSense' values. All the instruction in a specific
1069 // column have the same value and it is fixed for the column according
1070 // to the values set in 'ValueCols'.
1071 list<string> ColFields = [];
1073 // Values for the fields/attributes listed in 'ColFields'.
1074 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1075 // that models this relation) should be non-predicated.
1076 // In the example above, 'Add' is the key instruction.
1077 list<string> KeyCol = [];
1079 // List of values for the fields/attributes listed in 'ColFields', one for
1080 // each column in the relation table.
1082 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1083 // table. First column requires all the instructions to have predSense
1084 // set to 'true' and second column requires it to be 'false'.
1085 list<list<string> > ValueCols = [];
1088 //===----------------------------------------------------------------------===//
1089 // Pull in the common support for calling conventions.
1091 include "llvm/Target/TargetCallingConv.td"
1093 //===----------------------------------------------------------------------===//
1094 // Pull in the common support for DAG isel generation.
1096 include "llvm/Target/TargetSelectionDAG.td"