1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<list<SubRegIndex> comps = []> {
26 string Namespace = "";
28 // ComposedOf - A list of two SubRegIndex instances, [A, B].
29 // This indicates that this SubRegIndex is the result of composing A and B.
30 list<SubRegIndex> ComposedOf = comps;
32 // CoveringSubRegIndices - A list of two or more sub-register indexes that
33 // cover this sub-register.
35 // This field should normally be left blank as TableGen can infer it.
37 // TableGen automatically detects sub-registers that straddle the registers
38 // in the SubRegs field of a Register definition. For example:
40 // Q0 = dsub_0 -> D0, dsub_1 -> D1
41 // Q1 = dsub_0 -> D2, dsub_1 -> D3
42 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
43 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
45 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
46 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
47 // CoveringSubRegIndices = [dsub_1, dsub_2].
48 list<SubRegIndex> CoveringSubRegIndices = [];
51 // RegAltNameIndex - The alternate name set to use for register operands of
52 // this register class when printing.
53 class RegAltNameIndex {
54 string Namespace = "";
56 def NoRegAltName : RegAltNameIndex;
58 // Register - You should define one instance of this class for each register
59 // in the target machine. String n will become the "name" of the register.
60 class Register<string n, list<string> altNames = []> {
61 string Namespace = "";
63 list<string> AltNames = altNames;
65 // Aliases - A list of registers that this register overlaps with. A read or
66 // modification of this register can potentially read or modify the aliased
68 list<Register> Aliases = [];
70 // SubRegs - A list of registers that are parts of this register. Note these
71 // are "immediate" sub-registers and the registers within the list do not
72 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
74 list<Register> SubRegs = [];
76 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
77 // to address it. Sub-sub-register indices are automatically inherited from
79 list<SubRegIndex> SubRegIndices = [];
81 // RegAltNameIndices - The alternate name indices which are valid for this
83 list<RegAltNameIndex> RegAltNameIndices = [];
85 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
86 // These values can be determined by locating the <target>.h file in the
87 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
88 // order of these names correspond to the enumeration used by gcc. A value of
89 // -1 indicates that the gcc number is undefined and -2 that register number
90 // is invalid for this mode/flavour.
91 list<int> DwarfNumbers = [];
93 // CostPerUse - Additional cost of instructions using this register compared
94 // to other registers in its class. The register allocator will try to
95 // minimize the number of instructions using a register with a CostPerUse.
96 // This is used by the x86-64 and ARM Thumb targets where some registers
97 // require larger instruction encodings.
100 // CoveredBySubRegs - When this bit is set, the value of this register is
101 // completely determined by the value of its sub-registers. For example, the
102 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
103 // covered by its sub-register AX.
104 bit CoveredBySubRegs = 0;
106 // HWEncoding - The target specific hardware encoding for this register.
107 bits<16> HWEncoding = 0;
110 // RegisterWithSubRegs - This can be used to define instances of Register which
111 // need to specify sub-registers.
112 // List "subregs" specifies which registers are sub-registers to this one. This
113 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
114 // This allows the code generator to be careful not to put two values with
115 // overlapping live ranges into registers which alias.
116 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
117 let SubRegs = subregs;
120 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
121 // of Operand's that are legal as type qualifiers in DAG patterns. This should
122 // only ever be used for defining multiclasses that are polymorphic over both
123 // RegisterClass's and other Operand's.
126 // RegisterClass - Now that all of the registers are defined, and aliases
127 // between registers are defined, specify which registers belong to which
128 // register classes. This also defines the default allocation order of
129 // registers by register allocators.
131 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
132 dag regList, RegAltNameIndex idx = NoRegAltName>
134 string Namespace = namespace;
136 // RegType - Specify the list ValueType of the registers in this register
137 // class. Note that all registers in a register class must have the same
138 // ValueTypes. This is a list because some targets permit storing different
139 // types in same register, for example vector values with 128-bit total size,
140 // but different count/size of items, like SSE on x86.
142 list<ValueType> RegTypes = regTypes;
144 // Size - Specify the spill size in bits of the registers. A default value of
145 // zero lets tablgen pick an appropriate size.
148 // Alignment - Specify the alignment required of the registers when they are
149 // stored or loaded to memory.
151 int Alignment = alignment;
153 // CopyCost - This value is used to specify the cost of copying a value
154 // between two registers in this register class. The default value is one
155 // meaning it takes a single instruction to perform the copying. A negative
156 // value means copying is extremely expensive or impossible.
159 // MemberList - Specify which registers are in this class. If the
160 // allocation_order_* method are not specified, this also defines the order of
161 // allocation used by the register allocator.
163 dag MemberList = regList;
165 // AltNameIndex - The alternate register name to use when printing operands
166 // of this register class. Every register in the register class must have
167 // a valid alternate name for the given index.
168 RegAltNameIndex altNameIndex = idx;
170 // isAllocatable - Specify that the register class can be used for virtual
171 // registers and register allocation. Some register classes are only used to
172 // model instruction operand constraints, and should have isAllocatable = 0.
173 bit isAllocatable = 1;
175 // AltOrders - List of alternative allocation orders. The default order is
176 // MemberList itself, and that is good enough for most targets since the
177 // register allocators automatically remove reserved registers and move
178 // callee-saved registers to the end.
179 list<dag> AltOrders = [];
181 // AltOrderSelect - The body of a function that selects the allocation order
182 // to use in a given machine function. The code will be inserted in a
183 // function like this:
185 // static inline unsigned f(const MachineFunction &MF) { ... }
187 // The function should return 0 to select the default order defined by
188 // MemberList, 1 to select the first AltOrders entry and so on.
189 code AltOrderSelect = [{}];
192 // The memberList in a RegisterClass is a dag of set operations. TableGen
193 // evaluates these set operations and expand them into register lists. These
194 // are the most common operation, see test/TableGen/SetTheory.td for more
195 // examples of what is possible:
197 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
198 // register class, or a sub-expression. This is also the way to simply list
201 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
203 // (and GPR, CSR) - Set intersection. All registers from the first set that are
204 // also in the second set.
206 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
207 // numbered registers. Takes an optional 4th operand which is a stride to use
208 // when generating the sequence.
210 // (shl GPR, 4) - Remove the first N elements.
212 // (trunc GPR, 4) - Truncate after the first N elements.
214 // (rotl GPR, 1) - Rotate N places to the left.
216 // (rotr GPR, 1) - Rotate N places to the right.
218 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
220 // (interleave A, B, ...) - Interleave the elements from each argument list.
222 // All of these operators work on ordered sets, not lists. That means
223 // duplicates are removed from sub-expressions.
225 // Set operators. The rest is defined in TargetSelectionDAG.td.
230 // RegisterTuples - Automatically generate super-registers by forming tuples of
231 // sub-registers. This is useful for modeling register sequence constraints
232 // with pseudo-registers that are larger than the architectural registers.
234 // The sub-register lists are zipped together:
236 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
238 // Generates the same registers as:
240 // let SubRegIndices = [sube, subo] in {
241 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
242 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
245 // The generated pseudo-registers inherit super-classes and fields from their
246 // first sub-register. Most fields from the Register class are inferred, and
247 // the AsmName and Dwarf numbers are cleared.
249 // RegisterTuples instances can be used in other set operations to form
250 // register classes and so on. This is the only way of using the generated
252 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
253 // SubRegs - N lists of registers to be zipped up. Super-registers are
254 // synthesized from the first element of each SubRegs list, the second
255 // element and so on.
256 list<dag> SubRegs = Regs;
258 // SubRegIndices - N SubRegIndex instances. This provides the names of the
259 // sub-registers in the synthesized super-registers.
260 list<SubRegIndex> SubRegIndices = Indices;
264 //===----------------------------------------------------------------------===//
265 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
266 // to the register numbering used by gcc and gdb. These values are used by a
267 // debug information writer to describe where values may be located during
269 class DwarfRegNum<list<int> Numbers> {
270 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
271 // These values can be determined by locating the <target>.h file in the
272 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
273 // order of these names correspond to the enumeration used by gcc. A value of
274 // -1 indicates that the gcc number is undefined and -2 that register number
275 // is invalid for this mode/flavour.
276 list<int> DwarfNumbers = Numbers;
279 // DwarfRegAlias - This class declares that a given register uses the same dwarf
280 // numbers as another one. This is useful for making it clear that the two
281 // registers do have the same number. It also lets us build a mapping
282 // from dwarf register number to llvm register.
283 class DwarfRegAlias<Register reg> {
284 Register DwarfAlias = reg;
287 //===----------------------------------------------------------------------===//
288 // Pull in the common support for scheduling
290 include "llvm/Target/TargetSchedule.td"
292 class Predicate; // Forward def
294 //===----------------------------------------------------------------------===//
295 // Instruction set description - These classes correspond to the C++ classes in
296 // the Target/TargetInstrInfo.h file.
299 string Namespace = "";
301 dag OutOperandList; // An dag containing the MI def operand list.
302 dag InOperandList; // An dag containing the MI use operand list.
303 string AsmString = ""; // The .s format to print the instruction with.
305 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
306 // otherwise, uninitialized.
309 // The follow state will eventually be inferred automatically from the
310 // instruction pattern.
312 list<Register> Uses = []; // Default to using no non-operand registers
313 list<Register> Defs = []; // Default to modifying no non-operand registers
315 // Predicates - List of predicates which will be turned into isel matching
317 list<Predicate> Predicates = [];
319 // Size - Size of encoded instruction, or zero if the size cannot be determined
323 // DecoderNamespace - The "namespace" in which this instruction exists, on
324 // targets like ARM which multiple ISA namespaces exist.
325 string DecoderNamespace = "";
327 // Code size, for instruction selection.
328 // FIXME: What does this actually mean?
331 // Added complexity passed onto matching pattern.
332 int AddedComplexity = 0;
334 // These bits capture information about the high-level semantics of the
336 bit isReturn = 0; // Is this instruction a return instruction?
337 bit isBranch = 0; // Is this instruction a branch instruction?
338 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
339 bit isCompare = 0; // Is this instruction a comparison instruction?
340 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
341 bit isBitcast = 0; // Is this instruction a bitcast instruction?
342 bit isSelect = 0; // Is this instruction a select instruction?
343 bit isBarrier = 0; // Can control flow fall through this instruction?
344 bit isCall = 0; // Is this instruction a call instruction?
345 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
346 bit mayLoad = ?; // Is it possible for this inst to read memory?
347 bit mayStore = ?; // Is it possible for this inst to write memory?
348 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
349 bit isCommutable = 0; // Is this 3 operand instruction commutable?
350 bit isTerminator = 0; // Is this part of the terminator for a basic block?
351 bit isReMaterializable = 0; // Is this instruction re-materializable?
352 bit isPredicable = 0; // Is this instruction predicable?
353 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
354 bit usesCustomInserter = 0; // Pseudo instr needing special help.
355 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
356 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
357 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
358 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
359 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
360 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
361 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
362 // If so, won't have encoding information for
363 // the [MC]CodeEmitter stuff.
365 // Side effect flags - When set, the flags have these meanings:
367 // hasSideEffects - The instruction has side effects that are not
368 // captured by any operands of the instruction or other flags.
370 // neverHasSideEffects - Set on an instruction with no pattern if it has no
372 bit hasSideEffects = ?;
373 bit neverHasSideEffects = 0;
375 // Is this instruction a "real" instruction (with a distinct machine
376 // encoding), or is it a pseudo instruction used for codegen modeling
378 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
379 // instructions can (and often do) still have encoding information
380 // associated with them. Once we've migrated all of them over to true
381 // pseudo-instructions that are lowered to real instructions prior to
382 // the printer/emitter, we can remove this attribute and just use isPseudo.
384 // The intended use is:
385 // isPseudo: Does not have encoding information and should be expanded,
386 // at the latest, during lowering to MCInst.
388 // isCodeGenOnly: Does have encoding information and can go through to the
389 // CodeEmitter unchanged, but duplicates a canonical instruction
390 // definition's encoding and should be ignored when constructing the
391 // assembler match tables.
392 bit isCodeGenOnly = 0;
394 // Is this instruction a pseudo instruction for use by the assembler parser.
395 bit isAsmParserOnly = 0;
397 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
399 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
401 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
402 /// be encoded into the output machineinstr.
403 string DisableEncoding = "";
405 string PostEncoderMethod = "";
406 string DecoderMethod = "";
408 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
409 bits<64> TSFlags = 0;
411 ///@name Assembler Parser Support
414 string AsmMatchConverter = "";
416 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
417 /// two-operand matcher inst-alias for a three operand instruction.
418 /// For example, the arm instruction "add r3, r3, r5" can be written
419 /// as "add r3, r5". The constraint is of the same form as a tied-operand
420 /// constraint. For example, "$Rn = $Rd".
421 string TwoOperandAliasConstraint = "";
426 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
427 /// Which instruction it expands to and how the operands map from the
429 class PseudoInstExpansion<dag Result> {
430 dag ResultInst = Result; // The instruction to generate.
434 /// Predicates - These are extra conditionals which are turned into instruction
435 /// selector matching code. Currently each predicate is just a string.
436 class Predicate<string cond> {
437 string CondString = cond;
439 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
440 /// matcher, this is true. Targets should set this by inheriting their
441 /// feature from the AssemblerPredicate class in addition to Predicate.
442 bit AssemblerMatcherPredicate = 0;
444 /// AssemblerCondString - Name of the subtarget feature being tested used
445 /// as alternative condition string used for assembler matcher.
446 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
447 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
448 /// It can also list multiple features separated by ",".
449 /// e.g. "ModeThumb,FeatureThumb2" is translated to
450 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
451 string AssemblerCondString = "";
453 /// PredicateName - User-level name to use for the predicate. Mainly for use
454 /// in diagnostics such as missing feature errors in the asm matcher.
455 string PredicateName = "";
458 /// NoHonorSignDependentRounding - This predicate is true if support for
459 /// sign-dependent-rounding is not enabled.
460 def NoHonorSignDependentRounding
461 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
463 class Requires<list<Predicate> preds> {
464 list<Predicate> Predicates = preds;
467 /// ops definition - This is just a simple marker used to identify the operand
468 /// list for an instruction. outs and ins are identical both syntactically and
469 /// semanticallyr; they are used to define def operands and use operands to
470 /// improve readibility. This should be used like this:
471 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
476 /// variable_ops definition - Mark this instruction as taking a variable number
481 /// PointerLikeRegClass - Values that are designed to have pointer width are
482 /// derived from this. TableGen treats the register class as having a symbolic
483 /// type that it doesn't know, and resolves the actual regclass to use by using
484 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
485 class PointerLikeRegClass<int Kind> {
486 int RegClassKind = Kind;
490 /// ptr_rc definition - Mark this operand as being a pointer value whose
491 /// register class is resolved dynamically via a callback to TargetInstrInfo.
492 /// FIXME: We should probably change this to a class which contain a list of
493 /// flags. But currently we have but one flag.
494 def ptr_rc : PointerLikeRegClass<0>;
496 /// unknown definition - Mark this operand as being of unknown type, causing
497 /// it to be resolved by inference in the context it is used.
499 def unknown : unknown_class;
501 /// AsmOperandClass - Representation for the kinds of operands which the target
502 /// specific parser can create and the assembly matcher may need to distinguish.
504 /// Operand classes are used to define the order in which instructions are
505 /// matched, to ensure that the instruction which gets matched for any
506 /// particular list of operands is deterministic.
508 /// The target specific parser must be able to classify a parsed operand into a
509 /// unique class which does not partially overlap with any other classes. It can
510 /// match a subset of some other class, in which case the super class field
511 /// should be defined.
512 class AsmOperandClass {
513 /// The name to use for this class, which should be usable as an enum value.
516 /// The super classes of this operand.
517 list<AsmOperandClass> SuperClasses = [];
519 /// The name of the method on the target specific operand to call to test
520 /// whether the operand is an instance of this class. If not set, this will
521 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
522 /// signature should be:
523 /// bool isFoo() const;
524 string PredicateMethod = ?;
526 /// The name of the method on the target specific operand to call to add the
527 /// target specific operand to an MCInst. If not set, this will default to
528 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
529 /// signature should be:
530 /// void addFooOperands(MCInst &Inst, unsigned N) const;
531 string RenderMethod = ?;
533 /// The name of the method on the target specific operand to call to custom
534 /// handle the operand parsing. This is useful when the operands do not relate
535 /// to immediates or registers and are very instruction specific (as flags to
536 /// set in a processor register, coprocessor number, ...).
537 string ParserMethod = ?;
539 // The diagnostic type to present when referencing this operand in a
540 // match failure error message. By default, use a generic "invalid operand"
541 // diagnostic. The target AsmParser maps these codes to text.
542 string DiagnosticType = "";
545 def ImmAsmOperand : AsmOperandClass {
549 /// Operand Types - These provide the built-in operand types that may be used
550 /// by a target. Targets can optionally provide their own operand types as
551 /// needed, though this should not be needed for RISC targets.
552 class Operand<ValueType ty> : DAGOperand {
554 string PrintMethod = "printOperand";
555 string EncoderMethod = "";
556 string DecoderMethod = "";
557 string AsmOperandLowerMethod = ?;
558 string OperandType = "OPERAND_UNKNOWN";
559 dag MIOperandInfo = (ops);
561 // ParserMatchClass - The "match class" that operands of this type fit
562 // in. Match classes are used to define the order in which instructions are
563 // match, to ensure that which instructions gets matched is deterministic.
565 // The target specific parser must be able to classify an parsed operand into
566 // a unique class, which does not partially overlap with any other classes. It
567 // can match a subset of some other class, in which case the AsmOperandClass
568 // should declare the other operand as one of its super classes.
569 AsmOperandClass ParserMatchClass = ImmAsmOperand;
572 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
574 // RegClass - The register class of the operand.
575 RegisterClass RegClass = regclass;
576 // PrintMethod - The target method to call to print register operands of
577 // this type. The method normally will just use an alt-name index to look
578 // up the name to print. Default to the generic printOperand().
579 string PrintMethod = pm;
580 // ParserMatchClass - The "match class" that operands of this type fit
581 // in. Match classes are used to define the order in which instructions are
582 // match, to ensure that which instructions gets matched is deterministic.
584 // The target specific parser must be able to classify an parsed operand into
585 // a unique class, which does not partially overlap with any other classes. It
586 // can match a subset of some other class, in which case the AsmOperandClass
587 // should declare the other operand as one of its super classes.
588 AsmOperandClass ParserMatchClass;
591 let OperandType = "OPERAND_IMMEDIATE" in {
592 def i1imm : Operand<i1>;
593 def i8imm : Operand<i8>;
594 def i16imm : Operand<i16>;
595 def i32imm : Operand<i32>;
596 def i64imm : Operand<i64>;
598 def f32imm : Operand<f32>;
599 def f64imm : Operand<f64>;
602 /// zero_reg definition - Special node to stand for the zero register.
606 /// OperandWithDefaultOps - This Operand class can be used as the parent class
607 /// for an Operand that needs to be initialized with a default value if
608 /// no value is supplied in a pattern. This class can be used to simplify the
609 /// pattern definitions for instructions that have target specific flags
610 /// encoded as immediate operands.
611 class OperandWithDefaultOps<ValueType ty, dag defaultops>
613 dag DefaultOps = defaultops;
616 /// PredicateOperand - This can be used to define a predicate operand for an
617 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
618 /// AlwaysVal specifies the value of this predicate when set to "always
620 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
621 : OperandWithDefaultOps<ty, AlwaysVal> {
622 let MIOperandInfo = OpTypes;
625 /// OptionalDefOperand - This is used to define a optional definition operand
626 /// for an instruction. DefaultOps is the register the operand represents if
627 /// none is supplied, e.g. zero_reg.
628 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
629 : OperandWithDefaultOps<ty, defaultops> {
630 let MIOperandInfo = OpTypes;
634 // InstrInfo - This class should only be instantiated once to provide parameters
635 // which are global to the target machine.
638 // Target can specify its instructions in either big or little-endian formats.
639 // For instance, while both Sparc and PowerPC are big-endian platforms, the
640 // Sparc manual specifies its instructions in the format [31..0] (big), while
641 // PowerPC specifies them using the format [0..31] (little).
642 bit isLittleEndianEncoding = 0;
644 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
645 // by default, and TableGen will infer their value from the instruction
646 // pattern when possible.
648 // Normally, TableGen will issue an error it it can't infer the value of a
649 // property that hasn't been set explicitly. When guessInstructionProperties
650 // is set, it will guess a safe value instead.
652 // This option is a temporary migration help. It will go away.
653 bit guessInstructionProperties = 1;
656 // Standard Pseudo Instructions.
657 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
658 // Only these instructions are allowed in the TargetOpcode namespace.
659 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
660 def PHI : Instruction {
661 let OutOperandList = (outs);
662 let InOperandList = (ins variable_ops);
663 let AsmString = "PHINODE";
665 def INLINEASM : Instruction {
666 let OutOperandList = (outs);
667 let InOperandList = (ins variable_ops);
669 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
671 def PROLOG_LABEL : Instruction {
672 let OutOperandList = (outs);
673 let InOperandList = (ins i32imm:$id);
676 let isNotDuplicable = 1;
678 def EH_LABEL : Instruction {
679 let OutOperandList = (outs);
680 let InOperandList = (ins i32imm:$id);
683 let isNotDuplicable = 1;
685 def GC_LABEL : Instruction {
686 let OutOperandList = (outs);
687 let InOperandList = (ins i32imm:$id);
690 let isNotDuplicable = 1;
692 def KILL : Instruction {
693 let OutOperandList = (outs);
694 let InOperandList = (ins variable_ops);
696 let neverHasSideEffects = 1;
698 def EXTRACT_SUBREG : Instruction {
699 let OutOperandList = (outs unknown:$dst);
700 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
702 let neverHasSideEffects = 1;
704 def INSERT_SUBREG : Instruction {
705 let OutOperandList = (outs unknown:$dst);
706 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
708 let neverHasSideEffects = 1;
709 let Constraints = "$supersrc = $dst";
711 def IMPLICIT_DEF : Instruction {
712 let OutOperandList = (outs unknown:$dst);
713 let InOperandList = (ins);
715 let neverHasSideEffects = 1;
716 let isReMaterializable = 1;
717 let isAsCheapAsAMove = 1;
719 def SUBREG_TO_REG : Instruction {
720 let OutOperandList = (outs unknown:$dst);
721 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
723 let neverHasSideEffects = 1;
725 def COPY_TO_REGCLASS : Instruction {
726 let OutOperandList = (outs unknown:$dst);
727 let InOperandList = (ins unknown:$src, i32imm:$regclass);
729 let neverHasSideEffects = 1;
730 let isAsCheapAsAMove = 1;
732 def DBG_VALUE : Instruction {
733 let OutOperandList = (outs);
734 let InOperandList = (ins variable_ops);
735 let AsmString = "DBG_VALUE";
736 let neverHasSideEffects = 1;
738 def REG_SEQUENCE : Instruction {
739 let OutOperandList = (outs unknown:$dst);
740 let InOperandList = (ins variable_ops);
742 let neverHasSideEffects = 1;
743 let isAsCheapAsAMove = 1;
745 def COPY : Instruction {
746 let OutOperandList = (outs unknown:$dst);
747 let InOperandList = (ins unknown:$src);
749 let neverHasSideEffects = 1;
750 let isAsCheapAsAMove = 1;
752 def BUNDLE : Instruction {
753 let OutOperandList = (outs);
754 let InOperandList = (ins variable_ops);
755 let AsmString = "BUNDLE";
757 def LIFETIME_START : Instruction {
758 let OutOperandList = (outs);
759 let InOperandList = (ins i32imm:$id);
760 let AsmString = "LIFETIME_START";
761 let neverHasSideEffects = 1;
763 def LIFETIME_END : Instruction {
764 let OutOperandList = (outs);
765 let InOperandList = (ins i32imm:$id);
766 let AsmString = "LIFETIME_END";
767 let neverHasSideEffects = 1;
771 //===----------------------------------------------------------------------===//
772 // AsmParser - This class can be implemented by targets that wish to implement
775 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
776 // syntax on X86 for example).
779 // AsmParserClassName - This specifies the suffix to use for the asmparser
780 // class. Generated AsmParser classes are always prefixed with the target
782 string AsmParserClassName = "AsmParser";
784 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
785 // function of the AsmParser class to call on every matched instruction.
786 // This can be used to perform target specific instruction post-processing.
787 string AsmParserInstCleanup = "";
789 //ShouldEmitMatchRegisterName - Set to false if the target needs a hand
790 //written register name matcher
791 bit ShouldEmitMatchRegisterName = 1;
793 def DefaultAsmParser : AsmParser;
795 //===----------------------------------------------------------------------===//
796 // AsmParserVariant - Subtargets can have multiple different assembly parsers
797 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
798 // implemented by targets to describe such variants.
800 class AsmParserVariant {
801 // Variant - AsmParsers can be of multiple different variants. Variants are
802 // used to support targets that need to parser multiple formats for the
803 // assembly language.
806 // CommentDelimiter - If given, the delimiter string used to recognize
807 // comments which are hard coded in the .td assembler strings for individual
809 string CommentDelimiter = "";
811 // RegisterPrefix - If given, the token prefix which indicates a register
812 // token. This is used by the matcher to automatically recognize hard coded
813 // register tokens as constrained registers, instead of tokens, for the
814 // purposes of matching.
815 string RegisterPrefix = "";
817 def DefaultAsmParserVariant : AsmParserVariant;
819 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
820 /// matches instructions and aliases.
821 class AssemblerPredicate<string cond, string name = ""> {
822 bit AssemblerMatcherPredicate = 1;
823 string AssemblerCondString = cond;
824 string PredicateName = name;
827 /// TokenAlias - This class allows targets to define assembler token
828 /// operand aliases. That is, a token literal operand which is equivalent
829 /// to another, canonical, token literal. For example, ARM allows:
830 /// vmov.u32 s4, #0 -> vmov.i32, #0
831 /// 'u32' is a more specific designator for the 32-bit integer type specifier
832 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
833 /// def : TokenAlias<".u32", ".i32">;
835 /// This works by marking the match class of 'From' as a subclass of the
836 /// match class of 'To'.
837 class TokenAlias<string From, string To> {
838 string FromToken = From;
842 /// MnemonicAlias - This class allows targets to define assembler mnemonic
843 /// aliases. This should be used when all forms of one mnemonic are accepted
844 /// with a different mnemonic. For example, X86 allows:
845 /// sal %al, 1 -> shl %al, 1
846 /// sal %ax, %cl -> shl %ax, %cl
847 /// sal %eax, %cl -> shl %eax, %cl
848 /// etc. Though "sal" is accepted with many forms, all of them are directly
849 /// translated to a shl, so it can be handled with (in the case of X86, it
850 /// actually has one for each suffix as well):
851 /// def : MnemonicAlias<"sal", "shl">;
853 /// Mnemonic aliases are mapped before any other translation in the match phase,
854 /// and do allow Requires predicates, e.g.:
856 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
857 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
859 class MnemonicAlias<string From, string To> {
860 string FromMnemonic = From;
861 string ToMnemonic = To;
863 // Predicates - Predicates that must be true for this remapping to happen.
864 list<Predicate> Predicates = [];
867 /// InstAlias - This defines an alternate assembly syntax that is allowed to
868 /// match an instruction that has a different (more canonical) assembly
870 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
871 string AsmString = Asm; // The .s format to match the instruction with.
872 dag ResultInst = Result; // The MCInst to generate.
873 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
875 // Predicates - Predicates that must be true for this to match.
876 list<Predicate> Predicates = [];
879 //===----------------------------------------------------------------------===//
880 // AsmWriter - This class can be implemented by targets that need to customize
881 // the format of the .s file writer.
883 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
884 // on X86 for example).
887 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
888 // class. Generated AsmWriter classes are always prefixed with the target
890 string AsmWriterClassName = "AsmPrinter";
892 // Variant - AsmWriters can be of multiple different variants. Variants are
893 // used to support targets that need to emit assembly code in ways that are
894 // mostly the same for different targets, but have minor differences in
895 // syntax. If the asmstring contains {|} characters in them, this integer
896 // will specify which alternative to use. For example "{x|y|z}" with Variant
897 // == 1, will expand to "y".
901 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
902 // layout, the asmwriter can actually generate output in this columns (in
903 // verbose-asm mode). These two values indicate the width of the first column
904 // (the "opcode" area) and the width to reserve for subsequent operands. When
905 // verbose asm mode is enabled, operands will be indented to respect this.
906 int FirstOperandColumn = -1;
908 // OperandSpacing - Space between operand columns.
909 int OperandSpacing = -1;
911 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
912 // generation of the printInstruction() method. For MC printers, it takes
913 // an MCInstr* operand, otherwise it takes a MachineInstr*.
914 bit isMCAsmWriter = 0;
916 def DefaultAsmWriter : AsmWriter;
919 //===----------------------------------------------------------------------===//
920 // Target - This class contains the "global" target information
923 // InstructionSet - Instruction set description for this target.
924 InstrInfo InstructionSet;
926 // AssemblyParsers - The AsmParser instances available for this target.
927 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
929 /// AssemblyParserVariants - The AsmParserVariant instances available for
931 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
933 // AssemblyWriters - The AsmWriter instances available for this target.
934 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
937 //===----------------------------------------------------------------------===//
938 // SubtargetFeature - A characteristic of the chip set.
940 class SubtargetFeature<string n, string a, string v, string d,
941 list<SubtargetFeature> i = []> {
942 // Name - Feature name. Used by command line (-mattr=) to determine the
943 // appropriate target chip.
947 // Attribute - Attribute to be set by feature.
949 string Attribute = a;
951 // Value - Value the attribute to be set to by feature.
955 // Desc - Feature description. Used by command line (-mattr=) to display help
960 // Implies - Features that this feature implies are present. If one of those
961 // features isn't set, then this one shouldn't be set either.
963 list<SubtargetFeature> Implies = i;
966 //===----------------------------------------------------------------------===//
967 // Processor chip sets - These values represent each of the chip sets supported
968 // by the scheduler. Each Processor definition requires corresponding
969 // instruction itineraries.
971 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
972 // Name - Chip set name. Used by command line (-mcpu=) to determine the
973 // appropriate target chip.
977 // SchedModel - The machine model for scheduling and instruction cost.
979 SchedMachineModel SchedModel = NoSchedModel;
981 // ProcItin - The scheduling information for the target processor.
983 ProcessorItineraries ProcItin = pi;
985 // Features - list of
986 list<SubtargetFeature> Features = f;
989 // ProcessorModel allows subtargets to specify the more general
990 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
991 // gradually move to this newer form.
993 // Although this class always passes NoItineraries to the Processor
994 // class, the SchedMachineModel may still define valid Itineraries.
995 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
996 : Processor<n, NoItineraries, f> {
1000 //===----------------------------------------------------------------------===//
1001 // Pull in the common support for calling conventions.
1003 include "llvm/Target/TargetCallingConv.td"
1005 //===----------------------------------------------------------------------===//
1006 // Pull in the common support for DAG isel generation.
1008 include "llvm/Target/TargetSelectionDAG.td"