1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // RegAltNameIndex - The alternate name set to use for register operands of
30 // this register class when printing.
31 class RegAltNameIndex {
32 string Namespace = "";
34 def NoRegAltName : RegAltNameIndex;
36 // Register - You should define one instance of this class for each register
37 // in the target machine. String n will become the "name" of the register.
38 class Register<string n, list<string> altNames = []> {
39 string Namespace = "";
41 list<string> AltNames = altNames;
43 // Aliases - A list of registers that this register overlaps with. A read or
44 // modification of this register can potentially read or modify the aliased
46 list<Register> Aliases = [];
48 // SubRegs - A list of registers that are parts of this register. Note these
49 // are "immediate" sub-registers and the registers within the list do not
50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
52 list<Register> SubRegs = [];
54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
55 // to address it. Sub-sub-register indices are automatically inherited from
57 list<SubRegIndex> SubRegIndices = [];
59 // RegAltNameIndices - The alternate name indices which are valid for this
61 list<RegAltNameIndex> RegAltNameIndices = [];
63 // CompositeIndices - Specify subreg indices that don't correspond directly to
64 // a register in SubRegs and are not inherited. The following formats are
67 // (a) Identity - Reg:a == Reg
68 // (a b) Alias - Reg:a == Reg:b
69 // (a b,c) Composite - Reg:a == (Reg:b):c
71 // This can be used to disambiguate a sub-sub-register that exists in more
72 // than one subregister and other weird stuff.
73 list<dag> CompositeIndices = [];
75 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
76 // These values can be determined by locating the <target>.h file in the
77 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
78 // order of these names correspond to the enumeration used by gcc. A value of
79 // -1 indicates that the gcc number is undefined and -2 that register number
80 // is invalid for this mode/flavour.
81 list<int> DwarfNumbers = [];
83 // CostPerUse - Additional cost of instructions using this register compared
84 // to other registers in its class. The register allocator will try to
85 // minimize the number of instructions using a register with a CostPerUse.
86 // This is used by the x86-64 and ARM Thumb targets where some registers
87 // require larger instruction encodings.
90 // CoveredBySubRegs - When this bit is set, the value of this register is
91 // completely determined by the value of its sub-registers. For example, the
92 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
93 // covered by its sub-register AX.
94 bit CoveredBySubRegs = 0;
97 // RegisterWithSubRegs - This can be used to define instances of Register which
98 // need to specify sub-registers.
99 // List "subregs" specifies which registers are sub-registers to this one. This
100 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
101 // This allows the code generator to be careful not to put two values with
102 // overlapping live ranges into registers which alias.
103 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
104 let SubRegs = subregs;
107 // RegisterClass - Now that all of the registers are defined, and aliases
108 // between registers are defined, specify which registers belong to which
109 // register classes. This also defines the default allocation order of
110 // registers by register allocators.
112 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
113 dag regList, RegAltNameIndex idx = NoRegAltName> {
114 string Namespace = namespace;
116 // RegType - Specify the list ValueType of the registers in this register
117 // class. Note that all registers in a register class must have the same
118 // ValueTypes. This is a list because some targets permit storing different
119 // types in same register, for example vector values with 128-bit total size,
120 // but different count/size of items, like SSE on x86.
122 list<ValueType> RegTypes = regTypes;
124 // Size - Specify the spill size in bits of the registers. A default value of
125 // zero lets tablgen pick an appropriate size.
128 // Alignment - Specify the alignment required of the registers when they are
129 // stored or loaded to memory.
131 int Alignment = alignment;
133 // CopyCost - This value is used to specify the cost of copying a value
134 // between two registers in this register class. The default value is one
135 // meaning it takes a single instruction to perform the copying. A negative
136 // value means copying is extremely expensive or impossible.
139 // MemberList - Specify which registers are in this class. If the
140 // allocation_order_* method are not specified, this also defines the order of
141 // allocation used by the register allocator.
143 dag MemberList = regList;
145 // AltNameIndex - The alternate register name to use when printing operands
146 // of this register class. Every register in the register class must have
147 // a valid alternate name for the given index.
148 RegAltNameIndex altNameIndex = idx;
150 // SubRegClasses - Specify the register class of subregisters as a list of
151 // dags: (RegClass SubRegIndex, SubRegindex, ...)
152 list<dag> SubRegClasses = [];
154 // isAllocatable - Specify that the register class can be used for virtual
155 // registers and register allocation. Some register classes are only used to
156 // model instruction operand constraints, and should have isAllocatable = 0.
157 bit isAllocatable = 1;
159 // AltOrders - List of alternative allocation orders. The default order is
160 // MemberList itself, and that is good enough for most targets since the
161 // register allocators automatically remove reserved registers and move
162 // callee-saved registers to the end.
163 list<dag> AltOrders = [];
165 // AltOrderSelect - The body of a function that selects the allocation order
166 // to use in a given machine function. The code will be inserted in a
167 // function like this:
169 // static inline unsigned f(const MachineFunction &MF) { ... }
171 // The function should return 0 to select the default order defined by
172 // MemberList, 1 to select the first AltOrders entry and so on.
173 code AltOrderSelect = [{}];
176 // The memberList in a RegisterClass is a dag of set operations. TableGen
177 // evaluates these set operations and expand them into register lists. These
178 // are the most common operation, see test/TableGen/SetTheory.td for more
179 // examples of what is possible:
181 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
182 // register class, or a sub-expression. This is also the way to simply list
185 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
187 // (and GPR, CSR) - Set intersection. All registers from the first set that are
188 // also in the second set.
190 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
191 // numbered registers.
193 // (shl GPR, 4) - Remove the first N elements.
195 // (trunc GPR, 4) - Truncate after the first N elements.
197 // (rotl GPR, 1) - Rotate N places to the left.
199 // (rotr GPR, 1) - Rotate N places to the right.
201 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
203 // All of these operators work on ordered sets, not lists. That means
204 // duplicates are removed from sub-expressions.
206 // Set operators. The rest is defined in TargetSelectionDAG.td.
210 // RegisterTuples - Automatically generate super-registers by forming tuples of
211 // sub-registers. This is useful for modeling register sequence constraints
212 // with pseudo-registers that are larger than the architectural registers.
214 // The sub-register lists are zipped together:
216 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
218 // Generates the same registers as:
220 // let SubRegIndices = [sube, subo] in {
221 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
222 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
225 // The generated pseudo-registers inherit super-classes and fields from their
226 // first sub-register. Most fields from the Register class are inferred, and
227 // the AsmName and Dwarf numbers are cleared.
229 // RegisterTuples instances can be used in other set operations to form
230 // register classes and so on. This is the only way of using the generated
232 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
233 // SubRegs - N lists of registers to be zipped up. Super-registers are
234 // synthesized from the first element of each SubRegs list, the second
235 // element and so on.
236 list<dag> SubRegs = Regs;
238 // SubRegIndices - N SubRegIndex instances. This provides the names of the
239 // sub-registers in the synthesized super-registers.
240 list<SubRegIndex> SubRegIndices = Indices;
242 // Compose sub-register indices like in a normal Register.
243 list<dag> CompositeIndices = [];
247 //===----------------------------------------------------------------------===//
248 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
249 // to the register numbering used by gcc and gdb. These values are used by a
250 // debug information writer to describe where values may be located during
252 class DwarfRegNum<list<int> Numbers> {
253 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
254 // These values can be determined by locating the <target>.h file in the
255 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
256 // order of these names correspond to the enumeration used by gcc. A value of
257 // -1 indicates that the gcc number is undefined and -2 that register number
258 // is invalid for this mode/flavour.
259 list<int> DwarfNumbers = Numbers;
262 // DwarfRegAlias - This class declares that a given register uses the same dwarf
263 // numbers as another one. This is useful for making it clear that the two
264 // registers do have the same number. It also lets us build a mapping
265 // from dwarf register number to llvm register.
266 class DwarfRegAlias<Register reg> {
267 Register DwarfAlias = reg;
270 //===----------------------------------------------------------------------===//
271 // Pull in the common support for scheduling
273 include "llvm/Target/TargetSchedule.td"
275 class Predicate; // Forward def
277 //===----------------------------------------------------------------------===//
278 // Instruction set description - These classes correspond to the C++ classes in
279 // the Target/TargetInstrInfo.h file.
282 string Namespace = "";
284 dag OutOperandList; // An dag containing the MI def operand list.
285 dag InOperandList; // An dag containing the MI use operand list.
286 string AsmString = ""; // The .s format to print the instruction with.
288 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
289 // otherwise, uninitialized.
292 // The follow state will eventually be inferred automatically from the
293 // instruction pattern.
295 list<Register> Uses = []; // Default to using no non-operand registers
296 list<Register> Defs = []; // Default to modifying no non-operand registers
298 // Predicates - List of predicates which will be turned into isel matching
300 list<Predicate> Predicates = [];
302 // Size - Size of encoded instruction, or zero if the size cannot be determined
306 // DecoderNamespace - The "namespace" in which this instruction exists, on
307 // targets like ARM which multiple ISA namespaces exist.
308 string DecoderNamespace = "";
310 // Code size, for instruction selection.
311 // FIXME: What does this actually mean?
314 // Added complexity passed onto matching pattern.
315 int AddedComplexity = 0;
317 // These bits capture information about the high-level semantics of the
319 bit isReturn = 0; // Is this instruction a return instruction?
320 bit isBranch = 0; // Is this instruction a branch instruction?
321 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
322 bit isCompare = 0; // Is this instruction a comparison instruction?
323 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
324 bit isBitcast = 0; // Is this instruction a bitcast instruction?
325 bit isBarrier = 0; // Can control flow fall through this instruction?
326 bit isCall = 0; // Is this instruction a call instruction?
327 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
328 bit mayLoad = 0; // Is it possible for this inst to read memory?
329 bit mayStore = 0; // Is it possible for this inst to write memory?
330 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
331 bit isCommutable = 0; // Is this 3 operand instruction commutable?
332 bit isTerminator = 0; // Is this part of the terminator for a basic block?
333 bit isReMaterializable = 0; // Is this instruction re-materializable?
334 bit isPredicable = 0; // Is this instruction predicable?
335 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
336 bit usesCustomInserter = 0; // Pseudo instr needing special help.
337 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
338 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
339 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
340 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
341 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
342 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
343 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
344 // If so, won't have encoding information for
345 // the [MC]CodeEmitter stuff.
347 // Side effect flags - When set, the flags have these meanings:
349 // hasSideEffects - The instruction has side effects that are not
350 // captured by any operands of the instruction or other flags.
352 // neverHasSideEffects - Set on an instruction with no pattern if it has no
354 bit hasSideEffects = 0;
355 bit neverHasSideEffects = 0;
357 // Is this instruction a "real" instruction (with a distinct machine
358 // encoding), or is it a pseudo instruction used for codegen modeling
360 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
361 // instructions can (and often do) still have encoding information
362 // associated with them. Once we've migrated all of them over to true
363 // pseudo-instructions that are lowered to real instructions prior to
364 // the printer/emitter, we can remove this attribute and just use isPseudo.
366 // The intended use is:
367 // isPseudo: Does not have encoding information and should be expanded,
368 // at the latest, during lowering to MCInst.
370 // isCodeGenOnly: Does have encoding information and can go through to the
371 // CodeEmitter unchanged, but duplicates a canonical instruction
372 // definition's encoding and should be ignored when constructing the
373 // assembler match tables.
374 bit isCodeGenOnly = 0;
376 // Is this instruction a pseudo instruction for use by the assembler parser.
377 bit isAsmParserOnly = 0;
379 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
381 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
383 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
384 /// be encoded into the output machineinstr.
385 string DisableEncoding = "";
387 string PostEncoderMethod = "";
388 string DecoderMethod = "";
390 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
391 bits<64> TSFlags = 0;
393 ///@name Assembler Parser Support
396 string AsmMatchConverter = "";
401 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
402 /// Which instruction it expands to and how the operands map from the
404 class PseudoInstExpansion<dag Result> {
405 dag ResultInst = Result; // The instruction to generate.
409 /// Predicates - These are extra conditionals which are turned into instruction
410 /// selector matching code. Currently each predicate is just a string.
411 class Predicate<string cond> {
412 string CondString = cond;
414 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
415 /// matcher, this is true. Targets should set this by inheriting their
416 /// feature from the AssemblerPredicate class in addition to Predicate.
417 bit AssemblerMatcherPredicate = 0;
419 /// AssemblerCondString - Name of the subtarget feature being tested used
420 /// as alternative condition string used for assembler matcher.
421 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
422 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
423 /// It can also list multiple features separated by ",".
424 /// e.g. "ModeThumb,FeatureThumb2" is translated to
425 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
426 string AssemblerCondString = "";
429 /// NoHonorSignDependentRounding - This predicate is true if support for
430 /// sign-dependent-rounding is not enabled.
431 def NoHonorSignDependentRounding
432 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
434 class Requires<list<Predicate> preds> {
435 list<Predicate> Predicates = preds;
438 /// ops definition - This is just a simple marker used to identify the operand
439 /// list for an instruction. outs and ins are identical both syntactically and
440 /// semanticallyr; they are used to define def operands and use operands to
441 /// improve readibility. This should be used like this:
442 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
447 /// variable_ops definition - Mark this instruction as taking a variable number
452 /// PointerLikeRegClass - Values that are designed to have pointer width are
453 /// derived from this. TableGen treats the register class as having a symbolic
454 /// type that it doesn't know, and resolves the actual regclass to use by using
455 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
456 class PointerLikeRegClass<int Kind> {
457 int RegClassKind = Kind;
461 /// ptr_rc definition - Mark this operand as being a pointer value whose
462 /// register class is resolved dynamically via a callback to TargetInstrInfo.
463 /// FIXME: We should probably change this to a class which contain a list of
464 /// flags. But currently we have but one flag.
465 def ptr_rc : PointerLikeRegClass<0>;
467 /// unknown definition - Mark this operand as being of unknown type, causing
468 /// it to be resolved by inference in the context it is used.
471 /// AsmOperandClass - Representation for the kinds of operands which the target
472 /// specific parser can create and the assembly matcher may need to distinguish.
474 /// Operand classes are used to define the order in which instructions are
475 /// matched, to ensure that the instruction which gets matched for any
476 /// particular list of operands is deterministic.
478 /// The target specific parser must be able to classify a parsed operand into a
479 /// unique class which does not partially overlap with any other classes. It can
480 /// match a subset of some other class, in which case the super class field
481 /// should be defined.
482 class AsmOperandClass {
483 /// The name to use for this class, which should be usable as an enum value.
486 /// The super classes of this operand.
487 list<AsmOperandClass> SuperClasses = [];
489 /// The name of the method on the target specific operand to call to test
490 /// whether the operand is an instance of this class. If not set, this will
491 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
492 /// signature should be:
493 /// bool isFoo() const;
494 string PredicateMethod = ?;
496 /// The name of the method on the target specific operand to call to add the
497 /// target specific operand to an MCInst. If not set, this will default to
498 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
499 /// signature should be:
500 /// void addFooOperands(MCInst &Inst, unsigned N) const;
501 string RenderMethod = ?;
503 /// The name of the method on the target specific operand to call to custom
504 /// handle the operand parsing. This is useful when the operands do not relate
505 /// to immediates or registers and are very instruction specific (as flags to
506 /// set in a processor register, coprocessor number, ...).
507 string ParserMethod = ?;
510 def ImmAsmOperand : AsmOperandClass {
514 /// Operand Types - These provide the built-in operand types that may be used
515 /// by a target. Targets can optionally provide their own operand types as
516 /// needed, though this should not be needed for RISC targets.
517 class Operand<ValueType ty> {
519 string PrintMethod = "printOperand";
520 string EncoderMethod = "";
521 string DecoderMethod = "";
522 string AsmOperandLowerMethod = ?;
523 string OperandType = "OPERAND_UNKNOWN";
524 dag MIOperandInfo = (ops);
526 // ParserMatchClass - The "match class" that operands of this type fit
527 // in. Match classes are used to define the order in which instructions are
528 // match, to ensure that which instructions gets matched is deterministic.
530 // The target specific parser must be able to classify an parsed operand into
531 // a unique class, which does not partially overlap with any other classes. It
532 // can match a subset of some other class, in which case the AsmOperandClass
533 // should declare the other operand as one of its super classes.
534 AsmOperandClass ParserMatchClass = ImmAsmOperand;
537 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
538 // RegClass - The register class of the operand.
539 RegisterClass RegClass = regclass;
540 // PrintMethod - The target method to call to print register operands of
541 // this type. The method normally will just use an alt-name index to look
542 // up the name to print. Default to the generic printOperand().
543 string PrintMethod = pm;
544 // ParserMatchClass - The "match class" that operands of this type fit
545 // in. Match classes are used to define the order in which instructions are
546 // match, to ensure that which instructions gets matched is deterministic.
548 // The target specific parser must be able to classify an parsed operand into
549 // a unique class, which does not partially overlap with any other classes. It
550 // can match a subset of some other class, in which case the AsmOperandClass
551 // should declare the other operand as one of its super classes.
552 AsmOperandClass ParserMatchClass;
555 let OperandType = "OPERAND_IMMEDIATE" in {
556 def i1imm : Operand<i1>;
557 def i8imm : Operand<i8>;
558 def i16imm : Operand<i16>;
559 def i32imm : Operand<i32>;
560 def i64imm : Operand<i64>;
562 def f32imm : Operand<f32>;
563 def f64imm : Operand<f64>;
566 /// zero_reg definition - Special node to stand for the zero register.
570 /// PredicateOperand - This can be used to define a predicate operand for an
571 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
572 /// AlwaysVal specifies the value of this predicate when set to "always
574 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
576 let MIOperandInfo = OpTypes;
577 dag DefaultOps = AlwaysVal;
580 /// OptionalDefOperand - This is used to define a optional definition operand
581 /// for an instruction. DefaultOps is the register the operand represents if
582 /// none is supplied, e.g. zero_reg.
583 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
585 let MIOperandInfo = OpTypes;
586 dag DefaultOps = defaultops;
590 // InstrInfo - This class should only be instantiated once to provide parameters
591 // which are global to the target machine.
594 // Target can specify its instructions in either big or little-endian formats.
595 // For instance, while both Sparc and PowerPC are big-endian platforms, the
596 // Sparc manual specifies its instructions in the format [31..0] (big), while
597 // PowerPC specifies them using the format [0..31] (little).
598 bit isLittleEndianEncoding = 0;
601 // Standard Pseudo Instructions.
602 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
603 // Only these instructions are allowed in the TargetOpcode namespace.
604 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
605 def PHI : Instruction {
606 let OutOperandList = (outs);
607 let InOperandList = (ins variable_ops);
608 let AsmString = "PHINODE";
610 def INLINEASM : Instruction {
611 let OutOperandList = (outs);
612 let InOperandList = (ins variable_ops);
614 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
616 def PROLOG_LABEL : Instruction {
617 let OutOperandList = (outs);
618 let InOperandList = (ins i32imm:$id);
621 let isNotDuplicable = 1;
623 def EH_LABEL : Instruction {
624 let OutOperandList = (outs);
625 let InOperandList = (ins i32imm:$id);
628 let isNotDuplicable = 1;
630 def GC_LABEL : Instruction {
631 let OutOperandList = (outs);
632 let InOperandList = (ins i32imm:$id);
635 let isNotDuplicable = 1;
637 def KILL : Instruction {
638 let OutOperandList = (outs);
639 let InOperandList = (ins variable_ops);
641 let neverHasSideEffects = 1;
643 def EXTRACT_SUBREG : Instruction {
644 let OutOperandList = (outs unknown:$dst);
645 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
647 let neverHasSideEffects = 1;
649 def INSERT_SUBREG : Instruction {
650 let OutOperandList = (outs unknown:$dst);
651 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
653 let neverHasSideEffects = 1;
654 let Constraints = "$supersrc = $dst";
656 def IMPLICIT_DEF : Instruction {
657 let OutOperandList = (outs unknown:$dst);
658 let InOperandList = (ins);
660 let neverHasSideEffects = 1;
661 let isReMaterializable = 1;
662 let isAsCheapAsAMove = 1;
664 def SUBREG_TO_REG : Instruction {
665 let OutOperandList = (outs unknown:$dst);
666 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
668 let neverHasSideEffects = 1;
670 def COPY_TO_REGCLASS : Instruction {
671 let OutOperandList = (outs unknown:$dst);
672 let InOperandList = (ins unknown:$src, i32imm:$regclass);
674 let neverHasSideEffects = 1;
675 let isAsCheapAsAMove = 1;
677 def DBG_VALUE : Instruction {
678 let OutOperandList = (outs);
679 let InOperandList = (ins variable_ops);
680 let AsmString = "DBG_VALUE";
681 let neverHasSideEffects = 1;
683 def REG_SEQUENCE : Instruction {
684 let OutOperandList = (outs unknown:$dst);
685 let InOperandList = (ins variable_ops);
687 let neverHasSideEffects = 1;
688 let isAsCheapAsAMove = 1;
690 def COPY : Instruction {
691 let OutOperandList = (outs unknown:$dst);
692 let InOperandList = (ins unknown:$src);
694 let neverHasSideEffects = 1;
695 let isAsCheapAsAMove = 1;
697 def BUNDLE : Instruction {
698 let OutOperandList = (outs);
699 let InOperandList = (ins variable_ops);
700 let AsmString = "BUNDLE";
704 //===----------------------------------------------------------------------===//
705 // AsmParser - This class can be implemented by targets that wish to implement
708 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
709 // syntax on X86 for example).
712 // AsmParserClassName - This specifies the suffix to use for the asmparser
713 // class. Generated AsmParser classes are always prefixed with the target
715 string AsmParserClassName = "AsmParser";
717 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
718 // function of the AsmParser class to call on every matched instruction.
719 // This can be used to perform target specific instruction post-processing.
720 string AsmParserInstCleanup = "";
722 def DefaultAsmParser : AsmParser;
724 //===----------------------------------------------------------------------===//
725 // AsmParserVariant - Subtargets can have multiple different assembly parsers
726 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
727 // implemented by targets to describe such variants.
729 class AsmParserVariant {
730 // Variant - AsmParsers can be of multiple different variants. Variants are
731 // used to support targets that need to parser multiple formats for the
732 // assembly language.
735 // CommentDelimiter - If given, the delimiter string used to recognize
736 // comments which are hard coded in the .td assembler strings for individual
738 string CommentDelimiter = "";
740 // RegisterPrefix - If given, the token prefix which indicates a register
741 // token. This is used by the matcher to automatically recognize hard coded
742 // register tokens as constrained registers, instead of tokens, for the
743 // purposes of matching.
744 string RegisterPrefix = "";
746 def DefaultAsmParserVariant : AsmParserVariant;
748 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
749 /// matches instructions and aliases.
750 class AssemblerPredicate<string cond> {
751 bit AssemblerMatcherPredicate = 1;
752 string AssemblerCondString = cond;
755 /// TokenAlias - This class allows targets to define assembler token
756 /// operand aliases. That is, a token literal operand which is equivalent
757 /// to another, canonical, token literal. For example, ARM allows:
758 /// vmov.u32 s4, #0 -> vmov.i32, #0
759 /// 'u32' is a more specific designator for the 32-bit integer type specifier
760 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
761 /// def : TokenAlias<".u32", ".i32">;
763 /// This works by marking the match class of 'From' as a subclass of the
764 /// match class of 'To'.
765 class TokenAlias<string From, string To> {
766 string FromToken = From;
770 /// MnemonicAlias - This class allows targets to define assembler mnemonic
771 /// aliases. This should be used when all forms of one mnemonic are accepted
772 /// with a different mnemonic. For example, X86 allows:
773 /// sal %al, 1 -> shl %al, 1
774 /// sal %ax, %cl -> shl %ax, %cl
775 /// sal %eax, %cl -> shl %eax, %cl
776 /// etc. Though "sal" is accepted with many forms, all of them are directly
777 /// translated to a shl, so it can be handled with (in the case of X86, it
778 /// actually has one for each suffix as well):
779 /// def : MnemonicAlias<"sal", "shl">;
781 /// Mnemonic aliases are mapped before any other translation in the match phase,
782 /// and do allow Requires predicates, e.g.:
784 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
785 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
787 class MnemonicAlias<string From, string To> {
788 string FromMnemonic = From;
789 string ToMnemonic = To;
791 // Predicates - Predicates that must be true for this remapping to happen.
792 list<Predicate> Predicates = [];
795 /// InstAlias - This defines an alternate assembly syntax that is allowed to
796 /// match an instruction that has a different (more canonical) assembly
798 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
799 string AsmString = Asm; // The .s format to match the instruction with.
800 dag ResultInst = Result; // The MCInst to generate.
801 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
803 // Predicates - Predicates that must be true for this to match.
804 list<Predicate> Predicates = [];
807 //===----------------------------------------------------------------------===//
808 // AsmWriter - This class can be implemented by targets that need to customize
809 // the format of the .s file writer.
811 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
812 // on X86 for example).
815 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
816 // class. Generated AsmWriter classes are always prefixed with the target
818 string AsmWriterClassName = "AsmPrinter";
820 // Variant - AsmWriters can be of multiple different variants. Variants are
821 // used to support targets that need to emit assembly code in ways that are
822 // mostly the same for different targets, but have minor differences in
823 // syntax. If the asmstring contains {|} characters in them, this integer
824 // will specify which alternative to use. For example "{x|y|z}" with Variant
825 // == 1, will expand to "y".
829 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
830 // layout, the asmwriter can actually generate output in this columns (in
831 // verbose-asm mode). These two values indicate the width of the first column
832 // (the "opcode" area) and the width to reserve for subsequent operands. When
833 // verbose asm mode is enabled, operands will be indented to respect this.
834 int FirstOperandColumn = -1;
836 // OperandSpacing - Space between operand columns.
837 int OperandSpacing = -1;
839 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
840 // generation of the printInstruction() method. For MC printers, it takes
841 // an MCInstr* operand, otherwise it takes a MachineInstr*.
842 bit isMCAsmWriter = 0;
844 def DefaultAsmWriter : AsmWriter;
847 //===----------------------------------------------------------------------===//
848 // Target - This class contains the "global" target information
851 // InstructionSet - Instruction set description for this target.
852 InstrInfo InstructionSet;
854 // AssemblyParsers - The AsmParser instances available for this target.
855 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
857 /// AssemblyParserVariants - The AsmParserVariant instances available for
859 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
861 // AssemblyWriters - The AsmWriter instances available for this target.
862 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
865 //===----------------------------------------------------------------------===//
866 // SubtargetFeature - A characteristic of the chip set.
868 class SubtargetFeature<string n, string a, string v, string d,
869 list<SubtargetFeature> i = []> {
870 // Name - Feature name. Used by command line (-mattr=) to determine the
871 // appropriate target chip.
875 // Attribute - Attribute to be set by feature.
877 string Attribute = a;
879 // Value - Value the attribute to be set to by feature.
883 // Desc - Feature description. Used by command line (-mattr=) to display help
888 // Implies - Features that this feature implies are present. If one of those
889 // features isn't set, then this one shouldn't be set either.
891 list<SubtargetFeature> Implies = i;
894 //===----------------------------------------------------------------------===//
895 // Processor chip sets - These values represent each of the chip sets supported
896 // by the scheduler. Each Processor definition requires corresponding
897 // instruction itineraries.
899 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
900 // Name - Chip set name. Used by command line (-mcpu=) to determine the
901 // appropriate target chip.
905 // ProcItin - The scheduling information for the target processor.
907 ProcessorItineraries ProcItin = pi;
909 // Features - list of
910 list<SubtargetFeature> Features = f;
913 //===----------------------------------------------------------------------===//
914 // Pull in the common support for calling conventions.
916 include "llvm/Target/TargetCallingConv.td"
918 //===----------------------------------------------------------------------===//
919 // Pull in the common support for DAG isel generation.
921 include "llvm/Target/TargetSelectionDAG.td"