1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // Register - You should define one instance of this class for each register
25 // in the target machine. String n will become the "name" of the register.
26 class Register<string n> {
27 string Namespace = "";
30 // SpillSize - If this value is set to a non-zero value, it is the size in
31 // bits of the spill slot required to hold this register. If this value is
32 // set to zero, the information is inferred from any register classes the
33 // register belongs to.
36 // SpillAlignment - This value is used to specify the alignment required for
37 // spilling the register. Like SpillSize, this should only be explicitly
38 // specified if the register is not in a register class.
39 int SpillAlignment = 0;
41 // Aliases - A list of registers that this register overlaps with. A read or
42 // modification of this register can potentially read or modify the aliased
44 list<Register> Aliases = [];
46 // SubRegs - A list of registers that are parts of this register. Note these
47 // are "immediate" sub-registers and the registers within the list do not
48 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
50 list<Register> SubRegs = [];
52 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
53 // These values can be determined by locating the <target>.h file in the
54 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
55 // order of these names correspond to the enumeration used by gcc. A value of
56 // -1 indicates that the gcc number is undefined and -2 that register number
57 // is invalid for this mode/flavour.
58 list<int> DwarfNumbers = [];
61 // RegisterWithSubRegs - This can be used to define instances of Register which
62 // need to specify sub-registers.
63 // List "subregs" specifies which registers are sub-registers to this one. This
64 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
65 // This allows the code generator to be careful not to put two values with
66 // overlapping live ranges into registers which alias.
67 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
68 let SubRegs = subregs;
71 // SubRegSet - This can be used to define a specific mapping of registers to
72 // indices, for use as named subregs of a particular physical register. Each
73 // register in 'subregs' becomes an addressable subregister at index 'n' of the
74 // corresponding register in 'regs'.
75 class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
78 list<Register> From = regs;
79 list<Register> To = subregs;
82 // RegisterClass - Now that all of the registers are defined, and aliases
83 // between registers are defined, specify which registers belong to which
84 // register classes. This also defines the default allocation order of
85 // registers by register allocators.
87 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
88 list<Register> regList> {
89 string Namespace = namespace;
91 // RegType - Specify the list ValueType of the registers in this register
92 // class. Note that all registers in a register class must have the same
93 // ValueTypes. This is a list because some targets permit storing different
94 // types in same register, for example vector values with 128-bit total size,
95 // but different count/size of items, like SSE on x86.
97 list<ValueType> RegTypes = regTypes;
99 // Size - Specify the spill size in bits of the registers. A default value of
100 // zero lets tablgen pick an appropriate size.
103 // Alignment - Specify the alignment required of the registers when they are
104 // stored or loaded to memory.
106 int Alignment = alignment;
108 // CopyCost - This value is used to specify the cost of copying a value
109 // between two registers in this register class. The default value is one
110 // meaning it takes a single instruction to perform the copying. A negative
111 // value means copying is extremely expensive or impossible.
114 // MemberList - Specify which registers are in this class. If the
115 // allocation_order_* method are not specified, this also defines the order of
116 // allocation used by the register allocator.
118 list<Register> MemberList = regList;
120 // SubClassList - Specify which register classes correspond to subregisters
121 // of this class. The order should be by subregister set index.
122 list<RegisterClass> SubRegClassList = [];
124 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
125 // code into a generated register class. The normal usage of this is to
126 // overload virtual methods.
127 code MethodProtos = [{}];
128 code MethodBodies = [{}];
132 //===----------------------------------------------------------------------===//
133 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
134 // to the register numbering used by gcc and gdb. These values are used by a
135 // debug information writer to describe where values may be located during
137 class DwarfRegNum<list<int> Numbers> {
138 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
139 // These values can be determined by locating the <target>.h file in the
140 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
141 // order of these names correspond to the enumeration used by gcc. A value of
142 // -1 indicates that the gcc number is undefined and -2 that register number is
143 // invalid for this mode/flavour.
144 list<int> DwarfNumbers = Numbers;
147 //===----------------------------------------------------------------------===//
148 // Pull in the common support for scheduling
150 include "llvm/Target/TargetSchedule.td"
152 class Predicate; // Forward def
154 //===----------------------------------------------------------------------===//
155 // Instruction set description - These classes correspond to the C++ classes in
156 // the Target/TargetInstrInfo.h file.
159 string Namespace = "";
161 dag OutOperandList; // An dag containing the MI def operand list.
162 dag InOperandList; // An dag containing the MI use operand list.
163 string AsmString = ""; // The .s format to print the instruction with.
165 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
166 // otherwise, uninitialized.
169 // The follow state will eventually be inferred automatically from the
170 // instruction pattern.
172 list<Register> Uses = []; // Default to using no non-operand registers
173 list<Register> Defs = []; // Default to modifying no non-operand registers
175 // Predicates - List of predicates which will be turned into isel matching
177 list<Predicate> Predicates = [];
182 // Added complexity passed onto matching pattern.
183 int AddedComplexity = 0;
185 // These bits capture information about the high-level semantics of the
187 bit isReturn = 0; // Is this instruction a return instruction?
188 bit isBranch = 0; // Is this instruction a branch instruction?
189 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
190 bit isBarrier = 0; // Can control flow fall through this instruction?
191 bit isCall = 0; // Is this instruction a call instruction?
192 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
193 bit mayLoad = 0; // Is it possible for this inst to read memory?
194 bit mayStore = 0; // Is it possible for this inst to write memory?
195 bit isTwoAddress = 0; // Is this a two address instruction?
196 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
197 bit isCommutable = 0; // Is this 3 operand instruction commutable?
198 bit isTerminator = 0; // Is this part of the terminator for a basic block?
199 bit isReMaterializable = 0; // Is this instruction re-materializable?
200 bit isPredicable = 0; // Is this instruction predicable?
201 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
202 bit usesCustomInserter = 0; // Pseudo instr needing special help.
203 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
204 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
205 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
206 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
207 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
209 // Side effect flags - When set, the flags have these meanings:
211 // hasSideEffects - The instruction has side effects that are not
212 // captured by any operands of the instruction or other flags.
214 // neverHasSideEffects - Set on an instruction with no pattern if it has no
216 bit hasSideEffects = 0;
217 bit neverHasSideEffects = 0;
219 // Is this instruction a "real" instruction (with a distinct machine
220 // encoding), or is it a pseudo instruction used for codegen modeling
222 bit isCodeGenOnly = 0;
224 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
226 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
228 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
229 /// be encoded into the output machineinstr.
230 string DisableEncoding = "";
232 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
233 bits<32> TSFlags = 0;
236 /// Predicates - These are extra conditionals which are turned into instruction
237 /// selector matching code. Currently each predicate is just a string.
238 class Predicate<string cond> {
239 string CondString = cond;
242 /// NoHonorSignDependentRounding - This predicate is true if support for
243 /// sign-dependent-rounding is not enabled.
244 def NoHonorSignDependentRounding
245 : Predicate<"!HonorSignDependentRoundingFPMath()">;
247 class Requires<list<Predicate> preds> {
248 list<Predicate> Predicates = preds;
251 /// ops definition - This is just a simple marker used to identify the operands
252 /// list for an instruction. outs and ins are identical both syntatically and
253 /// semantically, they are used to define def operands and use operands to
254 /// improve readibility. This should be used like this:
255 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
260 /// variable_ops definition - Mark this instruction as taking a variable number
265 /// PointerLikeRegClass - Values that are designed to have pointer width are
266 /// derived from this. TableGen treats the register class as having a symbolic
267 /// type that it doesn't know, and resolves the actual regclass to use by using
268 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
269 class PointerLikeRegClass<int Kind> {
270 int RegClassKind = Kind;
274 /// ptr_rc definition - Mark this operand as being a pointer value whose
275 /// register class is resolved dynamically via a callback to TargetInstrInfo.
276 /// FIXME: We should probably change this to a class which contain a list of
277 /// flags. But currently we have but one flag.
278 def ptr_rc : PointerLikeRegClass<0>;
280 /// unknown definition - Mark this operand as being of unknown type, causing
281 /// it to be resolved by inference in the context it is used.
284 /// AsmOperandClass - Representation for the kinds of operands which the target
285 /// specific parser can create and the assembly matcher may need to distinguish.
287 /// Operand classes are used to define the order in which instructions are
288 /// matched, to ensure that the instruction which gets matched for any
289 /// particular list of operands is deterministic.
291 /// The target specific parser must be able to classify a parsed operand into a
292 /// unique class which does not partially overlap with any other classes. It can
293 /// match a subset of some other class, in which case the super class field
294 /// should be defined.
295 class AsmOperandClass {
296 /// The name to use for this class, which should be usable as an enum value.
299 /// The super class of this operand.
300 AsmOperandClass SuperClass = ?;
302 /// The name of the method on the target specific operand to call to test
303 /// whether the operand is an instance of this class. If not set, this will
304 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
305 /// signature should be:
306 /// bool isFoo() const;
307 string PredicateMethod = ?;
309 /// The name of the method on the target specific operand to call to add the
310 /// target specific operand to an MCInst. If not set, this will default to
311 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
312 /// signature should be:
313 /// void addFooOperands(MCInst &Inst, unsigned N) const;
314 string RenderMethod = ?;
317 def ImmAsmOperand : AsmOperandClass {
321 /// Operand Types - These provide the built-in operand types that may be used
322 /// by a target. Targets can optionally provide their own operand types as
323 /// needed, though this should not be needed for RISC targets.
324 class Operand<ValueType ty> {
326 string PrintMethod = "printOperand";
327 string AsmOperandLowerMethod = ?;
328 dag MIOperandInfo = (ops);
330 // ParserMatchClass - The "match class" that operands of this type fit
331 // in. Match classes are used to define the order in which instructions are
332 // match, to ensure that which instructions gets matched is deterministic.
334 // The target specific parser must be able to classify an parsed operand
335 // into a unique class, which does not partially overlap with any other
336 // classes. It can match a subset of some other class, in which case
337 // ParserMatchSuperClass should be set to the name of that class.
338 AsmOperandClass ParserMatchClass = ImmAsmOperand;
341 def i1imm : Operand<i1>;
342 def i8imm : Operand<i8>;
343 def i16imm : Operand<i16>;
344 def i32imm : Operand<i32>;
345 def i64imm : Operand<i64>;
347 def f32imm : Operand<f32>;
348 def f64imm : Operand<f64>;
350 /// zero_reg definition - Special node to stand for the zero register.
354 /// PredicateOperand - This can be used to define a predicate operand for an
355 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
356 /// AlwaysVal specifies the value of this predicate when set to "always
358 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
360 let MIOperandInfo = OpTypes;
361 dag DefaultOps = AlwaysVal;
364 /// OptionalDefOperand - This is used to define a optional definition operand
365 /// for an instruction. DefaultOps is the register the operand represents if
366 /// none is supplied, e.g. zero_reg.
367 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
369 let MIOperandInfo = OpTypes;
370 dag DefaultOps = defaultops;
374 // InstrInfo - This class should only be instantiated once to provide parameters
375 // which are global to the target machine.
378 // Target can specify its instructions in either big or little-endian formats.
379 // For instance, while both Sparc and PowerPC are big-endian platforms, the
380 // Sparc manual specifies its instructions in the format [31..0] (big), while
381 // PowerPC specifies them using the format [0..31] (little).
382 bit isLittleEndianEncoding = 0;
385 // Standard Pseudo Instructions.
386 let isCodeGenOnly = 1 in {
387 def PHI : Instruction {
388 let OutOperandList = (outs);
389 let InOperandList = (ins variable_ops);
390 let AsmString = "PHINODE";
391 let Namespace = "TargetOpcode";
393 def INLINEASM : Instruction {
394 let OutOperandList = (outs);
395 let InOperandList = (ins variable_ops);
397 let Namespace = "TargetOpcode";
399 def DBG_LABEL : Instruction {
400 let OutOperandList = (outs);
401 let InOperandList = (ins i32imm:$id);
403 let Namespace = "TargetOpcode";
405 let isNotDuplicable = 1;
407 def EH_LABEL : Instruction {
408 let OutOperandList = (outs);
409 let InOperandList = (ins i32imm:$id);
411 let Namespace = "TargetOpcode";
413 let isNotDuplicable = 1;
415 def GC_LABEL : Instruction {
416 let OutOperandList = (outs);
417 let InOperandList = (ins i32imm:$id);
419 let Namespace = "TargetOpcode";
421 let isNotDuplicable = 1;
423 def KILL : Instruction {
424 let OutOperandList = (outs);
425 let InOperandList = (ins variable_ops);
427 let Namespace = "TargetOpcode";
428 let neverHasSideEffects = 1;
430 def EXTRACT_SUBREG : Instruction {
431 let OutOperandList = (outs unknown:$dst);
432 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
434 let Namespace = "TargetOpcode";
435 let neverHasSideEffects = 1;
437 def INSERT_SUBREG : Instruction {
438 let OutOperandList = (outs unknown:$dst);
439 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
441 let Namespace = "TargetOpcode";
442 let neverHasSideEffects = 1;
443 let Constraints = "$supersrc = $dst";
445 def IMPLICIT_DEF : Instruction {
446 let OutOperandList = (outs unknown:$dst);
447 let InOperandList = (ins);
449 let Namespace = "TargetOpcode";
450 let neverHasSideEffects = 1;
451 let isReMaterializable = 1;
452 let isAsCheapAsAMove = 1;
454 def SUBREG_TO_REG : Instruction {
455 let OutOperandList = (outs unknown:$dst);
456 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
458 let Namespace = "TargetOpcode";
459 let neverHasSideEffects = 1;
461 def COPY_TO_REGCLASS : Instruction {
462 let OutOperandList = (outs unknown:$dst);
463 let InOperandList = (ins unknown:$src, i32imm:$regclass);
465 let Namespace = "TargetOpcode";
466 let neverHasSideEffects = 1;
467 let isAsCheapAsAMove = 1;
469 def DBG_VALUE : Instruction {
470 let OutOperandList = (outs);
471 let InOperandList = (ins variable_ops);
472 let AsmString = "DBG_VALUE";
473 let Namespace = "TargetOpcode";
474 let isAsCheapAsAMove = 1;
477 def REG_SEQUENCE : Instruction {
478 let OutOperandList = (outs unknown:$dst);
479 let InOperandList = (ins variable_ops);
481 let Namespace = "TargetOpcode";
482 let neverHasSideEffects = 1;
483 let isAsCheapAsAMove = 1;
487 //===----------------------------------------------------------------------===//
488 // AsmParser - This class can be implemented by targets that wish to implement
491 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
492 // syntax on X86 for example).
495 // AsmParserClassName - This specifies the suffix to use for the asmparser
496 // class. Generated AsmParser classes are always prefixed with the target
498 string AsmParserClassName = "AsmParser";
500 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the
501 // AsmParser class to call on every matched instruction. This can be used to
502 // perform target specific instruction post-processing.
503 string AsmParserInstCleanup = "";
505 // MatchInstructionName - The name of the instruction matching function to
507 string MatchInstructionName = "MatchInstruction";
509 // Variant - AsmParsers can be of multiple different variants. Variants are
510 // used to support targets that need to parser multiple formats for the
511 // assembly language.
514 // CommentDelimiter - If given, the delimiter string used to recognize
515 // comments which are hard coded in the .td assembler strings for individual
517 string CommentDelimiter = "";
519 // RegisterPrefix - If given, the token prefix which indicates a register
520 // token. This is used by the matcher to automatically recognize hard coded
521 // register tokens as constrained registers, instead of tokens, for the
522 // purposes of matching.
523 string RegisterPrefix = "";
525 def DefaultAsmParser : AsmParser;
528 //===----------------------------------------------------------------------===//
529 // AsmWriter - This class can be implemented by targets that need to customize
530 // the format of the .s file writer.
532 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
533 // on X86 for example).
536 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
537 // class. Generated AsmWriter classes are always prefixed with the target
539 string AsmWriterClassName = "AsmPrinter";
541 // InstFormatName - AsmWriters can specify the name of the format string to
542 // print instructions with.
543 string InstFormatName = "AsmString";
545 // Variant - AsmWriters can be of multiple different variants. Variants are
546 // used to support targets that need to emit assembly code in ways that are
547 // mostly the same for different targets, but have minor differences in
548 // syntax. If the asmstring contains {|} characters in them, this integer
549 // will specify which alternative to use. For example "{x|y|z}" with Variant
550 // == 1, will expand to "y".
554 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
555 // layout, the asmwriter can actually generate output in this columns (in
556 // verbose-asm mode). These two values indicate the width of the first column
557 // (the "opcode" area) and the width to reserve for subsequent operands. When
558 // verbose asm mode is enabled, operands will be indented to respect this.
559 int FirstOperandColumn = -1;
561 // OperandSpacing - Space between operand columns.
562 int OperandSpacing = -1;
564 def DefaultAsmWriter : AsmWriter;
567 //===----------------------------------------------------------------------===//
568 // Target - This class contains the "global" target information
571 // InstructionSet - Instruction set description for this target.
572 InstrInfo InstructionSet;
574 // AssemblyParsers - The AsmParser instances available for this target.
575 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
577 // AssemblyWriters - The AsmWriter instances available for this target.
578 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
581 //===----------------------------------------------------------------------===//
582 // SubtargetFeature - A characteristic of the chip set.
584 class SubtargetFeature<string n, string a, string v, string d,
585 list<SubtargetFeature> i = []> {
586 // Name - Feature name. Used by command line (-mattr=) to determine the
587 // appropriate target chip.
591 // Attribute - Attribute to be set by feature.
593 string Attribute = a;
595 // Value - Value the attribute to be set to by feature.
599 // Desc - Feature description. Used by command line (-mattr=) to display help
604 // Implies - Features that this feature implies are present. If one of those
605 // features isn't set, then this one shouldn't be set either.
607 list<SubtargetFeature> Implies = i;
610 //===----------------------------------------------------------------------===//
611 // Processor chip sets - These values represent each of the chip sets supported
612 // by the scheduler. Each Processor definition requires corresponding
613 // instruction itineraries.
615 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
616 // Name - Chip set name. Used by command line (-mcpu=) to determine the
617 // appropriate target chip.
621 // ProcItin - The scheduling information for the target processor.
623 ProcessorItineraries ProcItin = pi;
625 // Features - list of
626 list<SubtargetFeature> Features = f;
629 //===----------------------------------------------------------------------===//
630 // Pull in the common support for calling conventions.
632 include "llvm/Target/TargetCallingConv.td"
634 //===----------------------------------------------------------------------===//
635 // Pull in the common support for DAG isel generation.
637 include "llvm/Target/TargetSelectionDAG.td"