1 //===-- llvm/Target/MachineCacheInfo.h --------------------------*- C++ -*-===//
3 // Describes properties of the target cache architecture.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINECACHEINFO_H
8 #define LLVM_TARGET_MACHINECACHEINFO_H
10 #include "Support/DataTypes.h"
13 struct MachineCacheInfo : public NonCopyableV {
14 const TargetMachine ⌖
16 unsigned int numLevels;
17 std::vector<unsigned short> cacheLineSizes;
18 std::vector<unsigned int> cacheSizes;
19 std::vector<unsigned short> cacheAssoc;
22 MachineCacheInfo(const TargetMachine& tgt) : target(tgt) {
26 // Default parameters are:
28 // L1: LineSize 16, Cache Size 32KB, Direct-mapped (assoc = 1)
29 // L2: LineSize 32, Cache Size 1 MB, 4-way associative
30 // NOTE: Cache levels are numbered from 1 as above, not from 0.
32 virtual void Initialize (); // subclass to override defaults
34 unsigned int getNumCacheLevels () const {
37 unsigned short getCacheLineSize (unsigned level) const {
38 assert(level <= cacheLineSizes.size() && "Invalid cache level");
39 return cacheLineSizes[level-1];
41 unsigned int getCacheSize (unsigned level) const {
42 assert(level <= cacheSizes.size() && "Invalid cache level");
43 return cacheSizes[level-1];
45 unsigned short getCacheAssoc (unsigned level) const {
46 assert(level <= cacheAssoc.size() && "Invalid cache level");
47 return cacheAssoc[level];