2 //***************************************************************************
7 // Describes properties of the target cache architecture.
8 //**************************************************************************/
10 #ifndef LLVM_TARGET_MACHINECACHEINFO_H
11 #define LLVM_TARGET_MACHINECACHEINFO_H
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/Support/DataTypes.h"
18 //---------------------------------------------------------------------------
19 // class MachineCacheInfo
22 // Describes properties of the target cache architecture.
23 //---------------------------------------------------------------------------
25 class MachineCacheInfo : public NonCopyableV {
27 const TargetMachine& target;
30 unsigned int numLevels;
31 vector<unsigned short> cacheLineSizes;
32 vector<unsigned int> cacheSizes;
33 vector<unsigned short> cacheAssoc;
36 /*ctor*/ MachineCacheInfo (const TargetMachine& tgt);
37 /*dtor*/ virtual ~MachineCacheInfo () {}
39 // Default parameters are:
41 // L1: LineSize 16, Cache Size 32KB, Direct-mapped (assoc = 1)
42 // L2: LineSize 32, Cache Size 1 MB, 4-way associative
43 // NOTE: Cache levels are numbered from 1 as above, not from 0.
45 virtual void Initialize (); // subclass to override defaults
47 unsigned int getNumCacheLevels () const {
50 unsigned short getCacheLineSize (unsigned level) const {
51 assert(level <= cacheLineSizes.size() && "Invalid cache level");
52 return cacheLineSizes[level-1];
54 unsigned int getCacheSize (unsigned level) const {
55 assert(level <= cacheSizes.size() && "Invalid cache level");
56 return cacheSizes[level-1];
58 unsigned short getCacheAssoc (unsigned level) const {
59 assert(level <= cacheAssoc.size() && "Invalid cache level");
60 return cacheAssoc[level];
65 //---------------------------------------------------------------------------