1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints: only "tied_to" for now.
28 enum OperandConstraint {
29 TIED_TO = 0 // Must be allocated the same register as.
32 /// OperandFlags - These are flags set on operands, but should be considered
33 /// private, all access should go through the TargetOperandInfo accessors.
34 /// See the accessors for a description of what these are.
36 LookupPtrRegClass = 0,
42 /// TargetOperandInfo - This holds information about one operand of a machine
43 /// instruction, indicating the register class for register operands, etc.
45 class TargetOperandInfo {
47 /// RegClass - This specifies the register class enumeration of the operand
48 /// if the operand is a register. If not, this contains 0.
49 unsigned short RegClass;
51 /// Lower 16 bits are used to specify which constraints are set. The higher 16
52 /// bits are used to specify the value of constraints (4 bits each).
53 unsigned int Constraints;
54 /// Currently no other information.
56 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
57 /// requires a callback to look up its register class.
58 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
60 /// isPredicate - Set if this is one of the operands that made up of
61 /// the predicate operand that controls an isPredicable() instruction.
62 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
64 /// isOptionalDef - Set if this operand is a optional def.
66 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
70 //===----------------------------------------------------------------------===//
71 // Machine Instruction Flags and Description
72 //===----------------------------------------------------------------------===//
74 /// TargetInstrDesc flags - These should be considered private to the
75 /// implementation of the TargetInstrDesc class. Clients should use the
76 /// predicate methods on TargetInstrDesc, not use these directly. These
77 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
97 UsesCustomDAGSchedInserter,
102 /// TargetInstrDesc - Describe properties that are true of each
103 /// instruction in the target description file. This captures information about
104 /// side effects, register use and many other things. There is one instance of
105 /// this struct for each target instruction class, and the MachineInstr class
106 /// points to this struct directly to describe itself.
107 class TargetInstrDesc {
109 unsigned short Opcode; // The opcode number.
110 unsigned short NumOperands; // Num of args (may be more if variable_ops)
111 unsigned short NumDefs; // Num of args that are definitions.
112 unsigned short SchedClass; // enum identifying instr sched class
113 const char * Name; // Name of the instruction record in td file.
114 unsigned Flags; // flags identifying machine instr class
115 unsigned TSFlags; // Target Specific Flag values
116 const unsigned *ImplicitUses; // Registers implicitly read by this instr
117 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
118 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands.
120 /// getOperandConstraint - Returns the value of the specific constraint if
121 /// it is set. Returns -1 if it is not set.
122 int getOperandConstraint(unsigned OpNum,
123 TOI::OperandConstraint Constraint) const {
124 if (OpNum < NumOperands &&
125 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
126 unsigned Pos = 16 + Constraint * 4;
127 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
132 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
133 /// dest operand. Returns -1 if there isn't one.
134 int findTiedToSrcOperand(unsigned OpNum) const;
136 /// getOpcode - Return the opcode number for this descriptor.
137 unsigned getOpcode() const {
141 /// getName - Return the name of the record in the .td file for this
142 /// instruction, for example "ADD8ri".
143 const char *getName() const {
147 /// getNumOperands - Return the number of declared MachineOperands for this
148 /// MachineInstruction. Note that variadic (isVariadic() returns true)
149 /// instructions may have additional operands at the end of the list, and note
150 /// that the machine instruction may include implicit register def/uses as
152 unsigned getNumOperands() const {
156 /// getNumDefs - Return the number of MachineOperands that are register
157 /// definitions. Register definitions always occur at the start of the
158 /// machine operand list. This is the number of "outs" in the .td file.
159 unsigned getNumDefs() const {
163 /// isVariadic - Return true if this instruction can have a variable number of
164 /// operands. In this case, the variable operands will be after the normal
165 /// operands but before the implicit definitions and uses (if any are
167 bool isVariadic() const {
168 return Flags & (1 << TID::Variadic);
171 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
172 /// ARM instructions which can set condition code if 's' bit is set.
173 bool hasOptionalDef() const {
174 return Flags & (1 << TID::HasOptionalDef);
177 /// getImplicitUses - Return a list of machine operands that are potentially
178 /// read by any instance of this machine instruction. For example, on X86,
179 /// the "adc" instruction adds two register operands and adds the carry bit in
180 /// from the flags register. In this case, the instruction is marked as
181 /// implicitly reading the flags. Likewise, the variable shift instruction on
182 /// X86 is marked as implicitly reading the 'CL' register, which it always
185 /// This method returns null if the instruction has no implicit uses.
186 const unsigned *getImplicitUses() const {
190 /// getImplicitDefs - Return a list of machine operands that are potentially
191 /// written by any instance of this machine instruction. For example, on X86,
192 /// many instructions implicitly set the flags register. In this case, they
193 /// are marked as setting the FLAGS. Likewise, many instructions always
194 /// deposit their result in a physical register. For example, the X86 divide
195 /// instruction always deposits the quotient and remainder in the EAX/EDX
196 /// registers. For that instruction, this will return a list containing the
197 /// EAX/EDX/EFLAGS registers.
199 /// This method returns null if the instruction has no implicit uses.
200 const unsigned *getImplicitDefs() const {
204 /// getSchedClass - Return the scheduling class for this instruction. The
205 /// scheduling class is an index into the InstrItineraryData table. This
206 /// returns zero if there is no known scheduling information for the
209 unsigned getSchedClass() const {
213 bool isReturn() const {
214 return Flags & (1 << TID::Return);
217 bool isCall() const {
218 return Flags & (1 << TID::Call);
221 /// isBarrier - Returns true if the specified instruction stops control flow
222 /// from executing the instruction immediately following it. Examples include
223 /// unconditional branches and return instructions.
224 bool isBarrier() const {
225 return Flags & (1 << TID::Barrier);
228 /// isTerminator - Returns true if this instruction part of the terminator for
229 /// a basic block. Typically this is things like return and branch
232 /// Various passes use this to insert code into the bottom of a basic block,
233 /// but before control flow occurs.
234 bool isTerminator() const {
235 return Flags & (1 << TID::Terminator);
238 /// isBranch - Returns true if this is a conditional, unconditional, or
239 /// indirect branch. Predicates below can be used to discriminate between
240 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
241 /// get more information.
242 bool isBranch() const {
243 return Flags & (1 << TID::Branch);
246 /// isIndirectBranch - Return true if this is an indirect branch, such as a
247 /// branch through a register.
248 bool isIndirectBranch() const {
249 return Flags & (1 << TID::IndirectBranch);
252 /// isConditionalBranch - Return true if this is a branch which may fall
253 /// through to the next instruction or may transfer control flow to some other
254 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
255 /// information about this branch.
256 bool isConditionalBranch() const {
257 return isBranch() & !isBarrier() & !isIndirectBranch();
260 /// isUnconditionalBranch - Return true if this is a branch which always
261 /// transfers control flow to some other block. The
262 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
263 /// about this branch.
264 bool isUnconditionalBranch() const {
265 return isBranch() & isBarrier() & !isIndirectBranch();
268 // isPredicable - Return true if this instruction has a predicate operand that
269 // controls execution. It may be set to 'always', or may be set to other
270 /// values. There are various methods in TargetInstrInfo that can be used to
271 /// control and modify the predicate in this instruction.
272 bool isPredicable() const {
273 return Flags & (1 << TID::Predicable);
276 /// isNotDuplicable - Return true if this instruction cannot be safely
277 /// duplicated. For example, if the instruction has a unique labels attached
278 /// to it, duplicating it would cause multiple definition errors.
279 bool isNotDuplicable() const {
280 return Flags & (1 << TID::NotDuplicable);
283 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
284 /// which must be filled by the code generator.
285 bool hasDelaySlot() const {
286 return Flags & (1 << TID::DelaySlot);
289 /// isSimpleLoad - Return true for instructions that are simple loads from
290 /// memory. This should only be set on instructions that load a value from
291 /// memory and return it in their only virtual register definition.
292 /// Instructions that return a value loaded from memory and then modified in
293 /// some way should not return true for this.
294 bool isSimpleLoad() const {
295 return Flags & (1 << TID::SimpleLoad);
298 //===--------------------------------------------------------------------===//
299 // Side Effect Analysis
300 //===--------------------------------------------------------------------===//
302 /// mayLoad - Return true if this instruction could possibly read memory.
303 /// Instructions with this flag set are not necessarily simple load
304 /// instructions, they may load a value and modify it, for example.
305 bool mayLoad() const {
306 return Flags & (1 << TID::MayLoad);
310 /// mayStore - Return true if this instruction could possibly modify memory.
311 /// Instructions with this flag set are not necessarily simple store
312 /// instructions, they may store a modified value based on their operands, or
313 /// may not actually modify anything, for example.
314 bool mayStore() const {
315 return Flags & (1 << TID::MayStore);
318 /// hasUnmodeledSideEffects - Return true if this instruction has side
319 /// effects that are not modeled by other flags. This does not return true
320 /// for instructions whose effects are captured by:
322 /// 1. Their operand list and implicit definition/use list. Register use/def
323 /// info is explicit for instructions.
324 /// 2. Memory accesses. Use mayLoad/mayStore.
325 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
327 /// Examples of side effects would be modifying 'invisible' machine state like
328 /// a control register, flushing a cache, modifying a register invisible to
331 bool hasUnmodeledSideEffects() const {
332 return Flags & (1 << TID::UnmodeledSideEffects);
335 //===--------------------------------------------------------------------===//
336 // Flags that indicate whether an instruction can be modified by a method.
337 //===--------------------------------------------------------------------===//
339 /// isCommutable - Return true if this may be a 2- or 3-address
340 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
341 /// result if Y and Z are exchanged. If this flag is set, then the
342 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
345 /// Note that this flag may be set on instructions that are only commutable
346 /// sometimes. In these cases, the call to commuteInstruction will fail.
347 /// Also note that some instructions require non-trivial modification to
349 bool isCommutable() const {
350 return Flags & (1 << TID::Commutable);
353 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
354 /// which can be changed into a 3-address instruction if needed. Doing this
355 /// transformation can be profitable in the register allocator, because it
356 /// means that the instruction can use a 2-address form if possible, but
357 /// degrade into a less efficient form if the source and dest register cannot
358 /// be assigned to the same register. For example, this allows the x86
359 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
360 /// is the same speed as the shift but has bigger code size.
362 /// If this returns true, then the target must implement the
363 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
364 /// is allowed to fail if the transformation isn't valid for this specific
365 /// instruction (e.g. shl reg, 4 on x86).
367 bool isConvertibleTo3Addr() const {
368 return Flags & (1 << TID::ConvertibleTo3Addr);
371 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
372 /// custom insertion support when the DAG scheduler is inserting it into a
373 /// machine basic block. If this is true for the instruction, it basically
374 /// means that it is a pseudo instruction used at SelectionDAG time that is
375 /// expanded out into magic code by the target when MachineInstrs are formed.
377 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
378 /// is used to insert this into the MachineBasicBlock.
379 bool usesCustomDAGSchedInsertionHook() const {
380 return Flags & (1 << TID::UsesCustomDAGSchedInserter);
383 /// isRematerializable - Returns true if this instruction is a candidate for
384 /// remat. This flag is deprecated, please don't use it anymore. If this
385 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
386 /// verify the instruction is really rematable.
387 bool isRematerializable() const {
388 return Flags & (1 << TID::Rematerializable);
392 } // end namespace llvm