1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
20 class TargetRegisterClass;
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints: only "tied_to" for now.
28 enum OperandConstraint {
29 TIED_TO = 0 // Must be allocated the same register as.
32 /// OperandFlags - These are flags set on operands, but should be considered
33 /// private, all access should go through the TargetOperandInfo accessors.
34 /// See the accessors for a description of what these are.
36 LookupPtrRegClass = 0,
42 /// TargetOperandInfo - This holds information about one operand of a machine
43 /// instruction, indicating the register class for register operands, etc.
45 class TargetOperandInfo {
47 /// RegClass - This specifies the register class enumeration of the operand
48 /// if the operand is a register. If not, this contains 0.
49 unsigned short RegClass;
51 /// Lower 16 bits are used to specify which constraints are set. The higher 16
52 /// bits are used to specify the value of constraints (4 bits each).
53 unsigned int Constraints;
54 /// Currently no other information.
56 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
57 /// requires a callback to look up its register class.
58 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
60 /// isPredicate - Set if this is one of the operands that made up of
61 /// the predicate operand that controls an isPredicable() instruction.
62 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
64 /// isOptionalDef - Set if this operand is a optional def.
66 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
70 //===----------------------------------------------------------------------===//
71 // Machine Instruction Flags and Description
72 //===----------------------------------------------------------------------===//
74 /// TargetInstrDesc flags - These should be considered private to the
75 /// implementation of the TargetInstrDesc class. Clients should use the
76 /// predicate methods on TargetInstrDesc, not use these directly. These
77 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
97 UsesCustomDAGSchedInserter,
103 /// TargetInstrDesc - Describe properties that are true of each
104 /// instruction in the target description file. This captures information about
105 /// side effects, register use and many other things. There is one instance of
106 /// this struct for each target instruction class, and the MachineInstr class
107 /// points to this struct directly to describe itself.
108 class TargetInstrDesc {
110 unsigned short Opcode; // The opcode number
111 unsigned short NumOperands; // Num of args (may be more if variable_ops)
112 unsigned short NumDefs; // Num of args that are definitions
113 unsigned short SchedClass; // enum identifying instr sched class
114 const char * Name; // Name of the instruction record in td file
115 unsigned Flags; // Flags identifying machine instr class
116 unsigned TSFlags; // Target Specific Flag values
117 const unsigned *ImplicitUses; // Registers implicitly read by this instr
118 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
119 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
120 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
122 /// getOperandConstraint - Returns the value of the specific constraint if
123 /// it is set. Returns -1 if it is not set.
124 int getOperandConstraint(unsigned OpNum,
125 TOI::OperandConstraint Constraint) const {
126 if (OpNum < NumOperands &&
127 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
128 unsigned Pos = 16 + Constraint * 4;
129 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
134 /// getOpcode - Return the opcode number for this descriptor.
135 unsigned getOpcode() const {
139 /// getName - Return the name of the record in the .td file for this
140 /// instruction, for example "ADD8ri".
141 const char *getName() const {
145 /// getNumOperands - Return the number of declared MachineOperands for this
146 /// MachineInstruction. Note that variadic (isVariadic() returns true)
147 /// instructions may have additional operands at the end of the list, and note
148 /// that the machine instruction may include implicit register def/uses as
150 unsigned getNumOperands() const {
154 /// getNumDefs - Return the number of MachineOperands that are register
155 /// definitions. Register definitions always occur at the start of the
156 /// machine operand list. This is the number of "outs" in the .td file,
157 /// and does not include implicit defs.
158 unsigned getNumDefs() const {
162 /// isVariadic - Return true if this instruction can have a variable number of
163 /// operands. In this case, the variable operands will be after the normal
164 /// operands but before the implicit definitions and uses (if any are
166 bool isVariadic() const {
167 return Flags & (1 << TID::Variadic);
170 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
171 /// ARM instructions which can set condition code if 's' bit is set.
172 bool hasOptionalDef() const {
173 return Flags & (1 << TID::HasOptionalDef);
176 /// getImplicitUses - Return a list of registers that are potentially
177 /// read by any instance of this machine instruction. For example, on X86,
178 /// the "adc" instruction adds two register operands and adds the carry bit in
179 /// from the flags register. In this case, the instruction is marked as
180 /// implicitly reading the flags. Likewise, the variable shift instruction on
181 /// X86 is marked as implicitly reading the 'CL' register, which it always
184 /// This method returns null if the instruction has no implicit uses.
185 const unsigned *getImplicitUses() const {
189 /// getImplicitDefs - Return a list of registers that are potentially
190 /// written by any instance of this machine instruction. For example, on X86,
191 /// many instructions implicitly set the flags register. In this case, they
192 /// are marked as setting the FLAGS. Likewise, many instructions always
193 /// deposit their result in a physical register. For example, the X86 divide
194 /// instruction always deposits the quotient and remainder in the EAX/EDX
195 /// registers. For that instruction, this will return a list containing the
196 /// EAX/EDX/EFLAGS registers.
198 /// This method returns null if the instruction has no implicit defs.
199 const unsigned *getImplicitDefs() const {
203 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
204 /// uses the specified physical register.
205 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
206 if (const unsigned *ImpUses = ImplicitUses)
207 for (; *ImpUses; ++ImpUses)
208 if (*ImpUses == Reg) return true;
212 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
213 /// defines the specified physical register.
214 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
215 if (const unsigned *ImpDefs = ImplicitDefs)
216 for (; *ImpDefs; ++ImpDefs)
217 if (*ImpDefs == Reg) return true;
221 /// getRegClassBarriers - Return a list of register classes that are
222 /// completely clobbered by this machine instruction. For example, on X86
223 /// the call instructions will completely clobber all the registers in the
224 /// fp stack and XMM classes.
226 /// This method returns null if the instruction doesn't completely clobber
227 /// any register class.
228 const TargetRegisterClass **getRegClassBarriers() const {
232 /// getSchedClass - Return the scheduling class for this instruction. The
233 /// scheduling class is an index into the InstrItineraryData table. This
234 /// returns zero if there is no known scheduling information for the
237 unsigned getSchedClass() const {
241 bool isReturn() const {
242 return Flags & (1 << TID::Return);
245 bool isCall() const {
246 return Flags & (1 << TID::Call);
249 /// isBarrier - Returns true if the specified instruction stops control flow
250 /// from executing the instruction immediately following it. Examples include
251 /// unconditional branches and return instructions.
252 bool isBarrier() const {
253 return Flags & (1 << TID::Barrier);
256 /// isTerminator - Returns true if this instruction part of the terminator for
257 /// a basic block. Typically this is things like return and branch
260 /// Various passes use this to insert code into the bottom of a basic block,
261 /// but before control flow occurs.
262 bool isTerminator() const {
263 return Flags & (1 << TID::Terminator);
266 /// isBranch - Returns true if this is a conditional, unconditional, or
267 /// indirect branch. Predicates below can be used to discriminate between
268 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
269 /// get more information.
270 bool isBranch() const {
271 return Flags & (1 << TID::Branch);
274 /// isIndirectBranch - Return true if this is an indirect branch, such as a
275 /// branch through a register.
276 bool isIndirectBranch() const {
277 return Flags & (1 << TID::IndirectBranch);
280 /// isConditionalBranch - Return true if this is a branch which may fall
281 /// through to the next instruction or may transfer control flow to some other
282 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
283 /// information about this branch.
284 bool isConditionalBranch() const {
285 return isBranch() & !isBarrier() & !isIndirectBranch();
288 /// isUnconditionalBranch - Return true if this is a branch which always
289 /// transfers control flow to some other block. The
290 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
291 /// about this branch.
292 bool isUnconditionalBranch() const {
293 return isBranch() & isBarrier() & !isIndirectBranch();
296 // isPredicable - Return true if this instruction has a predicate operand that
297 // controls execution. It may be set to 'always', or may be set to other
298 /// values. There are various methods in TargetInstrInfo that can be used to
299 /// control and modify the predicate in this instruction.
300 bool isPredicable() const {
301 return Flags & (1 << TID::Predicable);
304 /// isNotDuplicable - Return true if this instruction cannot be safely
305 /// duplicated. For example, if the instruction has a unique labels attached
306 /// to it, duplicating it would cause multiple definition errors.
307 bool isNotDuplicable() const {
308 return Flags & (1 << TID::NotDuplicable);
311 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
312 /// which must be filled by the code generator.
313 bool hasDelaySlot() const {
314 return Flags & (1 << TID::DelaySlot);
317 /// canFoldAsLoad - Return true for instructions that can be folded as
318 /// memory operands in other instructions. The most common use for this
319 /// is instructions that are simple loads from memory that don't modify
320 /// the loaded value in any way, but it can also be used for instructions
321 /// that can be expressed as constant-pool loads, such as V_SETALLONES
322 /// on x86, to allow them to be folded when it is beneficial.
323 /// This should only be set on instructions that return a value in their
324 /// only virtual register definition.
325 bool canFoldAsLoad() const {
326 return Flags & (1 << TID::FoldableAsLoad);
329 //===--------------------------------------------------------------------===//
330 // Side Effect Analysis
331 //===--------------------------------------------------------------------===//
333 /// mayLoad - Return true if this instruction could possibly read memory.
334 /// Instructions with this flag set are not necessarily simple load
335 /// instructions, they may load a value and modify it, for example.
336 bool mayLoad() const {
337 return Flags & (1 << TID::MayLoad);
341 /// mayStore - Return true if this instruction could possibly modify memory.
342 /// Instructions with this flag set are not necessarily simple store
343 /// instructions, they may store a modified value based on their operands, or
344 /// may not actually modify anything, for example.
345 bool mayStore() const {
346 return Flags & (1 << TID::MayStore);
349 /// hasUnmodeledSideEffects - Return true if this instruction has side
350 /// effects that are not modeled by other flags. This does not return true
351 /// for instructions whose effects are captured by:
353 /// 1. Their operand list and implicit definition/use list. Register use/def
354 /// info is explicit for instructions.
355 /// 2. Memory accesses. Use mayLoad/mayStore.
356 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
358 /// Examples of side effects would be modifying 'invisible' machine state like
359 /// a control register, flushing a cache, modifying a register invisible to
362 bool hasUnmodeledSideEffects() const {
363 return Flags & (1 << TID::UnmodeledSideEffects);
366 //===--------------------------------------------------------------------===//
367 // Flags that indicate whether an instruction can be modified by a method.
368 //===--------------------------------------------------------------------===//
370 /// isCommutable - Return true if this may be a 2- or 3-address
371 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
372 /// result if Y and Z are exchanged. If this flag is set, then the
373 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
376 /// Note that this flag may be set on instructions that are only commutable
377 /// sometimes. In these cases, the call to commuteInstruction will fail.
378 /// Also note that some instructions require non-trivial modification to
380 bool isCommutable() const {
381 return Flags & (1 << TID::Commutable);
384 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
385 /// which can be changed into a 3-address instruction if needed. Doing this
386 /// transformation can be profitable in the register allocator, because it
387 /// means that the instruction can use a 2-address form if possible, but
388 /// degrade into a less efficient form if the source and dest register cannot
389 /// be assigned to the same register. For example, this allows the x86
390 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
391 /// is the same speed as the shift but has bigger code size.
393 /// If this returns true, then the target must implement the
394 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
395 /// is allowed to fail if the transformation isn't valid for this specific
396 /// instruction (e.g. shl reg, 4 on x86).
398 bool isConvertibleTo3Addr() const {
399 return Flags & (1 << TID::ConvertibleTo3Addr);
402 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
403 /// custom insertion support when the DAG scheduler is inserting it into a
404 /// machine basic block. If this is true for the instruction, it basically
405 /// means that it is a pseudo instruction used at SelectionDAG time that is
406 /// expanded out into magic code by the target when MachineInstrs are formed.
408 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
409 /// is used to insert this into the MachineBasicBlock.
410 bool usesCustomDAGSchedInsertionHook() const {
411 return Flags & (1 << TID::UsesCustomDAGSchedInserter);
414 /// isRematerializable - Returns true if this instruction is a candidate for
415 /// remat. This flag is deprecated, please don't use it anymore. If this
416 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
417 /// verify the instruction is really rematable.
418 bool isRematerializable() const {
419 return Flags & (1 << TID::Rematerializable);
422 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
423 /// less) than a move instruction. This is useful during certain types of
424 /// optimizations (e.g., remat during two-address conversion or machine licm)
425 /// where we would like to remat or hoist the instruction, but not if it costs
426 /// more than moving the instruction into the appropriate register. Note, we
427 /// are not marking copies from and to the same register class with this flag.
428 bool isAsCheapAsAMove() const {
429 return Flags & (1 << TID::CheapAsAMove);
433 } // end namespace llvm