1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
18 #include "llvm/Support/DataTypes.h"
22 class TargetRegisterClass;
23 class TargetRegisterInfo;
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// OperandFlags - These are flags set on operands, but should be considered
37 /// private, all access should go through the TargetOperandInfo accessors.
38 /// See the accessors for a description of what these are.
40 LookupPtrRegClass = 0,
46 /// TargetOperandInfo - This holds information about one operand of a machine
47 /// instruction, indicating the register class for register operands, etc.
49 class TargetOperandInfo {
51 /// RegClass - This specifies the register class enumeration of the operand
52 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
53 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
54 /// get a dynamic register class.
56 /// NOTE: This member should be considered to be private, all access should go
57 /// through "getRegClass(TRI)" below.
60 /// Flags - These are flags from the TOI::OperandFlags enum.
63 /// Lower 16 bits are used to specify which constraints are set. The higher 16
64 /// bits are used to specify the value of constraints (4 bits each).
66 /// Currently no other information.
68 /// getRegClass - Get the register class for the operand, handling resolution
69 /// of "symbolic" pointer register classes etc. If this is not a register
70 /// operand, this returns null.
71 const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const;
74 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75 /// requires a callback to look up its register class.
76 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
78 /// isPredicate - Set if this is one of the operands that made up of
79 /// the predicate operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
82 /// isOptionalDef - Set if this operand is a optional def.
84 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
88 //===----------------------------------------------------------------------===//
89 // Machine Instruction Flags and Description
90 //===----------------------------------------------------------------------===//
92 /// TargetInstrDesc flags - These should be considered private to the
93 /// implementation of the TargetInstrDesc class. Clients should use the
94 /// predicate methods on TargetInstrDesc, not use these directly. These
95 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
114 UnmodeledSideEffects,
125 /// TargetInstrDesc - Describe properties that are true of each
126 /// instruction in the target description file. This captures information about
127 /// side effects, register use and many other things. There is one instance of
128 /// this struct for each target instruction class, and the MachineInstr class
129 /// points to this struct directly to describe itself.
130 class TargetInstrDesc {
132 unsigned short Opcode; // The opcode number
133 unsigned short NumOperands; // Num of args (may be more if variable_ops)
134 unsigned short NumDefs; // Num of args that are definitions
135 unsigned short SchedClass; // enum identifying instr sched class
136 const char * Name; // Name of the instruction record in td file
137 unsigned Flags; // Flags identifying machine instr class
138 uint64_t TSFlags; // Target Specific Flag values
139 const unsigned *ImplicitUses; // Registers implicitly read by this instr
140 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
141 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
142 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
144 /// getOperandConstraint - Returns the value of the specific constraint if
145 /// it is set. Returns -1 if it is not set.
146 int getOperandConstraint(unsigned OpNum,
147 TOI::OperandConstraint Constraint) const {
148 if (OpNum < NumOperands &&
149 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
150 unsigned Pos = 16 + Constraint * 4;
151 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
156 /// getRegClass - Returns the register class constraint for OpNum, or NULL.
157 const TargetRegisterClass *getRegClass(unsigned OpNum,
158 const TargetRegisterInfo *TRI) const {
159 return OpNum < NumOperands ? OpInfo[OpNum].getRegClass(TRI) : 0;
162 /// getOpcode - Return the opcode number for this descriptor.
163 unsigned getOpcode() const {
167 /// getName - Return the name of the record in the .td file for this
168 /// instruction, for example "ADD8ri".
169 const char *getName() const {
173 /// getNumOperands - Return the number of declared MachineOperands for this
174 /// MachineInstruction. Note that variadic (isVariadic() returns true)
175 /// instructions may have additional operands at the end of the list, and note
176 /// that the machine instruction may include implicit register def/uses as
178 unsigned getNumOperands() const {
182 /// getNumDefs - Return the number of MachineOperands that are register
183 /// definitions. Register definitions always occur at the start of the
184 /// machine operand list. This is the number of "outs" in the .td file,
185 /// and does not include implicit defs.
186 unsigned getNumDefs() const {
190 /// isVariadic - Return true if this instruction can have a variable number of
191 /// operands. In this case, the variable operands will be after the normal
192 /// operands but before the implicit definitions and uses (if any are
194 bool isVariadic() const {
195 return Flags & (1 << TID::Variadic);
198 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
199 /// ARM instructions which can set condition code if 's' bit is set.
200 bool hasOptionalDef() const {
201 return Flags & (1 << TID::HasOptionalDef);
204 /// getImplicitUses - Return a list of registers that are potentially
205 /// read by any instance of this machine instruction. For example, on X86,
206 /// the "adc" instruction adds two register operands and adds the carry bit in
207 /// from the flags register. In this case, the instruction is marked as
208 /// implicitly reading the flags. Likewise, the variable shift instruction on
209 /// X86 is marked as implicitly reading the 'CL' register, which it always
212 /// This method returns null if the instruction has no implicit uses.
213 const unsigned *getImplicitUses() const {
217 /// getNumImplicitUses - Return the number of implicit uses this instruction
219 unsigned getNumImplicitUses() const {
220 if (ImplicitUses == 0) return 0;
222 for (; ImplicitUses[i]; ++i) /*empty*/;
227 /// getImplicitDefs - Return a list of registers that are potentially
228 /// written by any instance of this machine instruction. For example, on X86,
229 /// many instructions implicitly set the flags register. In this case, they
230 /// are marked as setting the FLAGS. Likewise, many instructions always
231 /// deposit their result in a physical register. For example, the X86 divide
232 /// instruction always deposits the quotient and remainder in the EAX/EDX
233 /// registers. For that instruction, this will return a list containing the
234 /// EAX/EDX/EFLAGS registers.
236 /// This method returns null if the instruction has no implicit defs.
237 const unsigned *getImplicitDefs() const {
241 /// getNumImplicitDefs - Return the number of implicit defs this instruction
243 unsigned getNumImplicitDefs() const {
244 if (ImplicitDefs == 0) return 0;
246 for (; ImplicitDefs[i]; ++i) /*empty*/;
250 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
251 /// uses the specified physical register.
252 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
253 if (const unsigned *ImpUses = ImplicitUses)
254 for (; *ImpUses; ++ImpUses)
255 if (*ImpUses == Reg) return true;
259 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
260 /// defines the specified physical register.
261 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
262 if (const unsigned *ImpDefs = ImplicitDefs)
263 for (; *ImpDefs; ++ImpDefs)
264 if (*ImpDefs == Reg) return true;
268 /// getRegClassBarriers - Return a list of register classes that are
269 /// completely clobbered by this machine instruction. For example, on X86
270 /// the call instructions will completely clobber all the registers in the
271 /// fp stack and XMM classes.
273 /// This method returns null if the instruction doesn't completely clobber
274 /// any register class.
275 const TargetRegisterClass **getRegClassBarriers() const {
279 /// getSchedClass - Return the scheduling class for this instruction. The
280 /// scheduling class is an index into the InstrItineraryData table. This
281 /// returns zero if there is no known scheduling information for the
284 unsigned getSchedClass() const {
288 bool isReturn() const {
289 return Flags & (1 << TID::Return);
292 bool isCall() const {
293 return Flags & (1 << TID::Call);
296 /// isBarrier - Returns true if the specified instruction stops control flow
297 /// from executing the instruction immediately following it. Examples include
298 /// unconditional branches and return instructions.
299 bool isBarrier() const {
300 return Flags & (1 << TID::Barrier);
303 /// isTerminator - Returns true if this instruction part of the terminator for
304 /// a basic block. Typically this is things like return and branch
307 /// Various passes use this to insert code into the bottom of a basic block,
308 /// but before control flow occurs.
309 bool isTerminator() const {
310 return Flags & (1 << TID::Terminator);
313 /// isBranch - Returns true if this is a conditional, unconditional, or
314 /// indirect branch. Predicates below can be used to discriminate between
315 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
316 /// get more information.
317 bool isBranch() const {
318 return Flags & (1 << TID::Branch);
321 /// isIndirectBranch - Return true if this is an indirect branch, such as a
322 /// branch through a register.
323 bool isIndirectBranch() const {
324 return Flags & (1 << TID::IndirectBranch);
327 /// isConditionalBranch - Return true if this is a branch which may fall
328 /// through to the next instruction or may transfer control flow to some other
329 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
330 /// information about this branch.
331 bool isConditionalBranch() const {
332 return isBranch() & !isBarrier() & !isIndirectBranch();
335 /// isUnconditionalBranch - Return true if this is a branch which always
336 /// transfers control flow to some other block. The
337 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
338 /// about this branch.
339 bool isUnconditionalBranch() const {
340 return isBranch() & isBarrier() & !isIndirectBranch();
343 // isPredicable - Return true if this instruction has a predicate operand that
344 // controls execution. It may be set to 'always', or may be set to other
345 /// values. There are various methods in TargetInstrInfo that can be used to
346 /// control and modify the predicate in this instruction.
347 bool isPredicable() const {
348 return Flags & (1 << TID::Predicable);
351 /// isCompare - Return true if this instruction is a comparison.
352 bool isCompare() const {
353 return Flags & (1 << TID::Compare);
356 /// isMoveImmediate - Return true if this instruction is a move immediate
357 /// (including conditional moves) instruction.
358 bool isMoveImmediate() const {
359 return Flags & (1 << TID::MoveImm);
362 /// isNotDuplicable - Return true if this instruction cannot be safely
363 /// duplicated. For example, if the instruction has a unique labels attached
364 /// to it, duplicating it would cause multiple definition errors.
365 bool isNotDuplicable() const {
366 return Flags & (1 << TID::NotDuplicable);
369 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
370 /// which must be filled by the code generator.
371 bool hasDelaySlot() const {
372 return Flags & (1 << TID::DelaySlot);
375 /// canFoldAsLoad - Return true for instructions that can be folded as
376 /// memory operands in other instructions. The most common use for this
377 /// is instructions that are simple loads from memory that don't modify
378 /// the loaded value in any way, but it can also be used for instructions
379 /// that can be expressed as constant-pool loads, such as V_SETALLONES
380 /// on x86, to allow them to be folded when it is beneficial.
381 /// This should only be set on instructions that return a value in their
382 /// only virtual register definition.
383 bool canFoldAsLoad() const {
384 return Flags & (1 << TID::FoldableAsLoad);
387 //===--------------------------------------------------------------------===//
388 // Side Effect Analysis
389 //===--------------------------------------------------------------------===//
391 /// mayLoad - Return true if this instruction could possibly read memory.
392 /// Instructions with this flag set are not necessarily simple load
393 /// instructions, they may load a value and modify it, for example.
394 bool mayLoad() const {
395 return Flags & (1 << TID::MayLoad);
399 /// mayStore - Return true if this instruction could possibly modify memory.
400 /// Instructions with this flag set are not necessarily simple store
401 /// instructions, they may store a modified value based on their operands, or
402 /// may not actually modify anything, for example.
403 bool mayStore() const {
404 return Flags & (1 << TID::MayStore);
407 /// hasUnmodeledSideEffects - Return true if this instruction has side
408 /// effects that are not modeled by other flags. This does not return true
409 /// for instructions whose effects are captured by:
411 /// 1. Their operand list and implicit definition/use list. Register use/def
412 /// info is explicit for instructions.
413 /// 2. Memory accesses. Use mayLoad/mayStore.
414 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
416 /// Examples of side effects would be modifying 'invisible' machine state like
417 /// a control register, flushing a cache, modifying a register invisible to
420 bool hasUnmodeledSideEffects() const {
421 return Flags & (1 << TID::UnmodeledSideEffects);
424 //===--------------------------------------------------------------------===//
425 // Flags that indicate whether an instruction can be modified by a method.
426 //===--------------------------------------------------------------------===//
428 /// isCommutable - Return true if this may be a 2- or 3-address
429 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
430 /// result if Y and Z are exchanged. If this flag is set, then the
431 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
434 /// Note that this flag may be set on instructions that are only commutable
435 /// sometimes. In these cases, the call to commuteInstruction will fail.
436 /// Also note that some instructions require non-trivial modification to
438 bool isCommutable() const {
439 return Flags & (1 << TID::Commutable);
442 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
443 /// which can be changed into a 3-address instruction if needed. Doing this
444 /// transformation can be profitable in the register allocator, because it
445 /// means that the instruction can use a 2-address form if possible, but
446 /// degrade into a less efficient form if the source and dest register cannot
447 /// be assigned to the same register. For example, this allows the x86
448 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
449 /// is the same speed as the shift but has bigger code size.
451 /// If this returns true, then the target must implement the
452 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
453 /// is allowed to fail if the transformation isn't valid for this specific
454 /// instruction (e.g. shl reg, 4 on x86).
456 bool isConvertibleTo3Addr() const {
457 return Flags & (1 << TID::ConvertibleTo3Addr);
460 /// usesCustomInsertionHook - Return true if this instruction requires
461 /// custom insertion support when the DAG scheduler is inserting it into a
462 /// machine basic block. If this is true for the instruction, it basically
463 /// means that it is a pseudo instruction used at SelectionDAG time that is
464 /// expanded out into magic code by the target when MachineInstrs are formed.
466 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
467 /// is used to insert this into the MachineBasicBlock.
468 bool usesCustomInsertionHook() const {
469 return Flags & (1 << TID::UsesCustomInserter);
472 /// isRematerializable - Returns true if this instruction is a candidate for
473 /// remat. This flag is deprecated, please don't use it anymore. If this
474 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
475 /// verify the instruction is really rematable.
476 bool isRematerializable() const {
477 return Flags & (1 << TID::Rematerializable);
480 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
481 /// less) than a move instruction. This is useful during certain types of
482 /// optimizations (e.g., remat during two-address conversion or machine licm)
483 /// where we would like to remat or hoist the instruction, but not if it costs
484 /// more than moving the instruction into the appropriate register. Note, we
485 /// are not marking copies from and to the same register class with this flag.
486 bool isAsCheapAsAMove() const {
487 return Flags & (1 << TID::CheapAsAMove);
490 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
491 /// have special register allocation requirements that are not captured by the
492 /// operand register classes. e.g. ARM::STRD's two source registers must be an
493 /// even / odd pair, ARM::STM registers have to be in ascending order.
494 /// Post-register allocation passes should not attempt to change allocations
495 /// for sources of instructions with this flag.
496 bool hasExtraSrcRegAllocReq() const {
497 return Flags & (1 << TID::ExtraSrcRegAllocReq);
500 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
501 /// have special register allocation requirements that are not captured by the
502 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
503 /// even / odd pair, ARM::LDM registers have to be in ascending order.
504 /// Post-register allocation passes should not attempt to change allocations
505 /// for definitions of instructions with this flag.
506 bool hasExtraDefRegAllocReq() const {
507 return Flags & (1 << TID::ExtraDefRegAllocReq);
511 } // end namespace llvm