1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
18 #include "llvm/System/DataTypes.h"
22 class TargetRegisterClass;
23 class TargetRegisterInfo;
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// OperandFlags - These are flags set on operands, but should be considered
37 /// private, all access should go through the TargetOperandInfo accessors.
38 /// See the accessors for a description of what these are.
40 LookupPtrRegClass = 0,
46 /// TargetOperandInfo - This holds information about one operand of a machine
47 /// instruction, indicating the register class for register operands, etc.
49 class TargetOperandInfo {
51 /// RegClass - This specifies the register class enumeration of the operand
52 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
53 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
54 /// get a dynamic register class.
56 /// NOTE: This member should be considered to be private, all access should go
57 /// through "getRegClass(TRI)" below.
60 /// Flags - These are flags from the TOI::OperandFlags enum.
63 /// Lower 16 bits are used to specify which constraints are set. The higher 16
64 /// bits are used to specify the value of constraints (4 bits each).
66 /// Currently no other information.
68 /// getRegClass - Get the register class for the operand, handling resolution
69 /// of "symbolic" pointer register classes etc. If this is not a register
70 /// operand, this returns null.
71 const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const;
74 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75 /// requires a callback to look up its register class.
76 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
78 /// isPredicate - Set if this is one of the operands that made up of
79 /// the predicate operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
82 /// isOptionalDef - Set if this operand is a optional def.
84 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
88 //===----------------------------------------------------------------------===//
89 // Machine Instruction Flags and Description
90 //===----------------------------------------------------------------------===//
92 /// TargetInstrDesc flags - These should be considered private to the
93 /// implementation of the TargetInstrDesc class. Clients should use the
94 /// predicate methods on TargetInstrDesc, not use these directly. These
95 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
112 UnmodeledSideEffects,
123 /// TargetInstrDesc - Describe properties that are true of each
124 /// instruction in the target description file. This captures information about
125 /// side effects, register use and many other things. There is one instance of
126 /// this struct for each target instruction class, and the MachineInstr class
127 /// points to this struct directly to describe itself.
128 class TargetInstrDesc {
130 unsigned short Opcode; // The opcode number
131 unsigned short NumOperands; // Num of args (may be more if variable_ops)
132 unsigned short NumDefs; // Num of args that are definitions
133 unsigned short SchedClass; // enum identifying instr sched class
134 const char * Name; // Name of the instruction record in td file
135 unsigned Flags; // Flags identifying machine instr class
136 uint64_t TSFlags; // Target Specific Flag values
137 const unsigned *ImplicitUses; // Registers implicitly read by this instr
138 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
139 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
140 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
142 /// getOperandConstraint - Returns the value of the specific constraint if
143 /// it is set. Returns -1 if it is not set.
144 int getOperandConstraint(unsigned OpNum,
145 TOI::OperandConstraint Constraint) const {
146 if (OpNum < NumOperands &&
147 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
148 unsigned Pos = 16 + Constraint * 4;
149 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
154 /// getOpcode - Return the opcode number for this descriptor.
155 unsigned getOpcode() const {
159 /// getName - Return the name of the record in the .td file for this
160 /// instruction, for example "ADD8ri".
161 const char *getName() const {
165 /// getNumOperands - Return the number of declared MachineOperands for this
166 /// MachineInstruction. Note that variadic (isVariadic() returns true)
167 /// instructions may have additional operands at the end of the list, and note
168 /// that the machine instruction may include implicit register def/uses as
170 unsigned getNumOperands() const {
174 /// getNumDefs - Return the number of MachineOperands that are register
175 /// definitions. Register definitions always occur at the start of the
176 /// machine operand list. This is the number of "outs" in the .td file,
177 /// and does not include implicit defs.
178 unsigned getNumDefs() const {
182 /// isVariadic - Return true if this instruction can have a variable number of
183 /// operands. In this case, the variable operands will be after the normal
184 /// operands but before the implicit definitions and uses (if any are
186 bool isVariadic() const {
187 return Flags & (1 << TID::Variadic);
190 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
191 /// ARM instructions which can set condition code if 's' bit is set.
192 bool hasOptionalDef() const {
193 return Flags & (1 << TID::HasOptionalDef);
196 /// getImplicitUses - Return a list of registers that are potentially
197 /// read by any instance of this machine instruction. For example, on X86,
198 /// the "adc" instruction adds two register operands and adds the carry bit in
199 /// from the flags register. In this case, the instruction is marked as
200 /// implicitly reading the flags. Likewise, the variable shift instruction on
201 /// X86 is marked as implicitly reading the 'CL' register, which it always
204 /// This method returns null if the instruction has no implicit uses.
205 const unsigned *getImplicitUses() const {
209 /// getNumImplicitUses - Return the number of implicit uses this instruction
211 unsigned getNumImplicitUses() const {
212 if (ImplicitUses == 0) return 0;
214 for (; ImplicitUses[i]; ++i) /*empty*/;
219 /// getImplicitDefs - Return a list of registers that are potentially
220 /// written by any instance of this machine instruction. For example, on X86,
221 /// many instructions implicitly set the flags register. In this case, they
222 /// are marked as setting the FLAGS. Likewise, many instructions always
223 /// deposit their result in a physical register. For example, the X86 divide
224 /// instruction always deposits the quotient and remainder in the EAX/EDX
225 /// registers. For that instruction, this will return a list containing the
226 /// EAX/EDX/EFLAGS registers.
228 /// This method returns null if the instruction has no implicit defs.
229 const unsigned *getImplicitDefs() const {
233 /// getNumImplicitDefs - Return the number of implicit defs this instruction
235 unsigned getNumImplicitDefs() const {
236 if (ImplicitDefs == 0) return 0;
238 for (; ImplicitDefs[i]; ++i) /*empty*/;
242 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
243 /// uses the specified physical register.
244 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
245 if (const unsigned *ImpUses = ImplicitUses)
246 for (; *ImpUses; ++ImpUses)
247 if (*ImpUses == Reg) return true;
251 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
252 /// defines the specified physical register.
253 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
254 if (const unsigned *ImpDefs = ImplicitDefs)
255 for (; *ImpDefs; ++ImpDefs)
256 if (*ImpDefs == Reg) return true;
260 /// getRegClassBarriers - Return a list of register classes that are
261 /// completely clobbered by this machine instruction. For example, on X86
262 /// the call instructions will completely clobber all the registers in the
263 /// fp stack and XMM classes.
265 /// This method returns null if the instruction doesn't completely clobber
266 /// any register class.
267 const TargetRegisterClass **getRegClassBarriers() const {
271 /// getSchedClass - Return the scheduling class for this instruction. The
272 /// scheduling class is an index into the InstrItineraryData table. This
273 /// returns zero if there is no known scheduling information for the
276 unsigned getSchedClass() const {
280 bool isReturn() const {
281 return Flags & (1 << TID::Return);
284 bool isCall() const {
285 return Flags & (1 << TID::Call);
288 /// isBarrier - Returns true if the specified instruction stops control flow
289 /// from executing the instruction immediately following it. Examples include
290 /// unconditional branches and return instructions.
291 bool isBarrier() const {
292 return Flags & (1 << TID::Barrier);
295 /// isTerminator - Returns true if this instruction part of the terminator for
296 /// a basic block. Typically this is things like return and branch
299 /// Various passes use this to insert code into the bottom of a basic block,
300 /// but before control flow occurs.
301 bool isTerminator() const {
302 return Flags & (1 << TID::Terminator);
305 /// isBranch - Returns true if this is a conditional, unconditional, or
306 /// indirect branch. Predicates below can be used to discriminate between
307 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
308 /// get more information.
309 bool isBranch() const {
310 return Flags & (1 << TID::Branch);
313 /// isIndirectBranch - Return true if this is an indirect branch, such as a
314 /// branch through a register.
315 bool isIndirectBranch() const {
316 return Flags & (1 << TID::IndirectBranch);
319 /// isConditionalBranch - Return true if this is a branch which may fall
320 /// through to the next instruction or may transfer control flow to some other
321 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
322 /// information about this branch.
323 bool isConditionalBranch() const {
324 return isBranch() & !isBarrier() & !isIndirectBranch();
327 /// isUnconditionalBranch - Return true if this is a branch which always
328 /// transfers control flow to some other block. The
329 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
330 /// about this branch.
331 bool isUnconditionalBranch() const {
332 return isBranch() & isBarrier() & !isIndirectBranch();
335 // isPredicable - Return true if this instruction has a predicate operand that
336 // controls execution. It may be set to 'always', or may be set to other
337 /// values. There are various methods in TargetInstrInfo that can be used to
338 /// control and modify the predicate in this instruction.
339 bool isPredicable() const {
340 return Flags & (1 << TID::Predicable);
343 /// isNotDuplicable - Return true if this instruction cannot be safely
344 /// duplicated. For example, if the instruction has a unique labels attached
345 /// to it, duplicating it would cause multiple definition errors.
346 bool isNotDuplicable() const {
347 return Flags & (1 << TID::NotDuplicable);
350 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
351 /// which must be filled by the code generator.
352 bool hasDelaySlot() const {
353 return Flags & (1 << TID::DelaySlot);
356 /// canFoldAsLoad - Return true for instructions that can be folded as
357 /// memory operands in other instructions. The most common use for this
358 /// is instructions that are simple loads from memory that don't modify
359 /// the loaded value in any way, but it can also be used for instructions
360 /// that can be expressed as constant-pool loads, such as V_SETALLONES
361 /// on x86, to allow them to be folded when it is beneficial.
362 /// This should only be set on instructions that return a value in their
363 /// only virtual register definition.
364 bool canFoldAsLoad() const {
365 return Flags & (1 << TID::FoldableAsLoad);
368 //===--------------------------------------------------------------------===//
369 // Side Effect Analysis
370 //===--------------------------------------------------------------------===//
372 /// mayLoad - Return true if this instruction could possibly read memory.
373 /// Instructions with this flag set are not necessarily simple load
374 /// instructions, they may load a value and modify it, for example.
375 bool mayLoad() const {
376 return Flags & (1 << TID::MayLoad);
380 /// mayStore - Return true if this instruction could possibly modify memory.
381 /// Instructions with this flag set are not necessarily simple store
382 /// instructions, they may store a modified value based on their operands, or
383 /// may not actually modify anything, for example.
384 bool mayStore() const {
385 return Flags & (1 << TID::MayStore);
388 /// hasUnmodeledSideEffects - Return true if this instruction has side
389 /// effects that are not modeled by other flags. This does not return true
390 /// for instructions whose effects are captured by:
392 /// 1. Their operand list and implicit definition/use list. Register use/def
393 /// info is explicit for instructions.
394 /// 2. Memory accesses. Use mayLoad/mayStore.
395 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
397 /// Examples of side effects would be modifying 'invisible' machine state like
398 /// a control register, flushing a cache, modifying a register invisible to
401 bool hasUnmodeledSideEffects() const {
402 return Flags & (1 << TID::UnmodeledSideEffects);
405 //===--------------------------------------------------------------------===//
406 // Flags that indicate whether an instruction can be modified by a method.
407 //===--------------------------------------------------------------------===//
409 /// isCommutable - Return true if this may be a 2- or 3-address
410 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
411 /// result if Y and Z are exchanged. If this flag is set, then the
412 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
415 /// Note that this flag may be set on instructions that are only commutable
416 /// sometimes. In these cases, the call to commuteInstruction will fail.
417 /// Also note that some instructions require non-trivial modification to
419 bool isCommutable() const {
420 return Flags & (1 << TID::Commutable);
423 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
424 /// which can be changed into a 3-address instruction if needed. Doing this
425 /// transformation can be profitable in the register allocator, because it
426 /// means that the instruction can use a 2-address form if possible, but
427 /// degrade into a less efficient form if the source and dest register cannot
428 /// be assigned to the same register. For example, this allows the x86
429 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
430 /// is the same speed as the shift but has bigger code size.
432 /// If this returns true, then the target must implement the
433 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
434 /// is allowed to fail if the transformation isn't valid for this specific
435 /// instruction (e.g. shl reg, 4 on x86).
437 bool isConvertibleTo3Addr() const {
438 return Flags & (1 << TID::ConvertibleTo3Addr);
441 /// usesCustomInsertionHook - Return true if this instruction requires
442 /// custom insertion support when the DAG scheduler is inserting it into a
443 /// machine basic block. If this is true for the instruction, it basically
444 /// means that it is a pseudo instruction used at SelectionDAG time that is
445 /// expanded out into magic code by the target when MachineInstrs are formed.
447 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
448 /// is used to insert this into the MachineBasicBlock.
449 bool usesCustomInsertionHook() const {
450 return Flags & (1 << TID::UsesCustomInserter);
453 /// isRematerializable - Returns true if this instruction is a candidate for
454 /// remat. This flag is deprecated, please don't use it anymore. If this
455 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
456 /// verify the instruction is really rematable.
457 bool isRematerializable() const {
458 return Flags & (1 << TID::Rematerializable);
461 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
462 /// less) than a move instruction. This is useful during certain types of
463 /// optimizations (e.g., remat during two-address conversion or machine licm)
464 /// where we would like to remat or hoist the instruction, but not if it costs
465 /// more than moving the instruction into the appropriate register. Note, we
466 /// are not marking copies from and to the same register class with this flag.
467 bool isAsCheapAsAMove() const {
468 return Flags & (1 << TID::CheapAsAMove);
471 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
472 /// have special register allocation requirements that are not captured by the
473 /// operand register classes. e.g. ARM::STRD's two source registers must be an
474 /// even / odd pair, ARM::STM registers have to be in ascending order.
475 /// Post-register allocation passes should not attempt to change allocations
476 /// for sources of instructions with this flag.
477 bool hasExtraSrcRegAllocReq() const {
478 return Flags & (1 << TID::ExtraSrcRegAllocReq);
481 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
482 /// have special register allocation requirements that are not captured by the
483 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
484 /// even / odd pair, ARM::LDM registers have to be in ascending order.
485 /// Post-register allocation passes should not attempt to change allocations
486 /// for definitions of instructions with this flag.
487 bool hasExtraDefRegAllocReq() const {
488 return Flags & (1 << TID::ExtraDefRegAllocReq);
492 } // end namespace llvm