1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
20 class TargetRegisterClass;
21 class TargetRegisterInfo;
23 //===----------------------------------------------------------------------===//
24 // Machine Operand Flags and Description
25 //===----------------------------------------------------------------------===//
28 // Operand constraints
29 enum OperandConstraint {
30 TIED_TO = 0, // Must be allocated the same register as.
31 EARLY_CLOBBER // Operand is an early clobber register operand
34 /// OperandFlags - These are flags set on operands, but should be considered
35 /// private, all access should go through the TargetOperandInfo accessors.
36 /// See the accessors for a description of what these are.
38 LookupPtrRegClass = 0,
44 /// TargetOperandInfo - This holds information about one operand of a machine
45 /// instruction, indicating the register class for register operands, etc.
47 class TargetOperandInfo {
49 /// RegClass - This specifies the register class enumeration of the operand
50 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
51 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
52 /// get a dynamic register class.
54 /// NOTE: This member should be considered to be private, all access should go
55 /// through "getRegClass(TRI)" below.
56 unsigned short RegClass;
58 /// Flags - These are flags from the TOI::OperandFlags enum.
61 /// Lower 16 bits are used to specify which constraints are set. The higher 16
62 /// bits are used to specify the value of constraints (4 bits each).
64 /// Currently no other information.
66 /// getRegClass - Get the register class for the operand, handling resolution
67 /// of "symbolic" pointer register classes etc. If this is not a register
68 /// operand, this returns null.
69 const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const;
72 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
73 /// requires a callback to look up its register class.
74 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
76 /// isPredicate - Set if this is one of the operands that made up of
77 /// the predicate operand that controls an isPredicable() instruction.
78 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
80 /// isOptionalDef - Set if this operand is a optional def.
82 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
86 //===----------------------------------------------------------------------===//
87 // Machine Instruction Flags and Description
88 //===----------------------------------------------------------------------===//
90 /// TargetInstrDesc flags - These should be considered private to the
91 /// implementation of the TargetInstrDesc class. Clients should use the
92 /// predicate methods on TargetInstrDesc, not use these directly. These
93 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
110 UnmodeledSideEffects,
121 /// TargetInstrDesc - Describe properties that are true of each
122 /// instruction in the target description file. This captures information about
123 /// side effects, register use and many other things. There is one instance of
124 /// this struct for each target instruction class, and the MachineInstr class
125 /// points to this struct directly to describe itself.
126 class TargetInstrDesc {
128 unsigned short Opcode; // The opcode number
129 unsigned short NumOperands; // Num of args (may be more if variable_ops)
130 unsigned short NumDefs; // Num of args that are definitions
131 unsigned short SchedClass; // enum identifying instr sched class
132 const char * Name; // Name of the instruction record in td file
133 unsigned Flags; // Flags identifying machine instr class
134 unsigned TSFlags; // Target Specific Flag values
135 const unsigned *ImplicitUses; // Registers implicitly read by this instr
136 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
137 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
138 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
140 /// getOperandConstraint - Returns the value of the specific constraint if
141 /// it is set. Returns -1 if it is not set.
142 int getOperandConstraint(unsigned OpNum,
143 TOI::OperandConstraint Constraint) const {
144 if (OpNum < NumOperands &&
145 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
146 unsigned Pos = 16 + Constraint * 4;
147 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
152 /// getOpcode - Return the opcode number for this descriptor.
153 unsigned getOpcode() const {
157 /// getName - Return the name of the record in the .td file for this
158 /// instruction, for example "ADD8ri".
159 const char *getName() const {
163 /// getNumOperands - Return the number of declared MachineOperands for this
164 /// MachineInstruction. Note that variadic (isVariadic() returns true)
165 /// instructions may have additional operands at the end of the list, and note
166 /// that the machine instruction may include implicit register def/uses as
168 unsigned getNumOperands() const {
172 /// getNumDefs - Return the number of MachineOperands that are register
173 /// definitions. Register definitions always occur at the start of the
174 /// machine operand list. This is the number of "outs" in the .td file,
175 /// and does not include implicit defs.
176 unsigned getNumDefs() const {
180 /// isVariadic - Return true if this instruction can have a variable number of
181 /// operands. In this case, the variable operands will be after the normal
182 /// operands but before the implicit definitions and uses (if any are
184 bool isVariadic() const {
185 return Flags & (1 << TID::Variadic);
188 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
189 /// ARM instructions which can set condition code if 's' bit is set.
190 bool hasOptionalDef() const {
191 return Flags & (1 << TID::HasOptionalDef);
194 /// getImplicitUses - Return a list of registers that are potentially
195 /// read by any instance of this machine instruction. For example, on X86,
196 /// the "adc" instruction adds two register operands and adds the carry bit in
197 /// from the flags register. In this case, the instruction is marked as
198 /// implicitly reading the flags. Likewise, the variable shift instruction on
199 /// X86 is marked as implicitly reading the 'CL' register, which it always
202 /// This method returns null if the instruction has no implicit uses.
203 const unsigned *getImplicitUses() const {
207 /// getNumImplicitUses - Return the number of implicit uses this instruction
209 unsigned getNumImplicitUses() const {
210 if (ImplicitUses == 0) return 0;
212 for (; ImplicitUses[i]; ++i) /*empty*/;
217 /// getImplicitDefs - Return a list of registers that are potentially
218 /// written by any instance of this machine instruction. For example, on X86,
219 /// many instructions implicitly set the flags register. In this case, they
220 /// are marked as setting the FLAGS. Likewise, many instructions always
221 /// deposit their result in a physical register. For example, the X86 divide
222 /// instruction always deposits the quotient and remainder in the EAX/EDX
223 /// registers. For that instruction, this will return a list containing the
224 /// EAX/EDX/EFLAGS registers.
226 /// This method returns null if the instruction has no implicit defs.
227 const unsigned *getImplicitDefs() const {
231 /// getNumImplicitDefs - Return the number of implicit defs this instruction
233 unsigned getNumImplicitDefs() const {
234 if (ImplicitDefs == 0) return 0;
236 for (; ImplicitDefs[i]; ++i) /*empty*/;
240 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
241 /// uses the specified physical register.
242 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
243 if (const unsigned *ImpUses = ImplicitUses)
244 for (; *ImpUses; ++ImpUses)
245 if (*ImpUses == Reg) return true;
249 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
250 /// defines the specified physical register.
251 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
252 if (const unsigned *ImpDefs = ImplicitDefs)
253 for (; *ImpDefs; ++ImpDefs)
254 if (*ImpDefs == Reg) return true;
258 /// getRegClassBarriers - Return a list of register classes that are
259 /// completely clobbered by this machine instruction. For example, on X86
260 /// the call instructions will completely clobber all the registers in the
261 /// fp stack and XMM classes.
263 /// This method returns null if the instruction doesn't completely clobber
264 /// any register class.
265 const TargetRegisterClass **getRegClassBarriers() const {
269 /// getSchedClass - Return the scheduling class for this instruction. The
270 /// scheduling class is an index into the InstrItineraryData table. This
271 /// returns zero if there is no known scheduling information for the
274 unsigned getSchedClass() const {
278 bool isReturn() const {
279 return Flags & (1 << TID::Return);
282 bool isCall() const {
283 return Flags & (1 << TID::Call);
286 /// isBarrier - Returns true if the specified instruction stops control flow
287 /// from executing the instruction immediately following it. Examples include
288 /// unconditional branches and return instructions.
289 bool isBarrier() const {
290 return Flags & (1 << TID::Barrier);
293 /// isTerminator - Returns true if this instruction part of the terminator for
294 /// a basic block. Typically this is things like return and branch
297 /// Various passes use this to insert code into the bottom of a basic block,
298 /// but before control flow occurs.
299 bool isTerminator() const {
300 return Flags & (1 << TID::Terminator);
303 /// isBranch - Returns true if this is a conditional, unconditional, or
304 /// indirect branch. Predicates below can be used to discriminate between
305 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
306 /// get more information.
307 bool isBranch() const {
308 return Flags & (1 << TID::Branch);
311 /// isIndirectBranch - Return true if this is an indirect branch, such as a
312 /// branch through a register.
313 bool isIndirectBranch() const {
314 return Flags & (1 << TID::IndirectBranch);
317 /// isConditionalBranch - Return true if this is a branch which may fall
318 /// through to the next instruction or may transfer control flow to some other
319 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
320 /// information about this branch.
321 bool isConditionalBranch() const {
322 return isBranch() & !isBarrier() & !isIndirectBranch();
325 /// isUnconditionalBranch - Return true if this is a branch which always
326 /// transfers control flow to some other block. The
327 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
328 /// about this branch.
329 bool isUnconditionalBranch() const {
330 return isBranch() & isBarrier() & !isIndirectBranch();
333 // isPredicable - Return true if this instruction has a predicate operand that
334 // controls execution. It may be set to 'always', or may be set to other
335 /// values. There are various methods in TargetInstrInfo that can be used to
336 /// control and modify the predicate in this instruction.
337 bool isPredicable() const {
338 return Flags & (1 << TID::Predicable);
341 /// isNotDuplicable - Return true if this instruction cannot be safely
342 /// duplicated. For example, if the instruction has a unique labels attached
343 /// to it, duplicating it would cause multiple definition errors.
344 bool isNotDuplicable() const {
345 return Flags & (1 << TID::NotDuplicable);
348 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
349 /// which must be filled by the code generator.
350 bool hasDelaySlot() const {
351 return Flags & (1 << TID::DelaySlot);
354 /// canFoldAsLoad - Return true for instructions that can be folded as
355 /// memory operands in other instructions. The most common use for this
356 /// is instructions that are simple loads from memory that don't modify
357 /// the loaded value in any way, but it can also be used for instructions
358 /// that can be expressed as constant-pool loads, such as V_SETALLONES
359 /// on x86, to allow them to be folded when it is beneficial.
360 /// This should only be set on instructions that return a value in their
361 /// only virtual register definition.
362 bool canFoldAsLoad() const {
363 return Flags & (1 << TID::FoldableAsLoad);
366 //===--------------------------------------------------------------------===//
367 // Side Effect Analysis
368 //===--------------------------------------------------------------------===//
370 /// mayLoad - Return true if this instruction could possibly read memory.
371 /// Instructions with this flag set are not necessarily simple load
372 /// instructions, they may load a value and modify it, for example.
373 bool mayLoad() const {
374 return Flags & (1 << TID::MayLoad);
378 /// mayStore - Return true if this instruction could possibly modify memory.
379 /// Instructions with this flag set are not necessarily simple store
380 /// instructions, they may store a modified value based on their operands, or
381 /// may not actually modify anything, for example.
382 bool mayStore() const {
383 return Flags & (1 << TID::MayStore);
386 /// hasUnmodeledSideEffects - Return true if this instruction has side
387 /// effects that are not modeled by other flags. This does not return true
388 /// for instructions whose effects are captured by:
390 /// 1. Their operand list and implicit definition/use list. Register use/def
391 /// info is explicit for instructions.
392 /// 2. Memory accesses. Use mayLoad/mayStore.
393 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
395 /// Examples of side effects would be modifying 'invisible' machine state like
396 /// a control register, flushing a cache, modifying a register invisible to
399 bool hasUnmodeledSideEffects() const {
400 return Flags & (1 << TID::UnmodeledSideEffects);
403 //===--------------------------------------------------------------------===//
404 // Flags that indicate whether an instruction can be modified by a method.
405 //===--------------------------------------------------------------------===//
407 /// isCommutable - Return true if this may be a 2- or 3-address
408 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
409 /// result if Y and Z are exchanged. If this flag is set, then the
410 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
413 /// Note that this flag may be set on instructions that are only commutable
414 /// sometimes. In these cases, the call to commuteInstruction will fail.
415 /// Also note that some instructions require non-trivial modification to
417 bool isCommutable() const {
418 return Flags & (1 << TID::Commutable);
421 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
422 /// which can be changed into a 3-address instruction if needed. Doing this
423 /// transformation can be profitable in the register allocator, because it
424 /// means that the instruction can use a 2-address form if possible, but
425 /// degrade into a less efficient form if the source and dest register cannot
426 /// be assigned to the same register. For example, this allows the x86
427 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
428 /// is the same speed as the shift but has bigger code size.
430 /// If this returns true, then the target must implement the
431 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
432 /// is allowed to fail if the transformation isn't valid for this specific
433 /// instruction (e.g. shl reg, 4 on x86).
435 bool isConvertibleTo3Addr() const {
436 return Flags & (1 << TID::ConvertibleTo3Addr);
439 /// usesCustomInsertionHook - Return true if this instruction requires
440 /// custom insertion support when the DAG scheduler is inserting it into a
441 /// machine basic block. If this is true for the instruction, it basically
442 /// means that it is a pseudo instruction used at SelectionDAG time that is
443 /// expanded out into magic code by the target when MachineInstrs are formed.
445 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
446 /// is used to insert this into the MachineBasicBlock.
447 bool usesCustomInsertionHook() const {
448 return Flags & (1 << TID::UsesCustomInserter);
451 /// isRematerializable - Returns true if this instruction is a candidate for
452 /// remat. This flag is deprecated, please don't use it anymore. If this
453 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
454 /// verify the instruction is really rematable.
455 bool isRematerializable() const {
456 return Flags & (1 << TID::Rematerializable);
459 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
460 /// less) than a move instruction. This is useful during certain types of
461 /// optimizations (e.g., remat during two-address conversion or machine licm)
462 /// where we would like to remat or hoist the instruction, but not if it costs
463 /// more than moving the instruction into the appropriate register. Note, we
464 /// are not marking copies from and to the same register class with this flag.
465 bool isAsCheapAsAMove() const {
466 return Flags & (1 << TID::CheapAsAMove);
469 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
470 /// have special register allocation requirements that are not captured by the
471 /// operand register classes. e.g. ARM::STRD's two source registers must be an
472 /// even / odd pair, ARM::STM registers have to be in ascending order.
473 /// Post-register allocation passes should not attempt to change allocations
474 /// for sources of instructions with this flag.
475 bool hasExtraSrcRegAllocReq() const {
476 return Flags & (1 << TID::ExtraSrcRegAllocReq);
479 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
480 /// have special register allocation requirements that are not captured by the
481 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
482 /// even / odd pair, ARM::LDM registers have to be in ascending order.
483 /// Post-register allocation passes should not attempt to change allocations
484 /// for definitions of instructions with this flag.
485 bool hasExtraDefRegAllocReq() const {
486 return Flags & (1 << TID::ExtraDefRegAllocReq);
490 } // end namespace llvm