1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
22 class TargetRegisterClass;
24 //===----------------------------------------------------------------------===//
25 // Machine Operand Flags and Description
26 //===----------------------------------------------------------------------===//
29 // Operand constraints: only "tied_to" for now.
30 enum OperandConstraint {
31 TIED_TO = 0 // Must be allocated the same register as.
34 /// OperandFlags - These are flags set on operands, but should be considered
35 /// private, all access should go through the TargetOperandInfo accessors.
36 /// See the accessors for a description of what these are.
38 LookupPtrRegClass = 0,
44 /// TargetOperandInfo - This holds information about one operand of a machine
45 /// instruction, indicating the register class for register operands, etc.
47 class TargetOperandInfo {
49 /// RegClass - This specifies the register class enumeration of the operand
50 /// if the operand is a register. If not, this contains 0.
51 unsigned short RegClass;
53 /// Lower 16 bits are used to specify which constraints are set. The higher 16
54 /// bits are used to specify the value of constraints (4 bits each).
55 unsigned int Constraints;
56 /// Currently no other information.
58 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
59 /// requires a callback to look up its register class.
60 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
62 /// isPredicate - Set if this is one of the operands that made up of
63 /// the predicate operand that controls an isPredicable() instruction.
64 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
66 /// isOptionalDef - Set if this operand is a optional def.
68 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
72 //===----------------------------------------------------------------------===//
73 // Machine Instruction Flags and Description
74 //===----------------------------------------------------------------------===//
76 /// TargetInstrDesc flags - These should be considered private to the
77 /// implementation of the TargetInstrDesc class. Clients should use the
78 /// predicate methods on TargetInstrDesc, not use these directly. These
79 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
99 UsesCustomDAGSchedInserter,
105 /// TargetInstrDesc - Describe properties that are true of each
106 /// instruction in the target description file. This captures information about
107 /// side effects, register use and many other things. There is one instance of
108 /// this struct for each target instruction class, and the MachineInstr class
109 /// points to this struct directly to describe itself.
110 class TargetInstrDesc {
112 unsigned short Opcode; // The opcode number
113 unsigned short NumOperands; // Num of args (may be more if variable_ops)
114 unsigned short NumDefs; // Num of args that are definitions
115 unsigned short SchedClass; // enum identifying instr sched class
116 const char * Name; // Name of the instruction record in td file
117 unsigned Flags; // Flags identifying machine instr class
118 unsigned TSFlags; // Target Specific Flag values
119 const unsigned *ImplicitUses; // Registers implicitly read by this instr
120 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
121 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
122 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
124 /// getOperandConstraint - Returns the value of the specific constraint if
125 /// it is set. Returns -1 if it is not set.
126 int getOperandConstraint(unsigned OpNum,
127 TOI::OperandConstraint Constraint) const {
128 if (OpNum < NumOperands &&
129 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
130 unsigned Pos = 16 + Constraint * 4;
131 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
136 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
137 /// dest operand. Returns -1 if there isn't one.
138 int findTiedToSrcOperand(unsigned OpNum) const;
140 /// getOpcode - Return the opcode number for this descriptor.
141 unsigned getOpcode() const {
145 /// getName - Return the name of the record in the .td file for this
146 /// instruction, for example "ADD8ri".
147 const char *getName() const {
151 /// getNumOperands - Return the number of declared MachineOperands for this
152 /// MachineInstruction. Note that variadic (isVariadic() returns true)
153 /// instructions may have additional operands at the end of the list, and note
154 /// that the machine instruction may include implicit register def/uses as
156 unsigned getNumOperands() const {
160 /// getNumDefs - Return the number of MachineOperands that are register
161 /// definitions. Register definitions always occur at the start of the
162 /// machine operand list. This is the number of "outs" in the .td file.
163 unsigned getNumDefs() const {
167 /// isVariadic - Return true if this instruction can have a variable number of
168 /// operands. In this case, the variable operands will be after the normal
169 /// operands but before the implicit definitions and uses (if any are
171 bool isVariadic() const {
172 return Flags & (1 << TID::Variadic);
175 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
176 /// ARM instructions which can set condition code if 's' bit is set.
177 bool hasOptionalDef() const {
178 return Flags & (1 << TID::HasOptionalDef);
181 /// getImplicitUses - Return a list of registers that are potentially
182 /// read by any instance of this machine instruction. For example, on X86,
183 /// the "adc" instruction adds two register operands and adds the carry bit in
184 /// from the flags register. In this case, the instruction is marked as
185 /// implicitly reading the flags. Likewise, the variable shift instruction on
186 /// X86 is marked as implicitly reading the 'CL' register, which it always
189 /// This method returns null if the instruction has no implicit uses.
190 const unsigned *getImplicitUses() const {
194 /// getImplicitDefs - Return a list of registers that are potentially
195 /// written by any instance of this machine instruction. For example, on X86,
196 /// many instructions implicitly set the flags register. In this case, they
197 /// are marked as setting the FLAGS. Likewise, many instructions always
198 /// deposit their result in a physical register. For example, the X86 divide
199 /// instruction always deposits the quotient and remainder in the EAX/EDX
200 /// registers. For that instruction, this will return a list containing the
201 /// EAX/EDX/EFLAGS registers.
203 /// This method returns null if the instruction has no implicit defs.
204 const unsigned *getImplicitDefs() const {
208 /// getRegClassBarriers - Return a list of register classes that are
209 /// completely clobbered by this machine instruction. For example, on X86
210 /// the call instructions will completely clobber all the registers in the
211 /// fp stack and XMM classes.
213 /// This method returns null if the instruction doesn't completely clobber
214 /// any register class.
215 const TargetRegisterClass **getRegClassBarriers() const {
219 /// getSchedClass - Return the scheduling class for this instruction. The
220 /// scheduling class is an index into the InstrItineraryData table. This
221 /// returns zero if there is no known scheduling information for the
224 unsigned getSchedClass() const {
228 bool isReturn() const {
229 return Flags & (1 << TID::Return);
232 bool isCall() const {
233 return Flags & (1 << TID::Call);
236 /// isBarrier - Returns true if the specified instruction stops control flow
237 /// from executing the instruction immediately following it. Examples include
238 /// unconditional branches and return instructions.
239 bool isBarrier() const {
240 return Flags & (1 << TID::Barrier);
243 /// isTerminator - Returns true if this instruction part of the terminator for
244 /// a basic block. Typically this is things like return and branch
247 /// Various passes use this to insert code into the bottom of a basic block,
248 /// but before control flow occurs.
249 bool isTerminator() const {
250 return Flags & (1 << TID::Terminator);
253 /// isBranch - Returns true if this is a conditional, unconditional, or
254 /// indirect branch. Predicates below can be used to discriminate between
255 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
256 /// get more information.
257 bool isBranch() const {
258 return Flags & (1 << TID::Branch);
261 /// isIndirectBranch - Return true if this is an indirect branch, such as a
262 /// branch through a register.
263 bool isIndirectBranch() const {
264 return Flags & (1 << TID::IndirectBranch);
267 /// isConditionalBranch - Return true if this is a branch which may fall
268 /// through to the next instruction or may transfer control flow to some other
269 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
270 /// information about this branch.
271 bool isConditionalBranch() const {
272 return isBranch() & !isBarrier() & !isIndirectBranch();
275 /// isUnconditionalBranch - Return true if this is a branch which always
276 /// transfers control flow to some other block. The
277 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
278 /// about this branch.
279 bool isUnconditionalBranch() const {
280 return isBranch() & isBarrier() & !isIndirectBranch();
283 // isPredicable - Return true if this instruction has a predicate operand that
284 // controls execution. It may be set to 'always', or may be set to other
285 /// values. There are various methods in TargetInstrInfo that can be used to
286 /// control and modify the predicate in this instruction.
287 bool isPredicable() const {
288 return Flags & (1 << TID::Predicable);
291 /// isNotDuplicable - Return true if this instruction cannot be safely
292 /// duplicated. For example, if the instruction has a unique labels attached
293 /// to it, duplicating it would cause multiple definition errors.
294 bool isNotDuplicable() const {
295 return Flags & (1 << TID::NotDuplicable);
298 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
299 /// which must be filled by the code generator.
300 bool hasDelaySlot() const {
301 return Flags & (1 << TID::DelaySlot);
304 /// canFoldAsLoad - Return true for instructions that can be folded as
305 /// memory operands in other instructions. The most common use for this
306 /// is instructions that are simple loads from memory that don't modify
307 /// the loaded value in any way, but it can also be used for instructions
308 /// that can be expressed as constant-pool loads, such as V_SETALLONES
309 /// on x86, to allow them to be folded when it is beneficial.
310 /// This should only be set on instructions that return a value in their
311 /// only virtual register definition.
312 bool canFoldAsLoad() const {
313 return Flags & (1 << TID::FoldableAsLoad);
316 //===--------------------------------------------------------------------===//
317 // Side Effect Analysis
318 //===--------------------------------------------------------------------===//
320 /// mayLoad - Return true if this instruction could possibly read memory.
321 /// Instructions with this flag set are not necessarily simple load
322 /// instructions, they may load a value and modify it, for example.
323 bool mayLoad() const {
324 return Flags & (1 << TID::MayLoad);
328 /// mayStore - Return true if this instruction could possibly modify memory.
329 /// Instructions with this flag set are not necessarily simple store
330 /// instructions, they may store a modified value based on their operands, or
331 /// may not actually modify anything, for example.
332 bool mayStore() const {
333 return Flags & (1 << TID::MayStore);
336 /// hasUnmodeledSideEffects - Return true if this instruction has side
337 /// effects that are not modeled by other flags. This does not return true
338 /// for instructions whose effects are captured by:
340 /// 1. Their operand list and implicit definition/use list. Register use/def
341 /// info is explicit for instructions.
342 /// 2. Memory accesses. Use mayLoad/mayStore.
343 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
345 /// Examples of side effects would be modifying 'invisible' machine state like
346 /// a control register, flushing a cache, modifying a register invisible to
349 bool hasUnmodeledSideEffects() const {
350 return Flags & (1 << TID::UnmodeledSideEffects);
353 //===--------------------------------------------------------------------===//
354 // Flags that indicate whether an instruction can be modified by a method.
355 //===--------------------------------------------------------------------===//
357 /// isCommutable - Return true if this may be a 2- or 3-address
358 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
359 /// result if Y and Z are exchanged. If this flag is set, then the
360 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
363 /// Note that this flag may be set on instructions that are only commutable
364 /// sometimes. In these cases, the call to commuteInstruction will fail.
365 /// Also note that some instructions require non-trivial modification to
367 bool isCommutable() const {
368 return Flags & (1 << TID::Commutable);
371 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
372 /// which can be changed into a 3-address instruction if needed. Doing this
373 /// transformation can be profitable in the register allocator, because it
374 /// means that the instruction can use a 2-address form if possible, but
375 /// degrade into a less efficient form if the source and dest register cannot
376 /// be assigned to the same register. For example, this allows the x86
377 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
378 /// is the same speed as the shift but has bigger code size.
380 /// If this returns true, then the target must implement the
381 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
382 /// is allowed to fail if the transformation isn't valid for this specific
383 /// instruction (e.g. shl reg, 4 on x86).
385 bool isConvertibleTo3Addr() const {
386 return Flags & (1 << TID::ConvertibleTo3Addr);
389 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
390 /// custom insertion support when the DAG scheduler is inserting it into a
391 /// machine basic block. If this is true for the instruction, it basically
392 /// means that it is a pseudo instruction used at SelectionDAG time that is
393 /// expanded out into magic code by the target when MachineInstrs are formed.
395 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
396 /// is used to insert this into the MachineBasicBlock.
397 bool usesCustomDAGSchedInsertionHook() const {
398 return Flags & (1 << TID::UsesCustomDAGSchedInserter);
401 /// isRematerializable - Returns true if this instruction is a candidate for
402 /// remat. This flag is deprecated, please don't use it anymore. If this
403 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
404 /// verify the instruction is really rematable.
405 bool isRematerializable() const {
406 return Flags & (1 << TID::Rematerializable);
409 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
410 /// less) than a move instruction. This is useful during certain types of
411 /// rematerializations (e.g., during two-address conversion) where we would
412 /// like to remat the instruction, but not if it costs more than moving the
413 /// instruction into the appropriate register.
414 bool isAsCheapAsAMove() const {
415 return Flags & (1 << TID::CheapAsAMove);
419 } // end namespace llvm