1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints: only "tied_to" for now.
28 enum OperandConstraint {
29 TIED_TO = 0 // Must be allocated the same register as.
32 /// OperandFlags - These are flags set on operands, but should be considered
33 /// private, all access should go through the TargetOperandInfo accessors.
34 /// See the accessors for a description of what these are.
36 LookupPtrRegClass = 0,
42 /// TargetOperandInfo - This holds information about one operand of a machine
43 /// instruction, indicating the register class for register operands, etc.
45 class TargetOperandInfo {
47 /// RegClass - This specifies the register class enumeration of the operand
48 /// if the operand is a register. If not, this contains 0.
49 unsigned short RegClass;
51 /// Lower 16 bits are used to specify which constraints are set. The higher 16
52 /// bits are used to specify the value of constraints (4 bits each).
53 unsigned int Constraints;
54 /// Currently no other information.
56 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
57 /// requires a callback to look up its register class.
58 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
60 /// isPredicate - Set if this is one of the operands that made up of
61 /// the predicate operand that controls an isPredicable() instruction.
62 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
64 /// isOptionalDef - Set if this operand is a optional def.
66 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
70 //===----------------------------------------------------------------------===//
71 // Machine Instruction Flags and Description
72 //===----------------------------------------------------------------------===//
74 /// TargetInstrDesc flags - These should be considered private to the
75 /// implementation of the TargetInstrDesc class. Clients should use the
76 /// predicate methods on TargetInstrDesc, not use these directly. These
77 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
98 UsesCustomDAGSchedInserter,
103 /// TargetInstrDesc - Describe properties that are true of each
104 /// instruction in the target description file. This captures information about
105 /// side effects, register use and many other things. There is one instance of
106 /// this struct for each target instruction class, and the MachineInstr class
107 /// points to this struct directly to describe itself.
108 class TargetInstrDesc {
110 unsigned short Opcode; // The opcode number.
111 unsigned short NumOperands; // Num of args (may be more if variable_ops)
112 unsigned short NumDefs; // Num of args that are definitions.
113 unsigned short SchedClass; // enum identifying instr sched class
114 const char * Name; // Name of the instruction record in td file.
115 unsigned Flags; // flags identifying machine instr class
116 unsigned TSFlags; // Target Specific Flag values
117 const unsigned *ImplicitUses; // Registers implicitly read by this instr
118 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
119 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands.
121 /// getOperandConstraint - Returns the value of the specific constraint if
122 /// it is set. Returns -1 if it is not set.
123 int getOperandConstraint(unsigned OpNum,
124 TOI::OperandConstraint Constraint) const {
125 assert((OpNum < NumOperands || isVariadic()) &&
126 "Invalid operand # of TargetInstrInfo");
127 if (OpNum < NumOperands &&
128 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
129 unsigned Pos = 16 + Constraint * 4;
130 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
135 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
136 /// dest operand. Returns -1 if there isn't one.
137 int findTiedToSrcOperand(unsigned OpNum) const;
139 /// getOpcode - Return the opcode number for this descriptor.
140 unsigned getOpcode() const {
144 /// getName - Return the name of the record in the .td file for this
145 /// instruction, for example "ADD8ri".
146 const char *getName() const {
150 /// getNumOperands - Return the number of declared MachineOperands for this
151 /// MachineInstruction. Note that variadic (isVariadic() returns true)
152 /// instructions may have additional operands at the end of the list, and note
153 /// that the machine instruction may include implicit register def/uses as
155 unsigned getNumOperands() const {
159 /// getNumDefs - Return the number of MachineOperands that are register
160 /// definitions. Register definitions always occur at the start of the
161 /// machine operand list. This is the number of "outs" in the .td file.
162 unsigned getNumDefs() const {
166 /// isVariadic - Return true if this instruction can have a variable number of
167 /// operands. In this case, the variable operands will be after the normal
168 /// operands but before the implicit definitions and uses (if any are
170 bool isVariadic() const {
171 return Flags & (1 << TID::Variadic);
174 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
175 /// ARM instructions which can set condition code if 's' bit is set.
176 bool hasOptionalDef() const {
177 return Flags & (1 << TID::HasOptionalDef);
180 /// getImplicitUses - Return a list of machine operands that are potentially
181 /// read by any instance of this machine instruction. For example, on X86,
182 /// the "adc" instruction adds two register operands and adds the carry bit in
183 /// from the flags register. In this case, the instruction is marked as
184 /// implicitly reading the flags. Likewise, the variable shift instruction on
185 /// X86 is marked as implicitly reading the 'CL' register, which it always
188 /// This method returns null if the instruction has no implicit uses.
189 const unsigned *getImplicitUses() const {
193 /// getImplicitDefs - Return a list of machine operands that are potentially
194 /// written by any instance of this machine instruction. For example, on X86,
195 /// many instructions implicitly set the flags register. In this case, they
196 /// are marked as setting the FLAGS. Likewise, many instructions always
197 /// deposit their result in a physical register. For example, the X86 divide
198 /// instruction always deposits the quotient and remainder in the EAX/EDX
199 /// registers. For that instruction, this will return a list containing the
200 /// EAX/EDX/EFLAGS registers.
202 /// This method returns null if the instruction has no implicit uses.
203 const unsigned *getImplicitDefs() const {
207 /// getSchedClass - Return the scheduling class for this instruction. The
208 /// scheduling class is an index into the InstrItineraryData table. This
209 /// returns zero if there is no known scheduling information for the
212 unsigned getSchedClass() const {
216 bool isReturn() const {
217 return Flags & (1 << TID::Return);
220 bool isCall() const {
221 return Flags & (1 << TID::Call);
224 /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
225 /// which defines a register to an unspecified value. These basically
226 /// correspond to x = undef.
227 bool isImplicitDef() const {
228 return Flags & (1 << TID::ImplicitDef);
231 /// isBarrier - Returns true if the specified instruction stops control flow
232 /// from executing the instruction immediately following it. Examples include
233 /// unconditional branches and return instructions.
234 bool isBarrier() const {
235 return Flags & (1 << TID::Barrier);
238 /// isTerminator - Returns true if this instruction part of the terminator for
239 /// a basic block. Typically this is things like return and branch
242 /// Various passes use this to insert code into the bottom of a basic block,
243 /// but before control flow occurs.
244 bool isTerminator() const {
245 return Flags & (1 << TID::Terminator);
248 /// isBranch - Returns true if this is a conditional, unconditional, or
249 /// indirect branch. Predicates below can be used to discriminate between
250 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
251 /// get more information.
252 bool isBranch() const {
253 return Flags & (1 << TID::Branch);
256 /// isIndirectBranch - Return true if this is an indirect branch, such as a
257 /// branch through a register.
258 bool isIndirectBranch() const {
259 return Flags & (1 << TID::IndirectBranch);
262 /// isConditionalBranch - Return true if this is a branch which may fall
263 /// through to the next instruction or may transfer control flow to some other
264 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
265 /// information about this branch.
266 bool isConditionalBranch() const {
267 return isBranch() & !isBarrier() & !isIndirectBranch();
270 /// isUnconditionalBranch - Return true if this is a branch which always
271 /// transfers control flow to some other block. The
272 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
273 /// about this branch.
274 bool isUnconditionalBranch() const {
275 return isBranch() & isBarrier() & !isIndirectBranch();
278 // isPredicable - Return true if this instruction has a predicate operand that
279 // controls execution. It may be set to 'always', or may be set to other
280 /// values. There are various methods in TargetInstrInfo that can be used to
281 /// control and modify the predicate in this instruction.
282 bool isPredicable() const {
283 return Flags & (1 << TID::Predicable);
286 /// isNotDuplicable - Return true if this instruction cannot be safely
287 /// duplicated. For example, if the instruction has a unique labels attached
288 /// to it, duplicating it would cause multiple definition errors.
289 bool isNotDuplicable() const {
290 return Flags & (1 << TID::NotDuplicable);
293 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
294 /// which must be filled by the code generator.
295 bool hasDelaySlot() const {
296 return Flags & (1 << TID::DelaySlot);
299 /// isSimpleLoad - Return true for instructions that are simple loads from
300 /// memory. This should only be set on instructions that load a value from
301 /// memory and return it in their only virtual register definition.
302 /// Instructions that return a value loaded from memory and then modified in
303 /// some way should not return true for this.
304 bool isSimpleLoad() const {
305 return Flags & (1 << TID::SimpleLoad);
308 //===--------------------------------------------------------------------===//
309 // Side Effect Analysis
310 //===--------------------------------------------------------------------===//
312 /// mayStore - Return true if this instruction could possibly modify memory.
313 /// Instructions with this flag set are not necessarily simple store
314 /// instructions, they may store a modified value based on their operands, or
315 /// may not actually modify anything, for example.
316 bool mayStore() const {
317 return Flags & (1 << TID::MayStore);
322 /// hasNoSideEffects - Return true if all instances of this instruction are
323 /// guaranteed to have no side effects other than:
324 /// 1. The register operands that are def/used by the MachineInstr.
325 /// 2. Registers that are implicitly def/used by the MachineInstr.
326 /// 3. Memory Accesses captured by mayLoad() or mayStore().
328 /// Examples of other side effects would be calling a function, modifying
329 /// 'invisible' machine state like a control register, etc.
331 /// If some instances of this instruction are side-effect free but others are
332 /// not, the hasConditionalSideEffects() property should return true, not this
335 /// Note that you should not call this method directly, instead, call the
336 /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
337 /// of the machine instruction.
338 bool hasNoSideEffects() const {
339 return Flags & (1 << TID::NeverHasSideEffects);
342 /// hasConditionalSideEffects - Return true if some instances of this
343 /// instruction are guaranteed to have no side effects other than those listed
344 /// for hasNoSideEffects(). To determine whether a specific machineinstr has
345 /// side effects, the TargetInstrInfo::isReallySideEffectFree virtual method
346 /// is invoked to decide.
348 /// Note that you should not call this method directly, instead, call the
349 /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis
350 /// of the machine instruction.
351 bool hasConditionalSideEffects() const {
352 return Flags & (1 << TID::MayHaveSideEffects);
355 //===--------------------------------------------------------------------===//
356 // Flags that indicate whether an instruction can be modified by a method.
357 //===--------------------------------------------------------------------===//
359 /// isCommutable - Return true if this may be a 2- or 3-address
360 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
361 /// result if Y and Z are exchanged. If this flag is set, then the
362 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
365 /// Note that this flag may be set on instructions that are only commutable
366 /// sometimes. In these cases, the call to commuteInstruction will fail.
367 /// Also note that some instructions require non-trivial modification to
369 bool isCommutable() const {
370 return Flags & (1 << TID::Commutable);
373 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
374 /// which can be changed into a 3-address instruction if needed. Doing this
375 /// transformation can be profitable in the register allocator, because it
376 /// means that the instruction can use a 2-address form if possible, but
377 /// degrade into a less efficient form if the source and dest register cannot
378 /// be assigned to the same register. For example, this allows the x86
379 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
380 /// is the same speed as the shift but has bigger code size.
382 /// If this returns true, then the target must implement the
383 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
384 /// is allowed to fail if the transformation isn't valid for this specific
385 /// instruction (e.g. shl reg, 4 on x86).
387 bool isConvertibleTo3Addr() const {
388 return Flags & (1 << TID::ConvertibleTo3Addr);
391 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
392 /// custom insertion support when the DAG scheduler is inserting it into a
393 /// machine basic block. If this is true for the instruction, it basically
394 /// means that it is a pseudo instruction used at SelectionDAG time that is
395 /// expanded out into magic code by the target when MachineInstrs are formed.
397 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
398 /// is used to insert this into the MachineBasicBlock.
399 bool usesCustomDAGSchedInsertionHook() const {
400 return Flags & (1 << TID::UsesCustomDAGSchedInserter);
403 /// isRematerializable - Returns true if this instruction is a candidate for
404 /// remat. This flag is deprecated, please don't use it anymore. If this
405 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
406 /// verify the instruction is really rematable.
407 bool isRematerializable() const {
408 return Flags & (1 << TID::Rematerializable);
412 } // end namespace llvm