1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class TargetRegisterClass;
24 class CalleeSavedInfo;
28 template<class T> class SmallVectorImpl;
31 //---------------------------------------------------------------------------
33 /// TargetInstrInfo - Interface to description of machine instructions
35 class TargetInstrInfo {
36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
37 unsigned NumOpcodes; // Number of entries in the desc array
39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
43 virtual ~TargetInstrInfo();
45 // Invariant opcodes: All instruction sets have these as their low opcodes.
57 unsigned getNumOpcodes() const { return NumOpcodes; }
59 /// get - Return the machine instruction descriptor that corresponds to the
60 /// specified instruction opcode.
62 const TargetInstrDesc &get(unsigned Opcode) const {
63 assert(Opcode < NumOpcodes && "Invalid opcode!");
64 return Descriptors[Opcode];
67 /// isTriviallyReMaterializable - Return true if the instruction is trivially
68 /// rematerializable, meaning it has no side effects and requires no operands
69 /// that aren't always available.
70 bool isTriviallyReMaterializable(MachineInstr *MI) const {
71 return MI->getDesc().isRematerializable() &&
72 isReallyTriviallyReMaterializable(MI);
76 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
77 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
78 /// instruction itself is actually trivially rematerializable, considering
79 /// its operands. This is used for targets that have instructions that are
80 /// only trivially rematerializable for specific uses. This predicate must
81 /// return false if the instruction has any side effects other than
82 /// producing a value, or if it requres any address registers that are not
84 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
89 /// Return true if the instruction is a register to register move
90 /// and leave the source and dest operands in the passed parameters.
91 virtual bool isMoveInstr(const MachineInstr& MI,
93 unsigned& destReg) const {
97 /// isLoadFromStackSlot - If the specified machine instruction is a direct
98 /// load from a stack slot, return the virtual or physical register number of
99 /// the destination along with the FrameIndex of the loaded stack slot. If
100 /// not, return 0. This predicate must return 0 if the instruction has
101 /// any side effects other than loading from the stack slot.
102 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
106 /// isStoreToStackSlot - If the specified machine instruction is a direct
107 /// store to a stack slot, return the virtual or physical register number of
108 /// the source reg along with the FrameIndex of the loaded stack slot. If
109 /// not, return 0. This predicate must return 0 if the instruction has
110 /// any side effects other than storing to the stack slot.
111 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
115 /// isInvariantLoad - Return true if the specified instruction (which is
116 /// marked mayLoad) is loading from a location whose value is invariant across
117 /// the function. For example, loading a value from the constant pool or from
118 /// from the argument area of a function if it does not change. This should
119 /// only return true of *all* loads the instruction does are invariant (if it
120 /// does multiple loads).
121 virtual bool isInvariantLoad(MachineInstr *MI) const {
125 /// convertToThreeAddress - This method must be implemented by targets that
126 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
127 /// may be able to convert a two-address instruction into one or more true
128 /// three-address instructions on demand. This allows the X86 target (for
129 /// example) to convert ADD and SHL instructions into LEA instructions if they
130 /// would require register copies due to two-addressness.
132 /// This method returns a null pointer if the transformation cannot be
133 /// performed, otherwise it returns the last new instruction.
135 virtual MachineInstr *
136 convertToThreeAddress(MachineFunction::iterator &MFI,
137 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
141 /// commuteInstruction - If a target has any instructions that are commutable,
142 /// but require converting to a different instruction or making non-trivial
143 /// changes to commute them, this method can overloaded to do this. The
144 /// default implementation of this method simply swaps the first two operands
145 /// of MI and returns it.
147 /// If a target wants to make more aggressive changes, they can construct and
148 /// return a new machine instruction. If an instruction cannot commute, it
149 /// can also return null.
151 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
153 /// CommuteChangesDestination - Return true if commuting the specified
154 /// instruction will also changes the destination operand. Also return the
155 /// current operand index of the would be new destination register by
156 /// reference. This can happen when the commutable instruction is also a
157 /// two-address instruction.
158 virtual bool CommuteChangesDestination(MachineInstr *MI,
159 unsigned &OpIdx) const = 0;
161 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
162 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
163 /// implemented for a target). Upon success, this returns false and returns
164 /// with the following information in various cases:
166 /// 1. If this block ends with no branches (it just falls through to its succ)
167 /// just return false, leaving TBB/FBB null.
168 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
169 /// the destination block.
170 /// 3. If this block ends with an conditional branch and it falls through to
171 /// an successor block, it sets TBB to be the branch destination block and a
172 /// list of operands that evaluate the condition. These
173 /// operands can be passed to other TargetInstrInfo methods to create new
175 /// 4. If this block ends with an conditional branch and an unconditional
176 /// block, it returns the 'true' destination in TBB, the 'false' destination
177 /// in FBB, and a list of operands that evaluate the condition. These
178 /// operands can be passed to other TargetInstrInfo methods to create new
181 /// Note that RemoveBranch and InsertBranch must be implemented to support
182 /// cases where this method returns success.
184 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
185 MachineBasicBlock *&FBB,
186 std::vector<MachineOperand> &Cond) const {
190 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
191 /// this is only invoked in cases where AnalyzeBranch returns success. It
192 /// returns the number of instructions that were removed.
193 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
194 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
198 /// InsertBranch - Insert a branch into the end of the specified
199 /// MachineBasicBlock. This operands to this method are the same as those
200 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
201 /// returns success and when an unconditional branch (TBB is non-null, FBB is
202 /// null, Cond is empty) needs to be inserted. It returns the number of
203 /// instructions inserted.
204 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
205 MachineBasicBlock *FBB,
206 const std::vector<MachineOperand> &Cond) const {
207 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
211 /// copyRegToReg - Add a copy between a pair of registers
212 virtual void copyRegToReg(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator MI,
214 unsigned DestReg, unsigned SrcReg,
215 const TargetRegisterClass *DestRC,
216 const TargetRegisterClass *SrcRC) const {
217 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
220 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator MI,
222 unsigned SrcReg, bool isKill, int FrameIndex,
223 const TargetRegisterClass *RC) const {
224 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
227 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
228 SmallVectorImpl<MachineOperand> &Addr,
229 const TargetRegisterClass *RC,
230 SmallVectorImpl<MachineInstr*> &NewMIs) const {
231 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
234 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
235 MachineBasicBlock::iterator MI,
236 unsigned DestReg, int FrameIndex,
237 const TargetRegisterClass *RC) const {
238 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
241 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
242 SmallVectorImpl<MachineOperand> &Addr,
243 const TargetRegisterClass *RC,
244 SmallVectorImpl<MachineInstr*> &NewMIs) const {
245 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
248 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
249 /// saved registers and returns true if it isn't possible / profitable to do
250 /// so by issuing a series of store instructions via
251 /// storeRegToStackSlot(). Returns false otherwise.
252 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator MI,
254 const std::vector<CalleeSavedInfo> &CSI) const {
258 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
259 /// saved registers and returns true if it isn't possible / profitable to do
260 /// so by issuing a series of load instructions via loadRegToStackSlot().
261 /// Returns false otherwise.
262 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
263 MachineBasicBlock::iterator MI,
264 const std::vector<CalleeSavedInfo> &CSI) const {
268 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
269 /// slot into the specified machine instruction for the specified operand(s).
270 /// If this is possible, a new instruction is returned with the specified
271 /// operand folded, otherwise NULL is returned. The client is responsible for
272 /// removing the old instruction and adding the new one in the instruction
274 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
276 SmallVectorImpl<unsigned> &Ops,
277 int FrameIndex) const {
281 /// foldMemoryOperand - Same as the previous version except it allows folding
282 /// of any load and store from / to any address, not just from a specific
284 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
286 SmallVectorImpl<unsigned> &Ops,
287 MachineInstr* LoadMI) const {
291 /// canFoldMemoryOperand - Returns true if the specified load / store is
292 /// folding is possible.
294 bool canFoldMemoryOperand(MachineInstr *MI,
295 SmallVectorImpl<unsigned> &Ops) const{
299 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
300 /// a store or a load and a store into two or more instruction. If this is
301 /// possible, returns true as well as the new instructions by reference.
302 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
303 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
304 SmallVectorImpl<MachineInstr*> &NewMIs) const{
308 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
309 SmallVectorImpl<SDNode*> &NewNodes) const {
313 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
314 /// instruction after load / store are unfolded from an instruction of the
315 /// specified opcode. It returns zero if the specified unfolding is not
317 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
318 bool UnfoldLoad, bool UnfoldStore) const {
322 /// BlockHasNoFallThrough - Return true if the specified block does not
323 /// fall-through into its successor block. This is primarily used when a
324 /// branch is unanalyzable. It is useful for things like unconditional
325 /// indirect branches (jump tables).
326 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
330 /// ReverseBranchCondition - Reverses the branch condition of the specified
331 /// condition list, returning false on success and true if it cannot be
333 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
337 /// insertNoop - Insert a noop into the instruction stream at the specified
339 virtual void insertNoop(MachineBasicBlock &MBB,
340 MachineBasicBlock::iterator MI) const {
341 assert(0 && "Target didn't implement insertNoop!");
345 /// isPredicated - Returns true if the instruction is already predicated.
347 virtual bool isPredicated(const MachineInstr *MI) const {
351 /// isUnpredicatedTerminator - Returns true if the instruction is a
352 /// terminator instruction that has not been predicated.
353 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
355 /// PredicateInstruction - Convert the instruction into a predicated
356 /// instruction. It returns true if the operation was successful.
358 bool PredicateInstruction(MachineInstr *MI,
359 const std::vector<MachineOperand> &Pred) const = 0;
361 /// SubsumesPredicate - Returns true if the first specified predicate
362 /// subsumes the second, e.g. GE subsumes GT.
364 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
365 const std::vector<MachineOperand> &Pred2) const {
369 /// DefinesPredicate - If the specified instruction defines any predicate
370 /// or condition code register(s) used for predication, returns true as well
371 /// as the definition predicate(s) by reference.
372 virtual bool DefinesPredicate(MachineInstr *MI,
373 std::vector<MachineOperand> &Pred) const {
377 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
379 virtual const TargetRegisterClass *getPointerRegClass() const {
380 assert(0 && "Target didn't implement getPointerRegClass!");
382 return 0; // Must return a value in order to compile with VS 2005
386 /// TargetInstrInfoImpl - This is the default implementation of
387 /// TargetInstrInfo, which just provides a couple of default implementations
388 /// for various methods. This separated out because it is implemented in
389 /// libcodegen, not in libtarget.
390 class TargetInstrInfoImpl : public TargetInstrInfo {
392 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
393 : TargetInstrInfo(desc, NumOpcodes) {}
395 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
396 virtual bool CommuteChangesDestination(MachineInstr *MI,
397 unsigned &OpIdx) const;
398 virtual bool PredicateInstruction(MachineInstr *MI,
399 const std::vector<MachineOperand> &Pred) const;
403 } // End llvm namespace