1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/BranchProbability.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
27 class InstrItineraryData;
30 class MachineMemOperand;
31 class MachineRegisterInfo;
35 class MCSymbolRefExpr;
37 class ScheduleHazardRecognizer;
40 class TargetRegisterClass;
41 class TargetRegisterInfo;
42 class TargetSubtargetInfo;
43 class TargetSchedModel;
46 template<class T> class SmallVectorImpl;
49 //---------------------------------------------------------------------------
51 /// TargetInstrInfo - Interface to description of machine instruction set
53 class TargetInstrInfo : public MCInstrInfo {
54 TargetInstrInfo(const TargetInstrInfo &) = delete;
55 void operator=(const TargetInstrInfo &) = delete;
57 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
58 unsigned CatchRetOpcode = ~0u)
59 : CallFrameSetupOpcode(CFSetupOpcode),
60 CallFrameDestroyOpcode(CFDestroyOpcode),
61 CatchRetOpcode(CatchRetOpcode) {}
63 virtual ~TargetInstrInfo();
65 static bool isGenericOpcode(unsigned Opc) {
66 return Opc <= TargetOpcode::GENERIC_OP_END;
69 /// Given a machine instruction descriptor, returns the register
70 /// class constraint for OpNum, or NULL.
71 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
73 const TargetRegisterInfo *TRI,
74 const MachineFunction &MF) const;
76 /// Return true if the instruction is trivially rematerializable, meaning it
77 /// has no side effects and requires no operands that aren't always available.
78 /// This means the only allowed uses are constants and unallocatable physical
79 /// registers so that the instructions result is independent of the place
81 bool isTriviallyReMaterializable(const MachineInstr *MI,
82 AliasAnalysis *AA = nullptr) const {
83 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
84 (MI->getDesc().isRematerializable() &&
85 (isReallyTriviallyReMaterializable(MI, AA) ||
86 isReallyTriviallyReMaterializableGeneric(MI, AA)));
90 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
91 /// set, this hook lets the target specify whether the instruction is actually
92 /// trivially rematerializable, taking into consideration its operands. This
93 /// predicate must return false if the instruction has any side effects other
94 /// than producing a value, or if it requres any address registers that are
95 /// not always available.
96 /// Requirements must be check as stated in isTriviallyReMaterializable() .
97 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
98 AliasAnalysis *AA) const {
102 /// This method commutes the operands of the given machine instruction MI.
103 /// The operands to be commuted are specified by their indices OpIdx1 and
106 /// If a target has any instructions that are commutable but require
107 /// converting to different instructions or making non-trivial changes
108 /// to commute them, this method can be overloaded to do that.
109 /// The default implementation simply swaps the commutable operands.
111 /// If NewMI is false, MI is modified in place and returned; otherwise, a
112 /// new machine instruction is created and returned.
114 /// Do not call this method for a non-commutable instruction.
115 /// Even though the instruction is commutable, the method may still
116 /// fail to commute the operands, null pointer is returned in such cases.
117 virtual MachineInstr *commuteInstructionImpl(MachineInstr *MI,
120 unsigned OpIdx2) const;
122 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
123 /// operand indices to (ResultIdx1, ResultIdx2).
124 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
125 /// predefined to some indices or be undefined (designated by the special
126 /// value 'CommuteAnyOperandIndex').
127 /// The predefined result indices cannot be re-defined.
128 /// The function returns true iff after the result pair redefinition
129 /// the fixed result pair is equal to or equivalent to the source pair of
130 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
131 /// the pairs (x,y) and (y,x) are equivalent.
132 static bool fixCommutedOpIndices(unsigned &ResultIdx1,
133 unsigned &ResultIdx2,
134 unsigned CommutableOpIdx1,
135 unsigned CommutableOpIdx2);
138 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
139 /// set and the target hook isReallyTriviallyReMaterializable returns false,
140 /// this function does target-independent tests to determine if the
141 /// instruction is really trivially rematerializable.
142 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
143 AliasAnalysis *AA) const;
146 /// These methods return the opcode of the frame setup/destroy instructions
147 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
148 /// order to abstract away the difference between operating with a frame
149 /// pointer and operating without, through the use of these two instructions.
151 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
152 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
154 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
156 /// Returns the actual stack pointer adjustment made by an instruction
157 /// as part of a call sequence. By default, only call frame setup/destroy
158 /// instructions adjust the stack, but targets may want to override this
159 /// to enable more fine-grained adjustment, or adjust by a different value.
160 virtual int getSPAdjust(const MachineInstr *MI) const;
162 /// Return true if the instruction is a "coalescable" extension instruction.
163 /// That is, it's like a copy where it's legal for the source to overlap the
164 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
165 /// expected the pre-extension value is available as a subreg of the result
166 /// register. This also returns the sub-register index in SubIdx.
167 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
168 unsigned &SrcReg, unsigned &DstReg,
169 unsigned &SubIdx) const {
173 /// If the specified machine instruction is a direct
174 /// load from a stack slot, return the virtual or physical register number of
175 /// the destination along with the FrameIndex of the loaded stack slot. If
176 /// not, return 0. This predicate must return 0 if the instruction has
177 /// any side effects other than loading from the stack slot.
178 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
179 int &FrameIndex) const {
183 /// Check for post-frame ptr elimination stack locations as well.
184 /// This uses a heuristic so it isn't reliable for correctness.
185 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
186 int &FrameIndex) const {
190 /// If the specified machine instruction has a load from a stack slot,
191 /// return true along with the FrameIndex of the loaded stack slot and the
192 /// machine mem operand containing the reference.
193 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
194 /// any instructions that loads from the stack. This is just a hint, as some
195 /// cases may be missed.
196 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
197 const MachineMemOperand *&MMO,
198 int &FrameIndex) const;
200 /// If the specified machine instruction is a direct
201 /// store to a stack slot, return the virtual or physical register number of
202 /// the source reg along with the FrameIndex of the loaded stack slot. If
203 /// not, return 0. This predicate must return 0 if the instruction has
204 /// any side effects other than storing to the stack slot.
205 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
206 int &FrameIndex) const {
210 /// Check for post-frame ptr elimination stack locations as well.
211 /// This uses a heuristic, so it isn't reliable for correctness.
212 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
213 int &FrameIndex) const {
217 /// If the specified machine instruction has a store to a stack slot,
218 /// return true along with the FrameIndex of the loaded stack slot and the
219 /// machine mem operand containing the reference.
220 /// If not, return false. Unlike isStoreToStackSlot,
221 /// this returns true for any instructions that stores to the
222 /// stack. This is just a hint, as some cases may be missed.
223 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
224 const MachineMemOperand *&MMO,
225 int &FrameIndex) const;
227 /// Return true if the specified machine instruction
228 /// is a copy of one stack slot to another and has no other effect.
229 /// Provide the identity of the two frame indices.
230 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
231 int &SrcFrameIndex) const {
235 /// Compute the size in bytes and offset within a stack slot of a spilled
236 /// register or subregister.
238 /// \param [out] Size in bytes of the spilled value.
239 /// \param [out] Offset in bytes within the stack slot.
240 /// \returns true if both Size and Offset are successfully computed.
242 /// Not all subregisters have computable spill slots. For example,
243 /// subregisters registers may not be byte-sized, and a pair of discontiguous
244 /// subregisters has no single offset.
246 /// Targets with nontrivial bigendian implementations may need to override
247 /// this, particularly to support spilled vector registers.
248 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
249 unsigned &Size, unsigned &Offset,
250 const MachineFunction &MF) const;
252 /// Return true if the instruction is as cheap as a move instruction.
254 /// Targets for different archs need to override this, and different
255 /// micro-architectures can also be finely tuned inside.
256 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const {
257 return MI->isAsCheapAsAMove();
260 /// Re-issue the specified 'original' instruction at the
261 /// specific location targeting a new destination register.
262 /// The register in Orig->getOperand(0).getReg() will be substituted by
263 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
265 virtual void reMaterialize(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator MI,
267 unsigned DestReg, unsigned SubIdx,
268 const MachineInstr *Orig,
269 const TargetRegisterInfo &TRI) const;
271 /// Create a duplicate of the Orig instruction in MF. This is like
272 /// MachineFunction::CloneMachineInstr(), but the target may update operands
273 /// that are required to be unique.
275 /// The instruction must be duplicable as indicated by isNotDuplicable().
276 virtual MachineInstr *duplicate(MachineInstr *Orig,
277 MachineFunction &MF) const;
279 /// This method must be implemented by targets that
280 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
281 /// may be able to convert a two-address instruction into one or more true
282 /// three-address instructions on demand. This allows the X86 target (for
283 /// example) to convert ADD and SHL instructions into LEA instructions if they
284 /// would require register copies due to two-addressness.
286 /// This method returns a null pointer if the transformation cannot be
287 /// performed, otherwise it returns the last new instruction.
289 virtual MachineInstr *
290 convertToThreeAddress(MachineFunction::iterator &MFI,
291 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
295 // This constant can be used as an input value of operand index passed to
296 // the method findCommutedOpIndices() to tell the method that the
297 // corresponding operand index is not pre-defined and that the method
298 // can pick any commutable operand.
299 static const unsigned CommuteAnyOperandIndex = ~0U;
301 /// This method commutes the operands of the given machine instruction MI.
303 /// The operands to be commuted are specified by their indices OpIdx1 and
304 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
305 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
306 /// any arbitrarily chosen commutable operand. If both arguments are set to
307 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
308 /// operands; then commutes them if such operands could be found.
310 /// If NewMI is false, MI is modified in place and returned; otherwise, a
311 /// new machine instruction is created and returned.
313 /// Do not call this method for a non-commutable instruction or
314 /// for non-commuable operands.
315 /// Even though the instruction is commutable, the method may still
316 /// fail to commute the operands, null pointer is returned in such cases.
318 commuteInstruction(MachineInstr *MI,
320 unsigned OpIdx1 = CommuteAnyOperandIndex,
321 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
323 /// Returns true iff the routine could find two commutable operands in the
324 /// given machine instruction.
325 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
326 /// If any of the INPUT values is set to the special value
327 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
328 /// operand, then returns its index in the corresponding argument.
329 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
330 /// looks for 2 commutable operands.
331 /// If INPUT values refer to some operands of MI, then the method simply
332 /// returns true if the corresponding operands are commutable and returns
335 /// For example, calling this method this way:
336 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
337 /// findCommutedOpIndices(MI, Op1, Op2);
338 /// can be interpreted as a query asking to find an operand that would be
339 /// commutable with the operand#1.
340 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
341 unsigned &SrcOpIdx2) const;
343 /// A pair composed of a register and a sub-register index.
344 /// Used to give some type checking when modeling Reg:SubReg.
345 struct RegSubRegPair {
348 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
349 : Reg(Reg), SubReg(SubReg) {}
351 /// A pair composed of a pair of a register and a sub-register index,
352 /// and another sub-register index.
353 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
354 struct RegSubRegPairAndIdx : RegSubRegPair {
356 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
358 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
361 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
363 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
364 /// the list is modeled as <Reg:SubReg, SubIdx>.
365 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
367 /// - vreg1:sub1, sub0
368 /// - vreg2<:0>, sub1
370 /// \returns true if it is possible to build such an input sequence
371 /// with the pair \p MI, \p DefIdx. False otherwise.
373 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
375 /// \note The generic implementation does not provide any support for
376 /// MI.isRegSequenceLike(). In other words, one has to override
377 /// getRegSequenceLikeInputs for target specific instructions.
379 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
380 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
382 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
384 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
385 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
386 /// - vreg1:sub1, sub0
388 /// \returns true if it is possible to build such an input sequence
389 /// with the pair \p MI, \p DefIdx. False otherwise.
391 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
393 /// \note The generic implementation does not provide any support for
394 /// MI.isExtractSubregLike(). In other words, one has to override
395 /// getExtractSubregLikeInputs for target specific instructions.
397 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
398 RegSubRegPairAndIdx &InputReg) const;
400 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
402 /// \p [out] BaseReg and \p [out] InsertedReg contain
403 /// the equivalent inputs of INSERT_SUBREG.
404 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
405 /// - BaseReg: vreg0:sub0
406 /// - InsertedReg: vreg1:sub1, sub3
408 /// \returns true if it is possible to build such an input sequence
409 /// with the pair \p MI, \p DefIdx. False otherwise.
411 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
413 /// \note The generic implementation does not provide any support for
414 /// MI.isInsertSubregLike(). In other words, one has to override
415 /// getInsertSubregLikeInputs for target specific instructions.
417 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
418 RegSubRegPair &BaseReg,
419 RegSubRegPairAndIdx &InsertedReg) const;
422 /// Return true if two machine instructions would produce identical values.
423 /// By default, this is only true when the two instructions
424 /// are deemed identical except for defs. If this function is called when the
425 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
426 /// aggressive checks.
427 virtual bool produceSameValue(const MachineInstr *MI0,
428 const MachineInstr *MI1,
429 const MachineRegisterInfo *MRI = nullptr) const;
431 /// Analyze the branching code at the end of MBB, returning
432 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
433 /// implemented for a target). Upon success, this returns false and returns
434 /// with the following information in various cases:
436 /// 1. If this block ends with no branches (it just falls through to its succ)
437 /// just return false, leaving TBB/FBB null.
438 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
439 /// the destination block.
440 /// 3. If this block ends with a conditional branch and it falls through to a
441 /// successor block, it sets TBB to be the branch destination block and a
442 /// list of operands that evaluate the condition. These operands can be
443 /// passed to other TargetInstrInfo methods to create new branches.
444 /// 4. If this block ends with a conditional branch followed by an
445 /// unconditional branch, it returns the 'true' destination in TBB, the
446 /// 'false' destination in FBB, and a list of operands that evaluate the
447 /// condition. These operands can be passed to other TargetInstrInfo
448 /// methods to create new branches.
450 /// Note that RemoveBranch and InsertBranch must be implemented to support
451 /// cases where this method returns success.
453 /// If AllowModify is true, then this routine is allowed to modify the basic
454 /// block (e.g. delete instructions after the unconditional branch).
456 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
457 MachineBasicBlock *&FBB,
458 SmallVectorImpl<MachineOperand> &Cond,
459 bool AllowModify = false) const {
463 /// Represents a predicate at the MachineFunction level. The control flow a
464 /// MachineBranchPredicate represents is:
466 /// Reg <def>= LHS `Predicate` RHS == ConditionDef
467 /// if Reg then goto TrueDest else goto FalseDest
469 struct MachineBranchPredicate {
470 enum ComparePredicate {
471 PRED_EQ, // True if two values are equal
472 PRED_NE, // True if two values are not equal
473 PRED_INVALID // Sentinel value
476 ComparePredicate Predicate;
479 MachineBasicBlock *TrueDest;
480 MachineBasicBlock *FalseDest;
481 MachineInstr *ConditionDef;
483 /// SingleUseCondition is true if ConditionDef is dead except for the
484 /// branch(es) at the end of the basic block.
486 bool SingleUseCondition;
488 explicit MachineBranchPredicate()
489 : Predicate(PRED_INVALID), LHS(MachineOperand::CreateImm(0)),
490 RHS(MachineOperand::CreateImm(0)), TrueDest(nullptr),
491 FalseDest(nullptr), ConditionDef(nullptr), SingleUseCondition(false) {
495 /// Analyze the branching code at the end of MBB and parse it into the
496 /// MachineBranchPredicate structure if possible. Returns false on success
497 /// and true on failure.
499 /// If AllowModify is true, then this routine is allowed to modify the basic
500 /// block (e.g. delete instructions after the unconditional branch).
502 virtual bool AnalyzeBranchPredicate(MachineBasicBlock &MBB,
503 MachineBranchPredicate &MBP,
504 bool AllowModify = false) const {
508 /// Remove the branching code at the end of the specific MBB.
509 /// This is only invoked in cases where AnalyzeBranch returns success. It
510 /// returns the number of instructions that were removed.
511 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
512 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
515 /// Insert branch code into the end of the specified MachineBasicBlock.
516 /// The operands to this method are the same as those
517 /// returned by AnalyzeBranch. This is only invoked in cases where
518 /// AnalyzeBranch returns success. It returns the number of instructions
521 /// It is also invoked by tail merging to add unconditional branches in
522 /// cases where AnalyzeBranch doesn't apply because there was no original
523 /// branch to analyze. At least this much must be implemented, else tail
524 /// merging needs to be disabled.
525 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
526 MachineBasicBlock *FBB,
527 ArrayRef<MachineOperand> Cond,
529 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
532 /// Delete the instruction OldInst and everything after it, replacing it with
533 /// an unconditional branch to NewDest. This is used by the tail merging pass.
534 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
535 MachineBasicBlock *NewDest) const;
537 /// Get an instruction that performs an unconditional branch to the given
540 getUnconditionalBranch(MCInst &MI,
541 const MCSymbolRefExpr *BranchTarget) const {
542 llvm_unreachable("Target didn't implement "
543 "TargetInstrInfo::getUnconditionalBranch!");
546 /// Get a machine trap instruction.
547 virtual void getTrap(MCInst &MI) const {
548 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!");
551 /// Get a number of bytes that suffices to hold
552 /// either the instruction returned by getUnconditionalBranch or the
553 /// instruction returned by getTrap. This only makes sense because
554 /// getUnconditionalBranch returns a single, specific instruction. This
555 /// information is needed by the jumptable construction code, since it must
556 /// decide how many bytes to use for a jumptable entry so it can generate the
559 /// Note that if the jumptable instruction requires alignment, then that
560 /// alignment should be factored into this required bound so that the
561 /// resulting bound gives the right alignment for the instruction.
562 virtual unsigned getJumpInstrTableEntryBound() const {
563 // This method gets called by LLVMTargetMachine always, so it can't fail
564 // just because there happens to be no implementation for this target.
565 // Any code that tries to use a jumptable annotation without defining
566 // getUnconditionalBranch on the appropriate Target will fail anyway, and
567 // the value returned here won't matter in that case.
571 /// Return true if it's legal to split the given basic
572 /// block at the specified instruction (i.e. instruction would be the start
573 /// of a new basic block).
574 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
575 MachineBasicBlock::iterator MBBI) const {
579 /// Return true if it's profitable to predicate
580 /// instructions with accumulated instruction latency of "NumCycles"
581 /// of the specified basic block, where the probability of the instructions
582 /// being executed is given by Probability, and Confidence is a measure
583 /// of our confidence that it will be properly predicted.
585 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
586 unsigned ExtraPredCycles,
587 BranchProbability Probability) const {
591 /// Second variant of isProfitableToIfCvt. This one
592 /// checks for the case where two basic blocks from true and false path
593 /// of a if-then-else (diamond) are predicated on mutally exclusive
594 /// predicates, where the probability of the true path being taken is given
595 /// by Probability, and Confidence is a measure of our confidence that it
596 /// will be properly predicted.
598 isProfitableToIfCvt(MachineBasicBlock &TMBB,
599 unsigned NumTCycles, unsigned ExtraTCycles,
600 MachineBasicBlock &FMBB,
601 unsigned NumFCycles, unsigned ExtraFCycles,
602 BranchProbability Probability) const {
606 /// Return true if it's profitable for if-converter to duplicate instructions
607 /// of specified accumulated instruction latencies in the specified MBB to
608 /// enable if-conversion.
609 /// The probability of the instructions being executed is given by
610 /// Probability, and Confidence is a measure of our confidence that it
611 /// will be properly predicted.
613 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
614 BranchProbability Probability) const {
618 /// Return true if it's profitable to unpredicate
619 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
620 /// exclusive predicates.
628 /// This may be profitable is conditional instructions are always executed.
629 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
630 MachineBasicBlock &FMBB) const {
634 /// Return true if it is possible to insert a select
635 /// instruction that chooses between TrueReg and FalseReg based on the
636 /// condition code in Cond.
638 /// When successful, also return the latency in cycles from TrueReg,
639 /// FalseReg, and Cond to the destination register. In most cases, a select
640 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
642 /// Some x86 implementations have 2-cycle cmov instructions.
644 /// @param MBB Block where select instruction would be inserted.
645 /// @param Cond Condition returned by AnalyzeBranch.
646 /// @param TrueReg Virtual register to select when Cond is true.
647 /// @param FalseReg Virtual register to select when Cond is false.
648 /// @param CondCycles Latency from Cond+Branch to select output.
649 /// @param TrueCycles Latency from TrueReg to select output.
650 /// @param FalseCycles Latency from FalseReg to select output.
651 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
652 ArrayRef<MachineOperand> Cond,
653 unsigned TrueReg, unsigned FalseReg,
655 int &TrueCycles, int &FalseCycles) const {
659 /// Insert a select instruction into MBB before I that will copy TrueReg to
660 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
662 /// This function can only be called after canInsertSelect() returned true.
663 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
664 /// that the same flags or registers required by Cond are available at the
667 /// @param MBB Block where select instruction should be inserted.
668 /// @param I Insertion point.
669 /// @param DL Source location for debugging.
670 /// @param DstReg Virtual register to be defined by select instruction.
671 /// @param Cond Condition as computed by AnalyzeBranch.
672 /// @param TrueReg Virtual register to copy when Cond is true.
673 /// @param FalseReg Virtual register to copy when Cons is false.
674 virtual void insertSelect(MachineBasicBlock &MBB,
675 MachineBasicBlock::iterator I, DebugLoc DL,
676 unsigned DstReg, ArrayRef<MachineOperand> Cond,
677 unsigned TrueReg, unsigned FalseReg) const {
678 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
681 /// Analyze the given select instruction, returning true if
682 /// it cannot be understood. It is assumed that MI->isSelect() is true.
684 /// When successful, return the controlling condition and the operands that
685 /// determine the true and false result values.
687 /// Result = SELECT Cond, TrueOp, FalseOp
689 /// Some targets can optimize select instructions, for example by predicating
690 /// the instruction defining one of the operands. Such targets should set
693 /// @param MI Select instruction to analyze.
694 /// @param Cond Condition controlling the select.
695 /// @param TrueOp Operand number of the value selected when Cond is true.
696 /// @param FalseOp Operand number of the value selected when Cond is false.
697 /// @param Optimizable Returned as true if MI is optimizable.
698 /// @returns False on success.
699 virtual bool analyzeSelect(const MachineInstr *MI,
700 SmallVectorImpl<MachineOperand> &Cond,
701 unsigned &TrueOp, unsigned &FalseOp,
702 bool &Optimizable) const {
703 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
707 /// Given a select instruction that was understood by
708 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
709 /// merging it with one of its operands. Returns NULL on failure.
711 /// When successful, returns the new select instruction. The client is
712 /// responsible for deleting MI.
714 /// If both sides of the select can be optimized, PreferFalse is used to pick
717 /// @param MI Optimizable select instruction.
718 /// @param NewMIs Set that record all MIs in the basic block up to \p
719 /// MI. Has to be updated with any newly created MI or deleted ones.
720 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
721 /// @returns Optimized instruction or NULL.
722 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
723 SmallPtrSetImpl<MachineInstr *> &NewMIs,
724 bool PreferFalse = false) const {
725 // This function must be implemented if Optimizable is ever set.
726 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
729 /// Emit instructions to copy a pair of physical registers.
731 /// This function should support copies within any legal register class as
732 /// well as any cross-class copies created during instruction selection.
734 /// The source and destination registers may overlap, which may require a
735 /// careful implementation when multiple copy instructions are required for
736 /// large registers. See for example the ARM target.
737 virtual void copyPhysReg(MachineBasicBlock &MBB,
738 MachineBasicBlock::iterator MI, DebugLoc DL,
739 unsigned DestReg, unsigned SrcReg,
740 bool KillSrc) const {
741 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
744 /// Store the specified register of the given register class to the specified
745 /// stack frame index. The store instruction is to be added to the given
746 /// machine basic block before the specified machine instruction. If isKill
747 /// is true, the register operand is the last use and must be marked kill.
748 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
749 MachineBasicBlock::iterator MI,
750 unsigned SrcReg, bool isKill, int FrameIndex,
751 const TargetRegisterClass *RC,
752 const TargetRegisterInfo *TRI) const {
753 llvm_unreachable("Target didn't implement "
754 "TargetInstrInfo::storeRegToStackSlot!");
757 /// Load the specified register of the given register class from the specified
758 /// stack frame index. The load instruction is to be added to the given
759 /// machine basic block before the specified machine instruction.
760 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
761 MachineBasicBlock::iterator MI,
762 unsigned DestReg, int FrameIndex,
763 const TargetRegisterClass *RC,
764 const TargetRegisterInfo *TRI) const {
765 llvm_unreachable("Target didn't implement "
766 "TargetInstrInfo::loadRegFromStackSlot!");
769 /// This function is called for all pseudo instructions
770 /// that remain after register allocation. Many pseudo instructions are
771 /// created to help register allocation. This is the place to convert them
772 /// into real instructions. The target can edit MI in place, or it can insert
773 /// new instructions and erase MI. The function should return true if
774 /// anything was changed.
775 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
779 /// Attempt to fold a load or store of the specified stack
780 /// slot into the specified machine instruction for the specified operand(s).
781 /// If this is possible, a new instruction is returned with the specified
782 /// operand folded, otherwise NULL is returned.
783 /// The new instruction is inserted before MI, and the client is responsible
784 /// for removing the old instruction.
785 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
786 ArrayRef<unsigned> Ops, int FrameIndex) const;
788 /// Same as the previous version except it allows folding of any load and
789 /// store from / to any address, not just from a specific stack slot.
790 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
791 ArrayRef<unsigned> Ops,
792 MachineInstr *LoadMI) const;
794 /// Return true when there is potentially a faster code sequence
795 /// for an instruction chain ending in \p Root. All potential patterns are
796 /// returned in the \p Pattern vector. Pattern should be sorted in priority
797 /// order since the pattern evaluator stops checking as soon as it finds a
799 /// \param Root - Instruction that could be combined with one of its operands
800 /// \param Patterns - Vector of possible combination patterns
801 virtual bool getMachineCombinerPatterns(
803 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const;
805 /// Return true if the input \P Inst is part of a chain of dependent ops
806 /// that are suitable for reassociation, otherwise return false.
807 /// If the instruction's operands must be commuted to have a previous
808 /// instruction of the same type define the first source operand, \P Commuted
809 /// will be set to true.
810 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
812 /// Return true when \P Inst is both associative and commutative.
813 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
817 /// Return true when \P Inst has reassociable operands in the same \P MBB.
818 virtual bool hasReassociableOperands(const MachineInstr &Inst,
819 const MachineBasicBlock *MBB) const;
821 /// Return true when \P Inst has reassociable sibling.
822 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
824 /// When getMachineCombinerPatterns() finds patterns, this function generates
825 /// the instructions that could replace the original code sequence. The client
826 /// has to decide whether the actual replacement is beneficial or not.
827 /// \param Root - Instruction that could be combined with one of its operands
828 /// \param Pattern - Combination pattern for Root
829 /// \param InsInstrs - Vector of new instructions that implement P
830 /// \param DelInstrs - Old instructions, including Root, that could be
831 /// replaced by InsInstr
832 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
833 /// InsInstr that defines it
834 virtual void genAlternativeCodeSequence(
835 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern,
836 SmallVectorImpl<MachineInstr *> &InsInstrs,
837 SmallVectorImpl<MachineInstr *> &DelInstrs,
838 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
840 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
841 /// reduce critical path length.
842 void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
843 MachineCombinerPattern::MC_PATTERN Pattern,
844 SmallVectorImpl<MachineInstr *> &InsInstrs,
845 SmallVectorImpl<MachineInstr *> &DelInstrs,
846 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
848 /// This is an architecture-specific helper function of reassociateOps.
849 /// Set special operand attributes for new instructions after reassociation.
850 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
851 MachineInstr &NewMI1,
852 MachineInstr &NewMI2) const {
856 /// Return true when a target supports MachineCombiner.
857 virtual bool useMachineCombiner() const { return false; }
860 /// Target-dependent implementation for foldMemoryOperand.
861 /// Target-independent code in foldMemoryOperand will
862 /// take care of adding a MachineMemOperand to the newly created instruction.
863 /// The instruction and any auxiliary instructions necessary will be inserted
865 virtual MachineInstr *foldMemoryOperandImpl(
866 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
867 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
871 /// Target-dependent implementation for foldMemoryOperand.
872 /// Target-independent code in foldMemoryOperand will
873 /// take care of adding a MachineMemOperand to the newly created instruction.
874 /// The instruction and any auxiliary instructions necessary will be inserted
876 virtual MachineInstr *foldMemoryOperandImpl(
877 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
878 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
882 /// \brief Target-dependent implementation of getRegSequenceInputs.
884 /// \returns true if it is possible to build the equivalent
885 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
887 /// \pre MI.isRegSequenceLike().
889 /// \see TargetInstrInfo::getRegSequenceInputs.
890 virtual bool getRegSequenceLikeInputs(
891 const MachineInstr &MI, unsigned DefIdx,
892 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
896 /// \brief Target-dependent implementation of getExtractSubregInputs.
898 /// \returns true if it is possible to build the equivalent
899 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
901 /// \pre MI.isExtractSubregLike().
903 /// \see TargetInstrInfo::getExtractSubregInputs.
904 virtual bool getExtractSubregLikeInputs(
905 const MachineInstr &MI, unsigned DefIdx,
906 RegSubRegPairAndIdx &InputReg) const {
910 /// \brief Target-dependent implementation of getInsertSubregInputs.
912 /// \returns true if it is possible to build the equivalent
913 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
915 /// \pre MI.isInsertSubregLike().
917 /// \see TargetInstrInfo::getInsertSubregInputs.
919 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
920 RegSubRegPair &BaseReg,
921 RegSubRegPairAndIdx &InsertedReg) const {
926 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
927 /// a store or a load and a store into two or more instruction. If this is
928 /// possible, returns true as well as the new instructions by reference.
929 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
930 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
931 SmallVectorImpl<MachineInstr*> &NewMIs) const{
935 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
936 SmallVectorImpl<SDNode*> &NewNodes) const {
940 /// Returns the opcode of the would be new
941 /// instruction after load / store are unfolded from an instruction of the
942 /// specified opcode. It returns zero if the specified unfolding is not
943 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
944 /// index of the operand which will hold the register holding the loaded
946 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
947 bool UnfoldLoad, bool UnfoldStore,
948 unsigned *LoadRegIndex = nullptr) const {
952 /// This is used by the pre-regalloc scheduler to determine if two loads are
953 /// loading from the same base address. It should only return true if the base
954 /// pointers are the same and the only differences between the two addresses
955 /// are the offset. It also returns the offsets by reference.
956 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
957 int64_t &Offset1, int64_t &Offset2) const {
961 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
962 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
963 /// On some targets if two loads are loading from
964 /// addresses in the same cache line, it's better if they are scheduled
965 /// together. This function takes two integers that represent the load offsets
966 /// from the common base address. It returns true if it decides it's desirable
967 /// to schedule the two loads together. "NumLoads" is the number of loads that
968 /// have already been scheduled after Load1.
969 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
970 int64_t Offset1, int64_t Offset2,
971 unsigned NumLoads) const {
975 /// Get the base register and byte offset of an instruction that reads/writes
977 virtual bool getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
979 const TargetRegisterInfo *TRI) const {
983 virtual bool enableClusterLoads() const { return false; }
985 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
986 MachineInstr *SecondLdSt,
987 unsigned NumLoads) const {
991 /// Can this target fuse the given instructions if they are scheduled
993 virtual bool shouldScheduleAdjacent(MachineInstr* First,
994 MachineInstr *Second) const {
998 /// Reverses the branch condition of the specified condition list,
999 /// returning false on success and true if it cannot be reversed.
1001 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1005 /// Insert a noop into the instruction stream at the specified point.
1006 virtual void insertNoop(MachineBasicBlock &MBB,
1007 MachineBasicBlock::iterator MI) const;
1010 /// Return the noop instruction to use for a noop.
1011 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
1014 /// Returns true if the instruction is already predicated.
1015 virtual bool isPredicated(const MachineInstr *MI) const {
1019 /// Returns true if the instruction is a
1020 /// terminator instruction that has not been predicated.
1021 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
1023 /// Convert the instruction into a predicated instruction.
1024 /// It returns true if the operation was successful.
1026 bool PredicateInstruction(MachineInstr *MI,
1027 ArrayRef<MachineOperand> Pred) const;
1029 /// Returns true if the first specified predicate
1030 /// subsumes the second, e.g. GE subsumes GT.
1032 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1033 ArrayRef<MachineOperand> Pred2) const {
1037 /// If the specified instruction defines any predicate
1038 /// or condition code register(s) used for predication, returns true as well
1039 /// as the definition predicate(s) by reference.
1040 virtual bool DefinesPredicate(MachineInstr *MI,
1041 std::vector<MachineOperand> &Pred) const {
1045 /// Return true if the specified instruction can be predicated.
1046 /// By default, this returns true for every instruction with a
1047 /// PredicateOperand.
1048 virtual bool isPredicable(MachineInstr *MI) const {
1049 return MI->getDesc().isPredicable();
1052 /// Return true if it's safe to move a machine
1053 /// instruction that defines the specified register class.
1054 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1058 /// Test if the given instruction should be considered a scheduling boundary.
1059 /// This primarily includes labels and terminators.
1060 virtual bool isSchedulingBoundary(const MachineInstr *MI,
1061 const MachineBasicBlock *MBB,
1062 const MachineFunction &MF) const;
1064 /// Measure the specified inline asm to determine an approximation of its
1066 virtual unsigned getInlineAsmLength(const char *Str,
1067 const MCAsmInfo &MAI) const;
1069 /// Allocate and return a hazard recognizer to use for this target when
1070 /// scheduling the machine instructions before register allocation.
1071 virtual ScheduleHazardRecognizer*
1072 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1073 const ScheduleDAG *DAG) const;
1075 /// Allocate and return a hazard recognizer to use for this target when
1076 /// scheduling the machine instructions before register allocation.
1077 virtual ScheduleHazardRecognizer*
1078 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
1079 const ScheduleDAG *DAG) const;
1081 /// Allocate and return a hazard recognizer to use for this target when
1082 /// scheduling the machine instructions after register allocation.
1083 virtual ScheduleHazardRecognizer*
1084 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
1085 const ScheduleDAG *DAG) const;
1087 /// Provide a global flag for disabling the PreRA hazard recognizer that
1088 /// targets may choose to honor.
1089 bool usePreRAHazardRecognizer() const;
1091 /// For a comparison instruction, return the source registers
1092 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1093 /// compares against in CmpValue. Return true if the comparison instruction
1094 /// can be analyzed.
1095 virtual bool analyzeCompare(const MachineInstr *MI,
1096 unsigned &SrcReg, unsigned &SrcReg2,
1097 int &Mask, int &Value) const {
1101 /// See if the comparison instruction can be converted
1102 /// into something more efficient. E.g., on ARM most instructions can set the
1103 /// flags register, obviating the need for a separate CMP.
1104 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
1105 unsigned SrcReg, unsigned SrcReg2,
1106 int Mask, int Value,
1107 const MachineRegisterInfo *MRI) const {
1110 virtual bool optimizeCondBranch(MachineInstr *MI) const { return false; }
1112 /// Try to remove the load by folding it to a register operand at the use.
1113 /// We fold the load instructions if and only if the
1114 /// def and use are in the same BB. We only look at one load and see
1115 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1116 /// defined by the load we are trying to fold. DefMI returns the machine
1117 /// instruction that defines FoldAsLoadDefReg, and the function returns
1118 /// the machine instruction generated due to folding.
1119 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
1120 const MachineRegisterInfo *MRI,
1121 unsigned &FoldAsLoadDefReg,
1122 MachineInstr *&DefMI) const {
1126 /// 'Reg' is known to be defined by a move immediate instruction,
1127 /// try to fold the immediate into the use instruction.
1128 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1129 /// then the caller may assume that DefMI has been erased from its parent
1130 /// block. The caller may assume that it will not be erased by this
1131 /// function otherwise.
1132 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1133 unsigned Reg, MachineRegisterInfo *MRI) const {
1137 /// Return the number of u-operations the given machine
1138 /// instruction will be decoded to on the target cpu. The itinerary's
1139 /// IssueWidth is the number of microops that can be dispatched each
1140 /// cycle. An instruction with zero microops takes no dispatch resources.
1141 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1142 const MachineInstr *MI) const;
1144 /// Return true for pseudo instructions that don't consume any
1145 /// machine resources in their current form. These are common cases that the
1146 /// scheduler should consider free, rather than conservatively handling them
1147 /// as instructions with no itinerary.
1148 bool isZeroCost(unsigned Opcode) const {
1149 return Opcode <= TargetOpcode::COPY;
1152 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1153 SDNode *DefNode, unsigned DefIdx,
1154 SDNode *UseNode, unsigned UseIdx) const;
1156 /// Compute and return the use operand latency of a given pair of def and use.
1157 /// In most cases, the static scheduling itinerary was enough to determine the
1158 /// operand latency. But it may not be possible for instructions with variable
1159 /// number of defs / uses.
1161 /// This is a raw interface to the itinerary that may be directly overridden
1162 /// by a target. Use computeOperandLatency to get the best estimate of
1164 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1165 const MachineInstr *DefMI, unsigned DefIdx,
1166 const MachineInstr *UseMI,
1167 unsigned UseIdx) const;
1169 /// Compute and return the latency of the given data
1170 /// dependent def and use when the operand indices are already known.
1171 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
1172 const MachineInstr *DefMI, unsigned DefIdx,
1173 const MachineInstr *UseMI, unsigned UseIdx)
1176 /// Compute the instruction latency of a given instruction.
1177 /// If the instruction has higher cost when predicated, it's returned via
1179 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1180 const MachineInstr *MI,
1181 unsigned *PredCost = nullptr) const;
1183 virtual unsigned getPredicationCost(const MachineInstr *MI) const;
1185 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1186 SDNode *Node) const;
1188 /// Return the default expected latency for a def based on it's opcode.
1189 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1190 const MachineInstr *DefMI) const;
1192 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1193 const MachineInstr *DefMI) const;
1195 /// Return true if this opcode has high latency to its result.
1196 virtual bool isHighLatencyDef(int opc) const { return false; }
1198 /// Compute operand latency between a def of 'Reg'
1199 /// and a use in the current loop. Return true if the target considered
1200 /// it 'high'. This is used by optimization passes such as machine LICM to
1201 /// determine whether it makes sense to hoist an instruction out even in a
1202 /// high register pressure situation.
1204 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1205 const MachineRegisterInfo *MRI,
1206 const MachineInstr *DefMI, unsigned DefIdx,
1207 const MachineInstr *UseMI, unsigned UseIdx) const {
1211 /// Compute operand latency of a def of 'Reg'. Return true
1212 /// if the target considered it 'low'.
1214 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1215 const MachineInstr *DefMI, unsigned DefIdx) const;
1217 /// Perform target-specific instruction verification.
1219 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
1223 /// Return the current execution domain and bit mask of
1224 /// possible domains for instruction.
1226 /// Some micro-architectures have multiple execution domains, and multiple
1227 /// opcodes that perform the same operation in different domains. For
1228 /// example, the x86 architecture provides the por, orps, and orpd
1229 /// instructions that all do the same thing. There is a latency penalty if a
1230 /// register is written in one domain and read in another.
1232 /// This function returns a pair (domain, mask) containing the execution
1233 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1234 /// function can be used to change the opcode to one of the domains in the
1235 /// bit mask. Instructions whose execution domain can't be changed should
1236 /// return a 0 mask.
1238 /// The execution domain numbers don't have any special meaning except domain
1239 /// 0 is used for instructions that are not associated with any interesting
1240 /// execution domain.
1242 virtual std::pair<uint16_t, uint16_t>
1243 getExecutionDomain(const MachineInstr *MI) const {
1244 return std::make_pair(0, 0);
1247 /// Change the opcode of MI to execute in Domain.
1249 /// The bit (1 << Domain) must be set in the mask returned from
1250 /// getExecutionDomain(MI).
1251 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
1254 /// Returns the preferred minimum clearance
1255 /// before an instruction with an unwanted partial register update.
1257 /// Some instructions only write part of a register, and implicitly need to
1258 /// read the other parts of the register. This may cause unwanted stalls
1259 /// preventing otherwise unrelated instructions from executing in parallel in
1260 /// an out-of-order CPU.
1262 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1263 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1264 /// the instruction needs to wait for the old value of the register to become
1267 /// addps %xmm1, %xmm0
1268 /// movaps %xmm0, (%rax)
1269 /// cvtsi2ss %rbx, %xmm0
1271 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1272 /// instruction before it can issue, even though the high bits of %xmm0
1273 /// probably aren't needed.
1275 /// This hook returns the preferred clearance before MI, measured in
1276 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1277 /// instructions before MI. It should only return a positive value for
1278 /// unwanted dependencies. If the old bits of the defined register have
1279 /// useful values, or if MI is determined to otherwise read the dependency,
1280 /// the hook should return 0.
1282 /// The unwanted dependency may be handled by:
1284 /// 1. Allocating the same register for an MI def and use. That makes the
1285 /// unwanted dependency identical to a required dependency.
1287 /// 2. Allocating a register for the def that has no defs in the previous N
1290 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1291 /// allows the target to insert a dependency breaking instruction.
1294 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
1295 const TargetRegisterInfo *TRI) const {
1296 // The default implementation returns 0 for no partial register dependency.
1300 /// \brief Return the minimum clearance before an instruction that reads an
1301 /// unused register.
1303 /// For example, AVX instructions may copy part of a register operand into
1304 /// the unused high bits of the destination register.
1306 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1308 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1309 /// false dependence on any previous write to %xmm0.
1311 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1312 /// does not take an operand index. Instead sets \p OpNum to the index of the
1313 /// unused register.
1314 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
1315 const TargetRegisterInfo *TRI) const {
1316 // The default implementation returns 0 for no undef register dependency.
1320 /// Insert a dependency-breaking instruction
1321 /// before MI to eliminate an unwanted dependency on OpNum.
1323 /// If it wasn't possible to avoid a def in the last N instructions before MI
1324 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1325 /// unwanted dependency.
1327 /// On x86, an xorps instruction can be used as a dependency breaker:
1329 /// addps %xmm1, %xmm0
1330 /// movaps %xmm0, (%rax)
1331 /// xorps %xmm0, %xmm0
1332 /// cvtsi2ss %rbx, %xmm0
1334 /// An <imp-kill> operand should be added to MI if an instruction was
1335 /// inserted. This ties the instructions together in the post-ra scheduler.
1338 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
1339 const TargetRegisterInfo *TRI) const {}
1341 /// Create machine specific model for scheduling.
1342 virtual DFAPacketizer *
1343 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1347 // Sometimes, it is possible for the target
1348 // to tell, even without aliasing information, that two MIs access different
1349 // memory addresses. This function returns true if two MIs access different
1350 // memory addresses and false otherwise.
1352 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
1353 AliasAnalysis *AA = nullptr) const {
1354 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1355 "MIa must load from or modify a memory location");
1356 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1357 "MIb must load from or modify a memory location");
1361 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1362 /// which is a heuristic used for CSE'ing phys reg defs.
1363 virtual unsigned getMachineCSELookAheadLimit () const {
1364 // The default lookahead is small to prevent unprofitable quadratic
1369 /// Return an array that contains the ids of the target indices (used for the
1370 /// TargetIndex machine operand) and their names.
1372 /// MIR Serialization is able to serialize only the target indices that are
1373 /// defined by this method.
1374 virtual ArrayRef<std::pair<int, const char *>>
1375 getSerializableTargetIndices() const {
1379 /// Decompose the machine operand's target flags into two values - the direct
1380 /// target flag value and any of bit flags that are applied.
1381 virtual std::pair<unsigned, unsigned>
1382 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1383 return std::make_pair(0u, 0u);
1386 /// Return an array that contains the direct target flag values and their
1389 /// MIR Serialization is able to serialize only the target flags that are
1390 /// defined by this method.
1391 virtual ArrayRef<std::pair<unsigned, const char *>>
1392 getSerializableDirectMachineOperandTargetFlags() const {
1396 /// Return an array that contains the bitmask target flag values and their
1399 /// MIR Serialization is able to serialize only the target flags that are
1400 /// defined by this method.
1401 virtual ArrayRef<std::pair<unsigned, const char *>>
1402 getSerializableBitmaskMachineOperandTargetFlags() const {
1407 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1408 unsigned CatchRetOpcode;
1411 /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1413 struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
1414 typedef DenseMapInfo<unsigned> RegInfo;
1416 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1417 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1418 RegInfo::getEmptyKey());
1420 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1421 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1422 RegInfo::getTombstoneKey());
1424 /// \brief Reuse getHashValue implementation from
1425 /// std::pair<unsigned, unsigned>.
1426 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1427 std::pair<unsigned, unsigned> PairVal =
1428 std::make_pair(Val.Reg, Val.SubReg);
1429 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1431 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1432 const TargetInstrInfo::RegSubRegPair &RHS) {
1433 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1434 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1438 } // End llvm namespace