1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
26 class InstrItineraryData;
29 class MachineMemOperand;
30 class MachineRegisterInfo;
34 class MCSymbolRefExpr;
36 class ScheduleHazardRecognizer;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class BranchProbability;
42 class TargetSubtargetInfo;
45 template<class T> class SmallVectorImpl;
48 //---------------------------------------------------------------------------
50 /// TargetInstrInfo - Interface to description of machine instruction set
52 class TargetInstrInfo : public MCInstrInfo {
53 TargetInstrInfo(const TargetInstrInfo &) = delete;
54 void operator=(const TargetInstrInfo &) = delete;
56 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
57 : CallFrameSetupOpcode(CFSetupOpcode),
58 CallFrameDestroyOpcode(CFDestroyOpcode) {
61 virtual ~TargetInstrInfo();
63 /// getRegClass - Givem a machine instruction descriptor, returns the register
64 /// class constraint for OpNum, or NULL.
65 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
67 const TargetRegisterInfo *TRI,
68 const MachineFunction &MF) const;
70 /// isTriviallyReMaterializable - Return true if the instruction is trivially
71 /// rematerializable, meaning it has no side effects and requires no operands
72 /// that aren't always available.
73 bool isTriviallyReMaterializable(const MachineInstr *MI,
74 AliasAnalysis *AA = nullptr) const {
75 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
76 (MI->getDesc().isRematerializable() &&
77 (isReallyTriviallyReMaterializable(MI, AA) ||
78 isReallyTriviallyReMaterializableGeneric(MI, AA)));
82 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
83 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
84 /// specify whether the instruction is actually trivially rematerializable,
85 /// taking into consideration its operands. This predicate must return false
86 /// if the instruction has any side effects other than producing a value, or
87 /// if it requres any address registers that are not always available.
88 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
89 AliasAnalysis *AA) const {
94 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
95 /// for which the M_REMATERIALIZABLE flag is set and the target hook
96 /// isReallyTriviallyReMaterializable returns false, this function does
97 /// target-independent tests to determine if the instruction is really
98 /// trivially rematerializable.
99 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
100 AliasAnalysis *AA) const;
103 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
104 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
105 /// targets use pseudo instructions in order to abstract away the difference
106 /// between operating with a frame pointer and operating without, through the
107 /// use of these two instructions.
109 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
110 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
112 /// Returns the actual stack pointer adjustment made by an instruction
113 /// as part of a call sequence. By default, only call frame setup/destroy
114 /// instructions adjust the stack, but targets may want to override this
115 /// to enable more fine-grained adjustment, or adjust by a different value.
116 virtual int getSPAdjust(const MachineInstr *MI) const;
118 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
119 /// extension instruction. That is, it's like a copy where it's legal for the
120 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
121 /// true, then it's expected the pre-extension value is available as a subreg
122 /// of the result register. This also returns the sub-register index in
124 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
125 unsigned &SrcReg, unsigned &DstReg,
126 unsigned &SubIdx) const {
130 /// isLoadFromStackSlot - If the specified machine instruction is a direct
131 /// load from a stack slot, return the virtual or physical register number of
132 /// the destination along with the FrameIndex of the loaded stack slot. If
133 /// not, return 0. This predicate must return 0 if the instruction has
134 /// any side effects other than loading from the stack slot.
135 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
136 int &FrameIndex) const {
140 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
141 /// stack locations as well. This uses a heuristic so it isn't
142 /// reliable for correctness.
143 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
144 int &FrameIndex) const {
148 /// hasLoadFromStackSlot - If the specified machine instruction has
149 /// a load from a stack slot, return true along with the FrameIndex
150 /// of the loaded stack slot and the machine mem operand containing
151 /// the reference. If not, return false. Unlike
152 /// isLoadFromStackSlot, this returns true for any instructions that
153 /// loads from the stack. This is just a hint, as some cases may be
155 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
156 const MachineMemOperand *&MMO,
157 int &FrameIndex) const;
159 /// isStoreToStackSlot - If the specified machine instruction is a direct
160 /// store to a stack slot, return the virtual or physical register number of
161 /// the source reg along with the FrameIndex of the loaded stack slot. If
162 /// not, return 0. This predicate must return 0 if the instruction has
163 /// any side effects other than storing to the stack slot.
164 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
165 int &FrameIndex) const {
169 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
170 /// stack locations as well. This uses a heuristic so it isn't
171 /// reliable for correctness.
172 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
173 int &FrameIndex) const {
177 /// hasStoreToStackSlot - If the specified machine instruction has a
178 /// store to a stack slot, return true along with the FrameIndex of
179 /// the loaded stack slot and the machine mem operand containing the
180 /// reference. If not, return false. Unlike isStoreToStackSlot,
181 /// this returns true for any instructions that stores to the
182 /// stack. This is just a hint, as some cases may be missed.
183 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
184 const MachineMemOperand *&MMO,
185 int &FrameIndex) const;
187 /// isStackSlotCopy - Return true if the specified machine instruction
188 /// is a copy of one stack slot to another and has no other effect.
189 /// Provide the identity of the two frame indices.
190 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
191 int &SrcFrameIndex) const {
195 /// Compute the size in bytes and offset within a stack slot of a spilled
196 /// register or subregister.
198 /// \param [out] Size in bytes of the spilled value.
199 /// \param [out] Offset in bytes within the stack slot.
200 /// \returns true if both Size and Offset are successfully computed.
202 /// Not all subregisters have computable spill slots. For example,
203 /// subregisters registers may not be byte-sized, and a pair of discontiguous
204 /// subregisters has no single offset.
206 /// Targets with nontrivial bigendian implementations may need to override
207 /// this, particularly to support spilled vector registers.
208 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
209 unsigned &Size, unsigned &Offset,
210 const MachineFunction &MF) const;
212 /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move
215 /// Targets for different archs need to override this, and different
216 /// micro-architectures can also be finely tuned inside.
217 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const {
218 return MI->isAsCheapAsAMove();
221 /// reMaterialize - Re-issue the specified 'original' instruction at the
222 /// specific location targeting a new destination register.
223 /// The register in Orig->getOperand(0).getReg() will be substituted by
224 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
226 virtual void reMaterialize(MachineBasicBlock &MBB,
227 MachineBasicBlock::iterator MI,
228 unsigned DestReg, unsigned SubIdx,
229 const MachineInstr *Orig,
230 const TargetRegisterInfo &TRI) const;
232 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
233 /// MachineFunction::CloneMachineInstr(), but the target may update operands
234 /// that are required to be unique.
236 /// The instruction must be duplicable as indicated by isNotDuplicable().
237 virtual MachineInstr *duplicate(MachineInstr *Orig,
238 MachineFunction &MF) const;
240 /// convertToThreeAddress - This method must be implemented by targets that
241 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
242 /// may be able to convert a two-address instruction into one or more true
243 /// three-address instructions on demand. This allows the X86 target (for
244 /// example) to convert ADD and SHL instructions into LEA instructions if they
245 /// would require register copies due to two-addressness.
247 /// This method returns a null pointer if the transformation cannot be
248 /// performed, otherwise it returns the last new instruction.
250 virtual MachineInstr *
251 convertToThreeAddress(MachineFunction::iterator &MFI,
252 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
256 /// commuteInstruction - If a target has any instructions that are
257 /// commutable but require converting to different instructions or making
258 /// non-trivial changes to commute them, this method can overloaded to do
259 /// that. The default implementation simply swaps the commutable operands.
260 /// If NewMI is false, MI is modified in place and returned; otherwise, a
261 /// new machine instruction is created and returned. Do not call this
262 /// method for a non-commutable instruction, but there may be some cases
263 /// where this method fails and returns null.
264 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
265 bool NewMI = false) const;
267 /// findCommutedOpIndices - If specified MI is commutable, return the two
268 /// operand indices that would swap value. Return false if the instruction
269 /// is not in a form which this routine understands.
270 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
271 unsigned &SrcOpIdx2) const;
273 /// A pair composed of a register and a sub-register index.
274 /// Used to give some type checking when modeling Reg:SubReg.
275 struct RegSubRegPair {
278 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
279 : Reg(Reg), SubReg(SubReg) {}
281 /// A pair composed of a pair of a register and a sub-register index,
282 /// and another sub-register index.
283 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
284 struct RegSubRegPairAndIdx : RegSubRegPair {
286 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
288 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
291 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
293 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
294 /// the list is modeled as <Reg:SubReg, SubIdx>.
295 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
297 /// - vreg1:sub1, sub0
298 /// - vreg2<:0>, sub1
300 /// \returns true if it is possible to build such an input sequence
301 /// with the pair \p MI, \p DefIdx. False otherwise.
303 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
305 /// \note The generic implementation does not provide any support for
306 /// MI.isRegSequenceLike(). In other words, one has to override
307 /// getRegSequenceLikeInputs for target specific instructions.
309 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
310 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
312 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
314 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
315 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
316 /// - vreg1:sub1, sub0
318 /// \returns true if it is possible to build such an input sequence
319 /// with the pair \p MI, \p DefIdx. False otherwise.
321 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
323 /// \note The generic implementation does not provide any support for
324 /// MI.isExtractSubregLike(). In other words, one has to override
325 /// getExtractSubregLikeInputs for target specific instructions.
327 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
328 RegSubRegPairAndIdx &InputReg) const;
330 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
332 /// \p [out] BaseReg and \p [out] InsertedReg contain
333 /// the equivalent inputs of INSERT_SUBREG.
334 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
335 /// - BaseReg: vreg0:sub0
336 /// - InsertedReg: vreg1:sub1, sub3
338 /// \returns true if it is possible to build such an input sequence
339 /// with the pair \p MI, \p DefIdx. False otherwise.
341 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
343 /// \note The generic implementation does not provide any support for
344 /// MI.isInsertSubregLike(). In other words, one has to override
345 /// getInsertSubregLikeInputs for target specific instructions.
347 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
348 RegSubRegPair &BaseReg,
349 RegSubRegPairAndIdx &InsertedReg) const;
352 /// produceSameValue - Return true if two machine instructions would produce
353 /// identical values. By default, this is only true when the two instructions
354 /// are deemed identical except for defs. If this function is called when the
355 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
356 /// aggressive checks.
357 virtual bool produceSameValue(const MachineInstr *MI0,
358 const MachineInstr *MI1,
359 const MachineRegisterInfo *MRI = nullptr) const;
361 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
362 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
363 /// implemented for a target). Upon success, this returns false and returns
364 /// with the following information in various cases:
366 /// 1. If this block ends with no branches (it just falls through to its succ)
367 /// just return false, leaving TBB/FBB null.
368 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
369 /// the destination block.
370 /// 3. If this block ends with a conditional branch and it falls through to a
371 /// successor block, it sets TBB to be the branch destination block and a
372 /// list of operands that evaluate the condition. These operands can be
373 /// passed to other TargetInstrInfo methods to create new branches.
374 /// 4. If this block ends with a conditional branch followed by an
375 /// unconditional branch, it returns the 'true' destination in TBB, the
376 /// 'false' destination in FBB, and a list of operands that evaluate the
377 /// condition. These operands can be passed to other TargetInstrInfo
378 /// methods to create new branches.
380 /// Note that RemoveBranch and InsertBranch must be implemented to support
381 /// cases where this method returns success.
383 /// If AllowModify is true, then this routine is allowed to modify the basic
384 /// block (e.g. delete instructions after the unconditional branch).
386 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
387 MachineBasicBlock *&FBB,
388 SmallVectorImpl<MachineOperand> &Cond,
389 bool AllowModify = false) const {
393 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
394 /// This is only invoked in cases where AnalyzeBranch returns success. It
395 /// returns the number of instructions that were removed.
396 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
397 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
400 /// InsertBranch - Insert branch code into the end of the specified
401 /// MachineBasicBlock. The operands to this method are the same as those
402 /// returned by AnalyzeBranch. This is only invoked in cases where
403 /// AnalyzeBranch returns success. It returns the number of instructions
406 /// It is also invoked by tail merging to add unconditional branches in
407 /// cases where AnalyzeBranch doesn't apply because there was no original
408 /// branch to analyze. At least this much must be implemented, else tail
409 /// merging needs to be disabled.
410 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
411 MachineBasicBlock *FBB,
412 const SmallVectorImpl<MachineOperand> &Cond,
414 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
417 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
418 /// after it, replacing it with an unconditional branch to NewDest. This is
419 /// used by the tail merging pass.
420 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
421 MachineBasicBlock *NewDest) const;
423 /// getUnconditionalBranch - Get an instruction that performs an unconditional
424 /// branch to the given symbol.
426 getUnconditionalBranch(MCInst &MI,
427 const MCSymbolRefExpr *BranchTarget) const {
428 llvm_unreachable("Target didn't implement "
429 "TargetInstrInfo::getUnconditionalBranch!");
432 /// getTrap - Get a machine trap instruction
433 virtual void getTrap(MCInst &MI) const {
434 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!");
437 /// getJumpInstrTableEntryBound - Get a number of bytes that suffices to hold
438 /// either the instruction returned by getUnconditionalBranch or the
439 /// instruction returned by getTrap. This only makes sense because
440 /// getUnconditionalBranch returns a single, specific instruction. This
441 /// information is needed by the jumptable construction code, since it must
442 /// decide how many bytes to use for a jumptable entry so it can generate the
445 /// Note that if the jumptable instruction requires alignment, then that
446 /// alignment should be factored into this required bound so that the
447 /// resulting bound gives the right alignment for the instruction.
448 virtual unsigned getJumpInstrTableEntryBound() const {
449 // This method gets called by LLVMTargetMachine always, so it can't fail
450 // just because there happens to be no implementation for this target.
451 // Any code that tries to use a jumptable annotation without defining
452 // getUnconditionalBranch on the appropriate Target will fail anyway, and
453 // the value returned here won't matter in that case.
457 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
458 /// block at the specified instruction (i.e. instruction would be the start
459 /// of a new basic block).
460 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MBBI) const {
465 /// isProfitableToIfCvt - Return true if it's profitable to predicate
466 /// instructions with accumulated instruction latency of "NumCycles"
467 /// of the specified basic block, where the probability of the instructions
468 /// being executed is given by Probability, and Confidence is a measure
469 /// of our confidence that it will be properly predicted.
471 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
472 unsigned ExtraPredCycles,
473 const BranchProbability &Probability) const {
477 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
478 /// checks for the case where two basic blocks from true and false path
479 /// of a if-then-else (diamond) are predicated on mutally exclusive
480 /// predicates, where the probability of the true path being taken is given
481 /// by Probability, and Confidence is a measure of our confidence that it
482 /// will be properly predicted.
484 isProfitableToIfCvt(MachineBasicBlock &TMBB,
485 unsigned NumTCycles, unsigned ExtraTCycles,
486 MachineBasicBlock &FMBB,
487 unsigned NumFCycles, unsigned ExtraFCycles,
488 const BranchProbability &Probability) const {
492 /// isProfitableToDupForIfCvt - Return true if it's profitable for
493 /// if-converter to duplicate instructions of specified accumulated
494 /// instruction latencies in the specified MBB to enable if-conversion.
495 /// The probability of the instructions being executed is given by
496 /// Probability, and Confidence is a measure of our confidence that it
497 /// will be properly predicted.
499 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
500 const BranchProbability &Probability) const {
504 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate
505 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
506 /// exclusive predicates.
514 /// This may be profitable is conditional instructions are always executed.
515 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
516 MachineBasicBlock &FMBB) const {
520 /// canInsertSelect - Return true if it is possible to insert a select
521 /// instruction that chooses between TrueReg and FalseReg based on the
522 /// condition code in Cond.
524 /// When successful, also return the latency in cycles from TrueReg,
525 /// FalseReg, and Cond to the destination register. In most cases, a select
526 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
528 /// Some x86 implementations have 2-cycle cmov instructions.
530 /// @param MBB Block where select instruction would be inserted.
531 /// @param Cond Condition returned by AnalyzeBranch.
532 /// @param TrueReg Virtual register to select when Cond is true.
533 /// @param FalseReg Virtual register to select when Cond is false.
534 /// @param CondCycles Latency from Cond+Branch to select output.
535 /// @param TrueCycles Latency from TrueReg to select output.
536 /// @param FalseCycles Latency from FalseReg to select output.
537 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
538 const SmallVectorImpl<MachineOperand> &Cond,
539 unsigned TrueReg, unsigned FalseReg,
541 int &TrueCycles, int &FalseCycles) const {
545 /// insertSelect - Insert a select instruction into MBB before I that will
546 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
549 /// This function can only be called after canInsertSelect() returned true.
550 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
551 /// that the same flags or registers required by Cond are available at the
554 /// @param MBB Block where select instruction should be inserted.
555 /// @param I Insertion point.
556 /// @param DL Source location for debugging.
557 /// @param DstReg Virtual register to be defined by select instruction.
558 /// @param Cond Condition as computed by AnalyzeBranch.
559 /// @param TrueReg Virtual register to copy when Cond is true.
560 /// @param FalseReg Virtual register to copy when Cons is false.
561 virtual void insertSelect(MachineBasicBlock &MBB,
562 MachineBasicBlock::iterator I, DebugLoc DL,
564 const SmallVectorImpl<MachineOperand> &Cond,
565 unsigned TrueReg, unsigned FalseReg) const {
566 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
569 /// analyzeSelect - Analyze the given select instruction, returning true if
570 /// it cannot be understood. It is assumed that MI->isSelect() is true.
572 /// When successful, return the controlling condition and the operands that
573 /// determine the true and false result values.
575 /// Result = SELECT Cond, TrueOp, FalseOp
577 /// Some targets can optimize select instructions, for example by predicating
578 /// the instruction defining one of the operands. Such targets should set
581 /// @param MI Select instruction to analyze.
582 /// @param Cond Condition controlling the select.
583 /// @param TrueOp Operand number of the value selected when Cond is true.
584 /// @param FalseOp Operand number of the value selected when Cond is false.
585 /// @param Optimizable Returned as true if MI is optimizable.
586 /// @returns False on success.
587 virtual bool analyzeSelect(const MachineInstr *MI,
588 SmallVectorImpl<MachineOperand> &Cond,
589 unsigned &TrueOp, unsigned &FalseOp,
590 bool &Optimizable) const {
591 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
595 /// optimizeSelect - Given a select instruction that was understood by
596 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
597 /// merging it with one of its operands. Returns NULL on failure.
599 /// When successful, returns the new select instruction. The client is
600 /// responsible for deleting MI.
602 /// If both sides of the select can be optimized, PreferFalse is used to pick
605 /// @param MI Optimizable select instruction.
606 /// @param NewMIs Set that record all MIs in the basic block up to \p
607 /// MI. Has to be updated with any newly created MI or deleted ones.
608 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
609 /// @returns Optimized instruction or NULL.
610 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
611 SmallPtrSetImpl<MachineInstr *> &NewMIs,
612 bool PreferFalse = false) const {
613 // This function must be implemented if Optimizable is ever set.
614 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
617 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
619 /// This function should support copies within any legal register class as
620 /// well as any cross-class copies created during instruction selection.
622 /// The source and destination registers may overlap, which may require a
623 /// careful implementation when multiple copy instructions are required for
624 /// large registers. See for example the ARM target.
625 virtual void copyPhysReg(MachineBasicBlock &MBB,
626 MachineBasicBlock::iterator MI, DebugLoc DL,
627 unsigned DestReg, unsigned SrcReg,
628 bool KillSrc) const {
629 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
632 /// storeRegToStackSlot - Store the specified register of the given register
633 /// class to the specified stack frame index. The store instruction is to be
634 /// added to the given machine basic block before the specified machine
635 /// instruction. If isKill is true, the register operand is the last use and
636 /// must be marked kill.
637 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
638 MachineBasicBlock::iterator MI,
639 unsigned SrcReg, bool isKill, int FrameIndex,
640 const TargetRegisterClass *RC,
641 const TargetRegisterInfo *TRI) const {
642 llvm_unreachable("Target didn't implement "
643 "TargetInstrInfo::storeRegToStackSlot!");
646 /// loadRegFromStackSlot - Load the specified register of the given register
647 /// class from the specified stack frame index. The load instruction is to be
648 /// added to the given machine basic block before the specified machine
650 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator MI,
652 unsigned DestReg, int FrameIndex,
653 const TargetRegisterClass *RC,
654 const TargetRegisterInfo *TRI) const {
655 llvm_unreachable("Target didn't implement "
656 "TargetInstrInfo::loadRegFromStackSlot!");
659 /// expandPostRAPseudo - This function is called for all pseudo instructions
660 /// that remain after register allocation. Many pseudo instructions are
661 /// created to help register allocation. This is the place to convert them
662 /// into real instructions. The target can edit MI in place, or it can insert
663 /// new instructions and erase MI. The function should return true if
664 /// anything was changed.
665 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
669 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
670 /// slot into the specified machine instruction for the specified operand(s).
671 /// If this is possible, a new instruction is returned with the specified
672 /// operand folded, otherwise NULL is returned.
673 /// The new instruction is inserted before MI, and the client is responsible
674 /// for removing the old instruction.
675 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
676 ArrayRef<unsigned> Ops, int FrameIndex) const;
678 /// foldMemoryOperand - Same as the previous version except it allows folding
679 /// of any load and store from / to any address, not just from a specific
681 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
682 ArrayRef<unsigned> Ops,
683 MachineInstr *LoadMI) const;
685 /// hasPattern - return true when there is potentially a faster code sequence
686 /// for an instruction chain ending in \p Root. All potential pattern are
687 /// returned in the \p Pattern vector. Pattern should be sorted in priority
688 /// order since the pattern evaluator stops checking as soon as it finds a
690 /// \param Root - Instruction that could be combined with one of its operands
691 /// \param Pattern - Vector of possible combination pattern
693 virtual bool hasPattern(
695 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
699 /// genAlternativeCodeSequence - when hasPattern() finds a pattern this
700 /// function generates the instructions that could replace the original code
701 /// sequence. The client has to decide whether the actual replacementment is
702 /// beneficial or not.
703 /// \param Root - Instruction that could be combined with one of its operands
704 /// \param P - Combination pattern for Root
705 /// \param InsInstrs - Vector of new instructions that implement P
706 /// \param DelInstrs - Old instructions, including Root, that could be replaced
708 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
709 /// InsInstr that defines it
710 virtual void genAlternativeCodeSequence(
711 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
712 SmallVectorImpl<MachineInstr *> &InsInstrs,
713 SmallVectorImpl<MachineInstr *> &DelInstrs,
714 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
718 /// useMachineCombiner - return true when a target supports MachineCombiner
719 virtual bool useMachineCombiner() const { return false; }
722 /// foldMemoryOperandImpl - Target-dependent implementation for
723 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
724 /// take care of adding a MachineMemOperand to the newly created instruction.
725 virtual MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
727 ArrayRef<unsigned> Ops,
728 int FrameIndex) const {
732 /// foldMemoryOperandImpl - Target-dependent implementation for
733 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
734 /// take care of adding a MachineMemOperand to the newly created instruction.
735 virtual MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
737 ArrayRef<unsigned> Ops,
738 MachineInstr *LoadMI) const {
742 /// \brief Target-dependent implementation of getRegSequenceInputs.
744 /// \returns true if it is possible to build the equivalent
745 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
747 /// \pre MI.isRegSequenceLike().
749 /// \see TargetInstrInfo::getRegSequenceInputs.
750 virtual bool getRegSequenceLikeInputs(
751 const MachineInstr &MI, unsigned DefIdx,
752 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
756 /// \brief Target-dependent implementation of getExtractSubregInputs.
758 /// \returns true if it is possible to build the equivalent
759 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
761 /// \pre MI.isExtractSubregLike().
763 /// \see TargetInstrInfo::getExtractSubregInputs.
764 virtual bool getExtractSubregLikeInputs(
765 const MachineInstr &MI, unsigned DefIdx,
766 RegSubRegPairAndIdx &InputReg) const {
770 /// \brief Target-dependent implementation of getInsertSubregInputs.
772 /// \returns true if it is possible to build the equivalent
773 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
775 /// \pre MI.isInsertSubregLike().
777 /// \see TargetInstrInfo::getInsertSubregInputs.
779 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
780 RegSubRegPair &BaseReg,
781 RegSubRegPairAndIdx &InsertedReg) const {
786 /// canFoldMemoryOperand - Returns true for the specified load / store if
787 /// folding is possible.
788 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
789 ArrayRef<unsigned> Ops) const;
791 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
792 /// a store or a load and a store into two or more instruction. If this is
793 /// possible, returns true as well as the new instructions by reference.
794 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
795 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
796 SmallVectorImpl<MachineInstr*> &NewMIs) const{
800 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
801 SmallVectorImpl<SDNode*> &NewNodes) const {
805 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
806 /// instruction after load / store are unfolded from an instruction of the
807 /// specified opcode. It returns zero if the specified unfolding is not
808 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
809 /// index of the operand which will hold the register holding the loaded
811 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
812 bool UnfoldLoad, bool UnfoldStore,
813 unsigned *LoadRegIndex = nullptr) const {
817 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
818 /// to determine if two loads are loading from the same base address. It
819 /// should only return true if the base pointers are the same and the
820 /// only differences between the two addresses are the offset. It also returns
821 /// the offsets by reference.
822 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
823 int64_t &Offset1, int64_t &Offset2) const {
827 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
828 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
829 /// be scheduled togther. On some targets if two loads are loading from
830 /// addresses in the same cache line, it's better if they are scheduled
831 /// together. This function takes two integers that represent the load offsets
832 /// from the common base address. It returns true if it decides it's desirable
833 /// to schedule the two loads together. "NumLoads" is the number of loads that
834 /// have already been scheduled after Load1.
835 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
836 int64_t Offset1, int64_t Offset2,
837 unsigned NumLoads) const {
841 /// \brief Get the base register and byte offset of a load/store instr.
842 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
843 unsigned &BaseReg, unsigned &Offset,
844 const TargetRegisterInfo *TRI) const {
848 virtual bool enableClusterLoads() const { return false; }
850 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
851 MachineInstr *SecondLdSt,
852 unsigned NumLoads) const {
856 /// \brief Can this target fuse the given instructions if they are scheduled
858 virtual bool shouldScheduleAdjacent(MachineInstr* First,
859 MachineInstr *Second) const {
863 /// ReverseBranchCondition - Reverses the branch condition of the specified
864 /// condition list, returning false on success and true if it cannot be
867 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
871 /// insertNoop - Insert a noop into the instruction stream at the specified
873 virtual void insertNoop(MachineBasicBlock &MBB,
874 MachineBasicBlock::iterator MI) const;
877 /// Return the noop instruction to use for a noop.
878 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
881 /// isPredicated - Returns true if the instruction is already predicated.
883 virtual bool isPredicated(const MachineInstr *MI) const {
887 /// isUnpredicatedTerminator - Returns true if the instruction is a
888 /// terminator instruction that has not been predicated.
889 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
891 /// PredicateInstruction - Convert the instruction into a predicated
892 /// instruction. It returns true if the operation was successful.
894 bool PredicateInstruction(MachineInstr *MI,
895 const SmallVectorImpl<MachineOperand> &Pred) const;
897 /// SubsumesPredicate - Returns true if the first specified predicate
898 /// subsumes the second, e.g. GE subsumes GT.
900 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
901 const SmallVectorImpl<MachineOperand> &Pred2) const {
905 /// DefinesPredicate - If the specified instruction defines any predicate
906 /// or condition code register(s) used for predication, returns true as well
907 /// as the definition predicate(s) by reference.
908 virtual bool DefinesPredicate(MachineInstr *MI,
909 std::vector<MachineOperand> &Pred) const {
913 /// isPredicable - Return true if the specified instruction can be predicated.
914 /// By default, this returns true for every instruction with a
915 /// PredicateOperand.
916 virtual bool isPredicable(MachineInstr *MI) const {
917 return MI->getDesc().isPredicable();
920 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
921 /// instruction that defines the specified register class.
922 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
926 /// isSchedulingBoundary - Test if the given instruction should be
927 /// considered a scheduling boundary. This primarily includes labels and
929 virtual bool isSchedulingBoundary(const MachineInstr *MI,
930 const MachineBasicBlock *MBB,
931 const MachineFunction &MF) const;
933 /// Measure the specified inline asm to determine an approximation of its
935 virtual unsigned getInlineAsmLength(const char *Str,
936 const MCAsmInfo &MAI) const;
938 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
939 /// use for this target when scheduling the machine instructions before
940 /// register allocation.
941 virtual ScheduleHazardRecognizer*
942 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
943 const ScheduleDAG *DAG) const;
945 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer
946 /// to use for this target when scheduling the machine instructions before
947 /// register allocation.
948 virtual ScheduleHazardRecognizer*
949 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
950 const ScheduleDAG *DAG) const;
952 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
953 /// recognizer to use for this target when scheduling the machine instructions
954 /// after register allocation.
955 virtual ScheduleHazardRecognizer*
956 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
957 const ScheduleDAG *DAG) const;
959 /// Provide a global flag for disabling the PreRA hazard recognizer that
960 /// targets may choose to honor.
961 bool usePreRAHazardRecognizer() const;
963 /// analyzeCompare - For a comparison instruction, return the source registers
964 /// in SrcReg and SrcReg2 if having two register operands, and the value it
965 /// compares against in CmpValue. Return true if the comparison instruction
967 virtual bool analyzeCompare(const MachineInstr *MI,
968 unsigned &SrcReg, unsigned &SrcReg2,
969 int &Mask, int &Value) const {
973 /// optimizeCompareInstr - See if the comparison instruction can be converted
974 /// into something more efficient. E.g., on ARM most instructions can set the
975 /// flags register, obviating the need for a separate CMP.
976 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
977 unsigned SrcReg, unsigned SrcReg2,
979 const MachineRegisterInfo *MRI) const {
982 virtual bool optimizeCondBranch(MachineInstr *MI) const { return false; }
984 /// optimizeLoadInstr - Try to remove the load by folding it to a register
985 /// operand at the use. We fold the load instructions if and only if the
986 /// def and use are in the same BB. We only look at one load and see
987 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
988 /// defined by the load we are trying to fold. DefMI returns the machine
989 /// instruction that defines FoldAsLoadDefReg, and the function returns
990 /// the machine instruction generated due to folding.
991 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
992 const MachineRegisterInfo *MRI,
993 unsigned &FoldAsLoadDefReg,
994 MachineInstr *&DefMI) const {
998 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
999 /// instruction, try to fold the immediate into the use instruction.
1000 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1001 /// then the caller may assume that DefMI has been erased from its parent
1002 /// block. The caller may assume that it will not be erased by this
1003 /// function otherwise.
1004 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1005 unsigned Reg, MachineRegisterInfo *MRI) const {
1009 /// getNumMicroOps - Return the number of u-operations the given machine
1010 /// instruction will be decoded to on the target cpu. The itinerary's
1011 /// IssueWidth is the number of microops that can be dispatched each
1012 /// cycle. An instruction with zero microops takes no dispatch resources.
1013 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1014 const MachineInstr *MI) const;
1016 /// isZeroCost - Return true for pseudo instructions that don't consume any
1017 /// machine resources in their current form. These are common cases that the
1018 /// scheduler should consider free, rather than conservatively handling them
1019 /// as instructions with no itinerary.
1020 bool isZeroCost(unsigned Opcode) const {
1021 return Opcode <= TargetOpcode::COPY;
1024 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1025 SDNode *DefNode, unsigned DefIdx,
1026 SDNode *UseNode, unsigned UseIdx) const;
1028 /// getOperandLatency - Compute and return the use operand latency of a given
1029 /// pair of def and use.
1030 /// In most cases, the static scheduling itinerary was enough to determine the
1031 /// operand latency. But it may not be possible for instructions with variable
1032 /// number of defs / uses.
1034 /// This is a raw interface to the itinerary that may be directly overriden by
1035 /// a target. Use computeOperandLatency to get the best estimate of latency.
1036 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1037 const MachineInstr *DefMI, unsigned DefIdx,
1038 const MachineInstr *UseMI,
1039 unsigned UseIdx) const;
1041 /// computeOperandLatency - Compute and return the latency of the given data
1042 /// dependent def and use when the operand indices are already known.
1043 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
1044 const MachineInstr *DefMI, unsigned DefIdx,
1045 const MachineInstr *UseMI, unsigned UseIdx)
1048 /// getInstrLatency - Compute the instruction latency of a given instruction.
1049 /// If the instruction has higher cost when predicated, it's returned via
1051 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1052 const MachineInstr *MI,
1053 unsigned *PredCost = nullptr) const;
1055 virtual unsigned getPredicationCost(const MachineInstr *MI) const;
1057 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1058 SDNode *Node) const;
1060 /// Return the default expected latency for a def based on it's opcode.
1061 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1062 const MachineInstr *DefMI) const;
1064 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1065 const MachineInstr *DefMI) const;
1067 /// isHighLatencyDef - Return true if this opcode has high latency to its
1069 virtual bool isHighLatencyDef(int opc) const { return false; }
1071 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
1072 /// and an use in the current loop, return true if the target considered
1073 /// it 'high'. This is used by optimization passes such as machine LICM to
1074 /// determine whether it makes sense to hoist an instruction out even in
1075 /// high register pressure situation.
1077 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
1078 const MachineRegisterInfo *MRI,
1079 const MachineInstr *DefMI, unsigned DefIdx,
1080 const MachineInstr *UseMI, unsigned UseIdx) const {
1084 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
1085 /// if the target considered it 'low'.
1087 bool hasLowDefLatency(const InstrItineraryData *ItinData,
1088 const MachineInstr *DefMI, unsigned DefIdx) const;
1090 /// verifyInstruction - Perform target specific instruction verification.
1092 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
1096 /// getExecutionDomain - Return the current execution domain and bit mask of
1097 /// possible domains for instruction.
1099 /// Some micro-architectures have multiple execution domains, and multiple
1100 /// opcodes that perform the same operation in different domains. For
1101 /// example, the x86 architecture provides the por, orps, and orpd
1102 /// instructions that all do the same thing. There is a latency penalty if a
1103 /// register is written in one domain and read in another.
1105 /// This function returns a pair (domain, mask) containing the execution
1106 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1107 /// function can be used to change the opcode to one of the domains in the
1108 /// bit mask. Instructions whose execution domain can't be changed should
1109 /// return a 0 mask.
1111 /// The execution domain numbers don't have any special meaning except domain
1112 /// 0 is used for instructions that are not associated with any interesting
1113 /// execution domain.
1115 virtual std::pair<uint16_t, uint16_t>
1116 getExecutionDomain(const MachineInstr *MI) const {
1117 return std::make_pair(0, 0);
1120 /// setExecutionDomain - Change the opcode of MI to execute in Domain.
1122 /// The bit (1 << Domain) must be set in the mask returned from
1123 /// getExecutionDomain(MI).
1125 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
1128 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance
1129 /// before an instruction with an unwanted partial register update.
1131 /// Some instructions only write part of a register, and implicitly need to
1132 /// read the other parts of the register. This may cause unwanted stalls
1133 /// preventing otherwise unrelated instructions from executing in parallel in
1134 /// an out-of-order CPU.
1136 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1137 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1138 /// the instruction needs to wait for the old value of the register to become
1141 /// addps %xmm1, %xmm0
1142 /// movaps %xmm0, (%rax)
1143 /// cvtsi2ss %rbx, %xmm0
1145 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1146 /// instruction before it can issue, even though the high bits of %xmm0
1147 /// probably aren't needed.
1149 /// This hook returns the preferred clearance before MI, measured in
1150 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1151 /// instructions before MI. It should only return a positive value for
1152 /// unwanted dependencies. If the old bits of the defined register have
1153 /// useful values, or if MI is determined to otherwise read the dependency,
1154 /// the hook should return 0.
1156 /// The unwanted dependency may be handled by:
1158 /// 1. Allocating the same register for an MI def and use. That makes the
1159 /// unwanted dependency identical to a required dependency.
1161 /// 2. Allocating a register for the def that has no defs in the previous N
1164 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1165 /// allows the target to insert a dependency breaking instruction.
1168 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
1169 const TargetRegisterInfo *TRI) const {
1170 // The default implementation returns 0 for no partial register dependency.
1174 /// \brief Return the minimum clearance before an instruction that reads an
1175 /// unused register.
1177 /// For example, AVX instructions may copy part of an register operand into
1178 /// the unused high bits of the destination register.
1180 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1182 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1183 /// false dependence on any previous write to %xmm0.
1185 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1186 /// does not take an operand index. Instead sets \p OpNum to the index of the
1187 /// unused register.
1188 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
1189 const TargetRegisterInfo *TRI) const {
1190 // The default implementation returns 0 for no undef register dependency.
1194 /// breakPartialRegDependency - Insert a dependency-breaking instruction
1195 /// before MI to eliminate an unwanted dependency on OpNum.
1197 /// If it wasn't possible to avoid a def in the last N instructions before MI
1198 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1199 /// unwanted dependency.
1201 /// On x86, an xorps instruction can be used as a dependency breaker:
1203 /// addps %xmm1, %xmm0
1204 /// movaps %xmm0, (%rax)
1205 /// xorps %xmm0, %xmm0
1206 /// cvtsi2ss %rbx, %xmm0
1208 /// An <imp-kill> operand should be added to MI if an instruction was
1209 /// inserted. This ties the instructions together in the post-ra scheduler.
1212 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
1213 const TargetRegisterInfo *TRI) const {}
1215 /// Create machine specific model for scheduling.
1216 virtual DFAPacketizer *
1217 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1221 // areMemAccessesTriviallyDisjoint - Sometimes, it is possible for the target
1222 // to tell, even without aliasing information, that two MIs access different
1223 // memory addresses. This function returns true if two MIs access different
1224 // memory addresses, and false otherwise.
1226 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
1227 AliasAnalysis *AA = nullptr) const {
1228 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1229 "MIa must load from or modify a memory location");
1230 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1231 "MIb must load from or modify a memory location");
1236 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
1239 } // End llvm namespace