1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
23 class TargetRegisterClass;
24 class TargetRegisterInfo;
26 class CalleeSavedInfo;
30 template<class T> class SmallVectorImpl;
33 //---------------------------------------------------------------------------
35 /// TargetInstrInfo - Interface to description of machine instruction set
37 class TargetInstrInfo {
38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
39 unsigned NumOpcodes; // Number of entries in the desc array
41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
45 virtual ~TargetInstrInfo();
47 // Invariant opcodes: All instruction sets have these as their low opcodes.
54 // FIXME: DECLARE is removed. Readjust enum values ?
56 /// EXTRACT_SUBREG - This instruction takes two operands: a register
57 /// that has subregisters, and a subregister index. It returns the
58 /// extracted subregister value. This is commonly used to implement
59 /// truncation operations on target architectures which support it.
62 /// INSERT_SUBREG - This instruction takes three operands: a register
63 /// that has subregisters, a register providing an insert value, and a
64 /// subregister index. It returns the value of the first register with
65 /// the value of the second register inserted. The first register is
66 /// often defined by an IMPLICIT_DEF, as is commonly used to implement
67 /// anyext operations on target architectures which support it.
70 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
73 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
74 /// that the first operand is an immediate integer constant. This constant
75 /// is often zero, as is commonly used to implement zext operations on
76 /// target architectures which support it, such as with x86-64 (with
77 /// zext from i32 to i64 via implicit zero-extension).
80 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
81 /// register-to-register copy into a specific register class. This is only
82 /// used between instruction selection and MachineInstr creation, before
83 /// virtual registers have been created for all the instructions, and it's
84 /// only needed in cases where the register classes implied by the
85 /// instructions are insufficient. The actual MachineInstrs to perform
86 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
90 unsigned getNumOpcodes() const { return NumOpcodes; }
92 /// get - Return the machine instruction descriptor that corresponds to the
93 /// specified instruction opcode.
95 const TargetInstrDesc &get(unsigned Opcode) const {
96 assert(Opcode < NumOpcodes && "Invalid opcode!");
97 return Descriptors[Opcode];
100 /// isTriviallyReMaterializable - Return true if the instruction is trivially
101 /// rematerializable, meaning it has no side effects and requires no operands
102 /// that aren't always available.
103 bool isTriviallyReMaterializable(const MachineInstr *MI) const {
104 return MI->getDesc().isRematerializable() &&
105 isReallyTriviallyReMaterializable(MI);
109 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
110 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
111 /// instruction itself is actually trivially rematerializable, considering
112 /// its operands. This is used for targets that have instructions that are
113 /// only trivially rematerializable for specific uses. This predicate must
114 /// return false if the instruction has any side effects other than
115 /// producing a value, or if it requres any address registers that are not
116 /// always available.
117 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
122 /// Return true if the instruction is a register to register move and return
123 /// the source and dest operands and their sub-register indices by reference.
124 virtual bool isMoveInstr(const MachineInstr& MI,
125 unsigned& SrcReg, unsigned& DstReg,
126 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
130 /// isLoadFromStackSlot - If the specified machine instruction is a direct
131 /// load from a stack slot, return the virtual or physical register number of
132 /// the destination along with the FrameIndex of the loaded stack slot. If
133 /// not, return 0. This predicate must return 0 if the instruction has
134 /// any side effects other than loading from the stack slot.
135 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
136 int &FrameIndex) const {
140 /// isStoreToStackSlot - If the specified machine instruction is a direct
141 /// store to a stack slot, return the virtual or physical register number of
142 /// the source reg along with the FrameIndex of the loaded stack slot. If
143 /// not, return 0. This predicate must return 0 if the instruction has
144 /// any side effects other than storing to the stack slot.
145 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
146 int &FrameIndex) const {
150 /// reMaterialize - Re-issue the specified 'original' instruction at the
151 /// specific location targeting a new destination register.
152 virtual void reMaterialize(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator MI,
154 unsigned DestReg, unsigned SubIdx,
155 const MachineInstr *Orig) const = 0;
157 /// isInvariantLoad - Return true if the specified instruction (which is
158 /// marked mayLoad) is loading from a location whose value is invariant across
159 /// the function. For example, loading a value from the constant pool or from
160 /// from the argument area of a function if it does not change. This should
161 /// only return true of *all* loads the instruction does are invariant (if it
162 /// does multiple loads).
163 virtual bool isInvariantLoad(const MachineInstr *MI) const {
167 /// convertToThreeAddress - This method must be implemented by targets that
168 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
169 /// may be able to convert a two-address instruction into one or more true
170 /// three-address instructions on demand. This allows the X86 target (for
171 /// example) to convert ADD and SHL instructions into LEA instructions if they
172 /// would require register copies due to two-addressness.
174 /// This method returns a null pointer if the transformation cannot be
175 /// performed, otherwise it returns the last new instruction.
177 virtual MachineInstr *
178 convertToThreeAddress(MachineFunction::iterator &MFI,
179 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
183 /// commuteInstruction - If a target has any instructions that are commutable,
184 /// but require converting to a different instruction or making non-trivial
185 /// changes to commute them, this method can overloaded to do this. The
186 /// default implementation of this method simply swaps the first two operands
187 /// of MI and returns it.
189 /// If a target wants to make more aggressive changes, they can construct and
190 /// return a new machine instruction. If an instruction cannot commute, it
191 /// can also return null.
193 /// If NewMI is true, then a new machine instruction must be created.
195 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
196 bool NewMI = false) const = 0;
198 /// findCommutedOpIndices - If specified MI is commutable, return the two
199 /// operand indices that would swap value. Return true if the instruction
200 /// is not in a form which this routine understands.
201 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
202 unsigned &SrcOpIdx2) const = 0;
204 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
205 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
206 /// implemented for a target). Upon success, this returns false and returns
207 /// with the following information in various cases:
209 /// 1. If this block ends with no branches (it just falls through to its succ)
210 /// just return false, leaving TBB/FBB null.
211 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
212 /// the destination block.
213 /// 3. If this block ends with an conditional branch and it falls through to
214 /// a successor block, it sets TBB to be the branch destination block and
215 /// a list of operands that evaluate the condition. These
216 /// operands can be passed to other TargetInstrInfo methods to create new
218 /// 4. If this block ends with a conditional branch followed by an
219 /// unconditional branch, it returns the 'true' destination in TBB, the
220 /// 'false' destination in FBB, and a list of operands that evaluate the
221 /// condition. These operands can be passed to other TargetInstrInfo
222 /// methods to create new branches.
224 /// Note that RemoveBranch and InsertBranch must be implemented to support
225 /// cases where this method returns success.
227 /// If AllowModify is true, then this routine is allowed to modify the basic
228 /// block (e.g. delete instructions after the unconditional branch).
230 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
231 MachineBasicBlock *&FBB,
232 SmallVectorImpl<MachineOperand> &Cond,
233 bool AllowModify = false) const {
237 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
238 /// This is only invoked in cases where AnalyzeBranch returns success. It
239 /// returns the number of instructions that were removed.
240 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
241 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
245 /// InsertBranch - Insert branch code into the end of the specified
246 /// MachineBasicBlock. The operands to this method are the same as those
247 /// returned by AnalyzeBranch. This is only invoked in cases where
248 /// AnalyzeBranch returns success. It returns the number of instructions
251 /// It is also invoked by tail merging to add unconditional branches in
252 /// cases where AnalyzeBranch doesn't apply because there was no original
253 /// branch to analyze. At least this much must be implemented, else tail
254 /// merging needs to be disabled.
255 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
256 MachineBasicBlock *FBB,
257 const SmallVectorImpl<MachineOperand> &Cond) const {
258 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
262 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
263 /// returns false if the target does not how to copy between the specified
265 virtual bool copyRegToReg(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator MI,
267 unsigned DestReg, unsigned SrcReg,
268 const TargetRegisterClass *DestRC,
269 const TargetRegisterClass *SrcRC) const {
270 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
274 /// storeRegToStackSlot - Store the specified register of the given register
275 /// class to the specified stack frame index. The store instruction is to be
276 /// added to the given machine basic block before the specified machine
277 /// instruction. If isKill is true, the register operand is the last use and
278 /// must be marked kill.
279 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
280 MachineBasicBlock::iterator MI,
281 unsigned SrcReg, bool isKill, int FrameIndex,
282 const TargetRegisterClass *RC) const {
283 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
286 /// loadRegFromStackSlot - Load the specified register of the given register
287 /// class from the specified stack frame index. The load instruction is to be
288 /// added to the given machine basic block before the specified machine
290 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator MI,
292 unsigned DestReg, int FrameIndex,
293 const TargetRegisterClass *RC) const {
294 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
297 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
298 /// saved registers and returns true if it isn't possible / profitable to do
299 /// so by issuing a series of store instructions via
300 /// storeRegToStackSlot(). Returns false otherwise.
301 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
302 MachineBasicBlock::iterator MI,
303 const std::vector<CalleeSavedInfo> &CSI) const {
307 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
308 /// saved registers and returns true if it isn't possible / profitable to do
309 /// so by issuing a series of load instructions via loadRegToStackSlot().
310 /// Returns false otherwise.
311 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MI,
313 const std::vector<CalleeSavedInfo> &CSI) const {
317 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
318 /// slot into the specified machine instruction for the specified operand(s).
319 /// If this is possible, a new instruction is returned with the specified
320 /// operand folded, otherwise NULL is returned. The client is responsible for
321 /// removing the old instruction and adding the new one in the instruction
323 MachineInstr* foldMemoryOperand(MachineFunction &MF,
325 const SmallVectorImpl<unsigned> &Ops,
326 int FrameIndex) const;
328 /// foldMemoryOperand - Same as the previous version except it allows folding
329 /// of any load and store from / to any address, not just from a specific
331 MachineInstr* foldMemoryOperand(MachineFunction &MF,
333 const SmallVectorImpl<unsigned> &Ops,
334 MachineInstr* LoadMI) const;
337 /// foldMemoryOperandImpl - Target-dependent implementation for
338 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
339 /// take care of adding a MachineMemOperand to the newly created instruction.
340 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
342 const SmallVectorImpl<unsigned> &Ops,
343 int FrameIndex) const {
347 /// foldMemoryOperandImpl - Target-dependent implementation for
348 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
349 /// take care of adding a MachineMemOperand to the newly created instruction.
350 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
352 const SmallVectorImpl<unsigned> &Ops,
353 MachineInstr* LoadMI) const {
358 /// canFoldMemoryOperand - Returns true for the specified load / store if
359 /// folding is possible.
361 bool canFoldMemoryOperand(const MachineInstr *MI,
362 const SmallVectorImpl<unsigned> &Ops) const {
366 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
367 /// a store or a load and a store into two or more instruction. If this is
368 /// possible, returns true as well as the new instructions by reference.
369 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
370 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
371 SmallVectorImpl<MachineInstr*> &NewMIs) const{
375 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
376 SmallVectorImpl<SDNode*> &NewNodes) const {
380 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
381 /// instruction after load / store are unfolded from an instruction of the
382 /// specified opcode. It returns zero if the specified unfolding is not
384 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
385 bool UnfoldLoad, bool UnfoldStore) const {
389 /// BlockHasNoFallThrough - Return true if the specified block does not
390 /// fall-through into its successor block. This is primarily used when a
391 /// branch is unanalyzable. It is useful for things like unconditional
392 /// indirect branches (jump tables).
393 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
397 /// ReverseBranchCondition - Reverses the branch condition of the specified
398 /// condition list, returning false on success and true if it cannot be
401 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
405 /// insertNoop - Insert a noop into the instruction stream at the specified
407 virtual void insertNoop(MachineBasicBlock &MBB,
408 MachineBasicBlock::iterator MI) const;
410 /// isPredicated - Returns true if the instruction is already predicated.
412 virtual bool isPredicated(const MachineInstr *MI) const {
416 /// isUnpredicatedTerminator - Returns true if the instruction is a
417 /// terminator instruction that has not been predicated.
418 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
420 /// PredicateInstruction - Convert the instruction into a predicated
421 /// instruction. It returns true if the operation was successful.
423 bool PredicateInstruction(MachineInstr *MI,
424 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
426 /// SubsumesPredicate - Returns true if the first specified predicate
427 /// subsumes the second, e.g. GE subsumes GT.
429 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
430 const SmallVectorImpl<MachineOperand> &Pred2) const {
434 /// DefinesPredicate - If the specified instruction defines any predicate
435 /// or condition code register(s) used for predication, returns true as well
436 /// as the definition predicate(s) by reference.
437 virtual bool DefinesPredicate(MachineInstr *MI,
438 std::vector<MachineOperand> &Pred) const {
442 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
443 /// instruction that defines the specified register class.
444 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
448 /// isDeadInstruction - Return true if the instruction is considered dead.
449 /// This allows some late codegen passes to delete them.
450 virtual bool isDeadInstruction(const MachineInstr *MI) const = 0;
452 /// GetInstSize - Returns the size of the specified Instruction.
454 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
455 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
459 /// GetFunctionSizeInBytes - Returns the size of the specified
462 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
464 /// Measure the specified inline asm to determine an approximation of its
466 virtual unsigned getInlineAsmLength(const char *Str,
467 const MCAsmInfo &MAI) const;
470 /// TargetInstrInfoImpl - This is the default implementation of
471 /// TargetInstrInfo, which just provides a couple of default implementations
472 /// for various methods. This separated out because it is implemented in
473 /// libcodegen, not in libtarget.
474 class TargetInstrInfoImpl : public TargetInstrInfo {
476 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
477 : TargetInstrInfo(desc, NumOpcodes) {}
479 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
480 bool NewMI = false) const;
481 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
482 unsigned &SrcOpIdx2) const;
483 virtual bool PredicateInstruction(MachineInstr *MI,
484 const SmallVectorImpl<MachineOperand> &Pred) const;
485 virtual void reMaterialize(MachineBasicBlock &MBB,
486 MachineBasicBlock::iterator MI,
487 unsigned DestReg, unsigned SubReg,
488 const MachineInstr *Orig) const;
489 virtual bool isDeadInstruction(const MachineInstr *MI) const;
491 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
494 } // End llvm namespace