1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class MachineCodeForInstruction;
28 class TargetRegisterClass;
31 //---------------------------------------------------------------------------
32 // Data types used to define information about a single machine instruction
33 //---------------------------------------------------------------------------
35 typedef short MachineOpCode;
36 typedef unsigned InstrSchedClass;
38 //---------------------------------------------------------------------------
39 // struct TargetInstrDescriptor:
40 // Predefined information about each machine instruction.
41 // Designed to initialized statically.
44 const unsigned M_BRANCH_FLAG = 1 << 0;
45 const unsigned M_CALL_FLAG = 1 << 1;
46 const unsigned M_RET_FLAG = 1 << 2;
47 const unsigned M_BARRIER_FLAG = 1 << 3;
48 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
49 const unsigned M_LOAD_FLAG = 1 << 5;
50 const unsigned M_STORE_FLAG = 1 << 6;
52 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
53 // changed into a 3-address instruction if the first two operands cannot be
54 // assigned to the same register. The target must implement the
55 // TargetInstrInfo::convertToThreeAddress method for this instruction.
56 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
58 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
59 // Z), which produces the same result if Y and Z are exchanged.
60 const unsigned M_COMMUTABLE = 1 << 8;
62 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
63 // block? Typically this is things like return and branch instructions.
64 // Various passes use this to insert code into the bottom of a basic block, but
65 // before control flow occurs.
66 const unsigned M_TERMINATOR_FLAG = 1 << 9;
68 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
69 // insertion support when the DAG scheduler is inserting it into a machine basic
71 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
73 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
74 // operands in addition to the minimum number operands specified.
75 const unsigned M_VARIABLE_OPS = 1 << 11;
77 // M_PREDICABLE - Set if this instruction has a predicate operand that
78 // controls execution. It may be set to 'always'.
79 const unsigned M_PREDICABLE = 1 << 12;
81 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
82 // at any time, e.g. constant generation, load from constant pool.
83 const unsigned M_REMATERIALIZIBLE = 1 << 13;
85 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
86 // (e.g. instructions with unique labels attached).
87 const unsigned M_NOT_DUPLICABLE = 1 << 14;
89 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
90 // ARM instructions which can set condition code if 's' bit is set.
91 const unsigned M_HAS_OPTIONAL_DEF = 1 << 15;
93 // Machine operand flags
94 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
95 // requires a callback to look up its register class.
96 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
98 /// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
99 /// predicate operand that controls an M_PREDICATED instruction.
100 const unsigned M_PREDICATE_OPERAND = 1 << 1;
102 /// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
104 const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
107 // Operand constraints: only "tied_to" for now.
108 enum OperandConstraint {
109 TIED_TO = 0 // Must be allocated the same register as.
113 /// TargetOperandInfo - This holds information about one operand of a machine
114 /// instruction, indicating the register class for register operands, etc.
116 class TargetOperandInfo {
118 /// RegClass - This specifies the register class enumeration of the operand
119 /// if the operand is a register. If not, this contains 0.
120 unsigned short RegClass;
121 unsigned short Flags;
122 /// Lower 16 bits are used to specify which constraints are set. The higher 16
123 /// bits are used to specify the value of constraints (4 bits each).
124 unsigned int Constraints;
125 /// Currently no other information.
129 class TargetInstrDescriptor {
131 MachineOpCode Opcode; // The opcode.
132 unsigned short numOperands; // Num of args (may be more if variable_ops).
133 unsigned short numDefs; // Num of args that are definitions.
134 const char * Name; // Assembly language mnemonic for the opcode.
135 InstrSchedClass schedClass; // enum identifying instr sched class
136 unsigned Flags; // flags identifying machine instr class
137 unsigned TSFlags; // Target Specific Flag values
138 const unsigned *ImplicitUses; // Registers implicitly read by this instr
139 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
140 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
142 /// getOperandConstraint - Returns the value of the specific constraint if
143 /// it is set. Returns -1 if it is not set.
144 int getOperandConstraint(unsigned OpNum,
145 TOI::OperandConstraint Constraint) const {
146 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
147 "Invalid operand # of TargetInstrInfo");
148 if (OpNum < numOperands &&
149 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
150 unsigned Pos = 16 + Constraint * 4;
151 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
156 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
157 /// dest operand. Returns -1 if there isn't one.
158 int findTiedToSrcOperand(unsigned OpNum) const;
162 //---------------------------------------------------------------------------
164 /// TargetInstrInfo - Interface to description of machine instructions
166 class TargetInstrInfo {
167 const TargetInstrDescriptor* desc; // raw array to allow static init'n
168 unsigned NumOpcodes; // number of entries in the desc array
169 unsigned numRealOpCodes; // number of non-dummy op codes
171 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
172 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
174 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
175 virtual ~TargetInstrInfo();
177 // Invariant opcodes: All instruction sets have these as their low opcodes.
186 unsigned getNumOpcodes() const { return NumOpcodes; }
188 /// get - Return the machine instruction descriptor that corresponds to the
189 /// specified instruction opcode.
191 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
192 assert((unsigned)Opcode < NumOpcodes);
196 const char *getName(MachineOpCode Opcode) const {
197 return get(Opcode).Name;
200 int getNumOperands(MachineOpCode Opcode) const {
201 return get(Opcode).numOperands;
204 int getNumDefs(MachineOpCode Opcode) const {
205 return get(Opcode).numDefs;
208 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
209 return get(Opcode).schedClass;
212 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
213 return get(Opcode).ImplicitUses;
216 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
217 return get(Opcode).ImplicitDefs;
222 // Query instruction class flags according to the machine-independent
223 // flags listed above.
225 bool isReturn(MachineOpCode Opcode) const {
226 return get(Opcode).Flags & M_RET_FLAG;
229 bool isCommutableInstr(MachineOpCode Opcode) const {
230 return get(Opcode).Flags & M_COMMUTABLE;
232 bool isTerminatorInstr(MachineOpCode Opcode) const {
233 return get(Opcode).Flags & M_TERMINATOR_FLAG;
236 bool isBranch(MachineOpCode Opcode) const {
237 return get(Opcode).Flags & M_BRANCH_FLAG;
240 /// isBarrier - Returns true if the specified instruction stops control flow
241 /// from executing the instruction immediately following it. Examples include
242 /// unconditional branches and return instructions.
243 bool isBarrier(MachineOpCode Opcode) const {
244 return get(Opcode).Flags & M_BARRIER_FLAG;
247 bool isCall(MachineOpCode Opcode) const {
248 return get(Opcode).Flags & M_CALL_FLAG;
250 bool isLoad(MachineOpCode Opcode) const {
251 return get(Opcode).Flags & M_LOAD_FLAG;
253 bool isStore(MachineOpCode Opcode) const {
254 return get(Opcode).Flags & M_STORE_FLAG;
257 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
258 /// which must be filled by the code generator.
259 bool hasDelaySlot(MachineOpCode Opcode) const {
260 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
263 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
264 /// custom insertion support when the DAG scheduler is inserting it into a
265 /// machine basic block.
266 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
267 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
270 bool hasVariableOperands(MachineOpCode Opcode) const {
271 return get(Opcode).Flags & M_VARIABLE_OPS;
274 bool isPredicable(MachineOpCode Opcode) const {
275 return get(Opcode).Flags & M_PREDICABLE;
278 bool isNotDuplicable(MachineOpCode Opcode) const {
279 return get(Opcode).Flags & M_NOT_DUPLICABLE;
282 bool hasOptionalDef(MachineOpCode Opcode) const {
283 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
286 /// isTriviallyReMaterializable - Return true if the instruction is trivially
287 /// rematerializable, meaning it has no side effects and requires no operands
288 /// that aren't always available.
289 bool isTriviallyReMaterializable(MachineInstr *MI) const {
290 return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
291 isReallyTriviallyReMaterializable(MI);
295 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
296 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
297 /// instruction itself is actually trivially rematerializable, considering
298 /// its operands. This is used for targets that have instructions that are
299 /// only trivially rematerializable for specific uses. This predicate must
300 /// return false if the instruction has any side effects other than
301 /// producing a value, or if it requres any address registers that are not
302 /// always available.
303 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
308 /// getOperandConstraint - Returns the value of the specific constraint if
309 /// it is set. Returns -1 if it is not set.
310 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
311 TOI::OperandConstraint Constraint) const {
312 return get(Opcode).getOperandConstraint(OpNum, Constraint);
315 /// Return true if the instruction is a register to register move
316 /// and leave the source and dest operands in the passed parameters.
317 virtual bool isMoveInstr(const MachineInstr& MI,
319 unsigned& destReg) const {
323 /// isLoadFromStackSlot - If the specified machine instruction is a direct
324 /// load from a stack slot, return the virtual or physical register number of
325 /// the destination along with the FrameIndex of the loaded stack slot. If
326 /// not, return 0. This predicate must return 0 if the instruction has
327 /// any side effects other than loading from the stack slot.
328 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
332 /// isStoreToStackSlot - If the specified machine instruction is a direct
333 /// store to a stack slot, return the virtual or physical register number of
334 /// the source reg along with the FrameIndex of the loaded stack slot. If
335 /// not, return 0. This predicate must return 0 if the instruction has
336 /// any side effects other than storing to the stack slot.
337 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
341 /// convertToThreeAddress - This method must be implemented by targets that
342 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
343 /// may be able to convert a two-address instruction into one or more true
344 /// three-address instructions on demand. This allows the X86 target (for
345 /// example) to convert ADD and SHL instructions into LEA instructions if they
346 /// would require register copies due to two-addressness.
348 /// This method returns a null pointer if the transformation cannot be
349 /// performed, otherwise it returns the last new instruction.
351 virtual MachineInstr *
352 convertToThreeAddress(MachineFunction::iterator &MFI,
353 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
357 /// commuteInstruction - If a target has any instructions that are commutable,
358 /// but require converting to a different instruction or making non-trivial
359 /// changes to commute them, this method can overloaded to do this. The
360 /// default implementation of this method simply swaps the first two operands
361 /// of MI and returns it.
363 /// If a target wants to make more aggressive changes, they can construct and
364 /// return a new machine instruction. If an instruction cannot commute, it
365 /// can also return null.
367 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
369 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
370 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
371 /// implemented for a target). Upon success, this returns false and returns
372 /// with the following information in various cases:
374 /// 1. If this block ends with no branches (it just falls through to its succ)
375 /// just return false, leaving TBB/FBB null.
376 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
377 /// the destination block.
378 /// 3. If this block ends with an conditional branch and it falls through to
379 /// an successor block, it sets TBB to be the branch destination block and a
380 /// list of operands that evaluate the condition. These
381 /// operands can be passed to other TargetInstrInfo methods to create new
383 /// 4. If this block ends with an conditional branch and an unconditional
384 /// block, it returns the 'true' destination in TBB, the 'false' destination
385 /// in FBB, and a list of operands that evaluate the condition. These
386 /// operands can be passed to other TargetInstrInfo methods to create new
389 /// Note that RemoveBranch and InsertBranch must be implemented to support
390 /// cases where this method returns success.
392 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
393 MachineBasicBlock *&FBB,
394 std::vector<MachineOperand> &Cond) const {
398 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
399 /// this is only invoked in cases where AnalyzeBranch returns success. It
400 /// returns the number of instructions that were removed.
401 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
402 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
406 /// InsertBranch - Insert a branch into the end of the specified
407 /// MachineBasicBlock. This operands to this method are the same as those
408 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
409 /// returns success and when an unconditional branch (TBB is non-null, FBB is
410 /// null, Cond is empty) needs to be inserted. It returns the number of
411 /// instructions inserted.
412 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
413 MachineBasicBlock *FBB,
414 const std::vector<MachineOperand> &Cond) const {
415 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
419 /// BlockHasNoFallThrough - Return true if the specified block does not
420 /// fall-through into its successor block. This is primarily used when a
421 /// branch is unanalyzable. It is useful for things like unconditional
422 /// indirect branches (jump tables).
423 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
427 /// ReverseBranchCondition - Reverses the branch condition of the specified
428 /// condition list, returning false on success and true if it cannot be
430 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
434 /// insertNoop - Insert a noop into the instruction stream at the specified
436 virtual void insertNoop(MachineBasicBlock &MBB,
437 MachineBasicBlock::iterator MI) const {
438 assert(0 && "Target didn't implement insertNoop!");
442 /// isPredicated - Returns true if the instruction is already predicated.
444 virtual bool isPredicated(const MachineInstr *MI) const {
448 /// isUnpredicatedTerminator - Returns true if the instruction is a
449 /// terminator instruction that has not been predicated.
450 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
452 /// PredicateInstruction - Convert the instruction into a predicated
453 /// instruction. It returns true if the operation was successful.
455 bool PredicateInstruction(MachineInstr *MI,
456 const std::vector<MachineOperand> &Pred) const;
458 /// SubsumesPredicate - Returns true if the first specified predicate
459 /// subsumes the second, e.g. GE subsumes GT.
461 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
462 const std::vector<MachineOperand> &Pred2) const {
466 /// DefinesPredicate - If the specified instruction defines any predicate
467 /// or condition code register(s) used for predication, returns true as well
468 /// as the definition predicate(s) by reference.
469 virtual bool DefinesPredicate(MachineInstr *MI,
470 std::vector<MachineOperand> &Pred) const {
474 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
476 virtual const TargetRegisterClass *getPointerRegClass() const {
477 assert(0 && "Target didn't implement getPointerRegClass!");
479 return 0; // Must return a value in order to compile with VS 2005
483 } // End llvm namespace