1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
32 class MachineCodeForInstruction;
33 class TargetRegisterClass;
36 //---------------------------------------------------------------------------
37 // Data types used to define information about a single machine instruction
38 //---------------------------------------------------------------------------
40 typedef short MachineOpCode;
41 typedef unsigned InstrSchedClass;
43 //---------------------------------------------------------------------------
44 // struct TargetInstrDescriptor:
45 // Predefined information about each machine instruction.
46 // Designed to initialized statically.
49 const unsigned M_BRANCH_FLAG = 1 << 0;
50 const unsigned M_CALL_FLAG = 1 << 1;
51 const unsigned M_RET_FLAG = 1 << 2;
52 const unsigned M_BARRIER_FLAG = 1 << 3;
53 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
54 const unsigned M_LOAD_FLAG = 1 << 5;
55 const unsigned M_STORE_FLAG = 1 << 6;
57 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
58 // changed into a 3-address instruction if the first two operands cannot be
59 // assigned to the same register. The target must implement the
60 // TargetInstrInfo::convertToThreeAddress method for this instruction.
61 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
63 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
64 // Z), which produces the same result if Y and Z are exchanged.
65 const unsigned M_COMMUTABLE = 1 << 8;
67 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
68 // block? Typically this is things like return and branch instructions.
69 // Various passes use this to insert code into the bottom of a basic block, but
70 // before control flow occurs.
71 const unsigned M_TERMINATOR_FLAG = 1 << 9;
73 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
74 // insertion support when the DAG scheduler is inserting it into a machine basic
76 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
78 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
79 // operands in addition to the minimum number operands specified.
80 const unsigned M_VARIABLE_OPS = 1 << 11;
82 // M_PREDICATED - Set if this instruction has a predicate that controls its
84 const unsigned M_PREDICATED = 1 << 12;
87 // Machine operand flags
88 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
89 // requires a callback to look up its register class.
90 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
92 /// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate
93 /// operand that controls an M_PREDICATED instruction.
94 const unsigned M_PREDICATE_OPERAND = 1 << 1;
97 // Operand constraints: only "tied_to" for now.
98 enum OperandConstraint {
99 TIED_TO = 0 // Must be allocated the same register as.
103 /// TargetOperandInfo - This holds information about one operand of a machine
104 /// instruction, indicating the register class for register operands, etc.
106 class TargetOperandInfo {
108 /// RegClass - This specifies the register class enumeration of the operand
109 /// if the operand is a register. If not, this contains 0.
110 unsigned short RegClass;
111 unsigned short Flags;
112 /// Lower 16 bits are used to specify which constraints are set. The higher 16
113 /// bits are used to specify the value of constraints (4 bits each).
114 unsigned int Constraints;
115 /// Currently no other information.
119 class TargetInstrDescriptor {
121 MachineOpCode Opcode; // The opcode.
122 unsigned short numOperands; // Num of args (may be more if variable_ops).
123 const char * Name; // Assembly language mnemonic for the opcode.
124 InstrSchedClass schedClass; // enum identifying instr sched class
125 unsigned Flags; // flags identifying machine instr class
126 unsigned TSFlags; // Target Specific Flag values
127 const unsigned *ImplicitUses; // Registers implicitly read by this instr
128 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
129 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
131 /// getOperandConstraint - Returns the value of the specific constraint if
132 /// it is set. Returns -1 if it is not set.
133 int getOperandConstraint(unsigned OpNum,
134 TOI::OperandConstraint Constraint) const {
135 assert(OpNum < numOperands && "Invalid operand # of TargetInstrInfo");
136 if (OpInfo[OpNum].Constraints & (1 << Constraint)) {
137 unsigned Pos = 16 + Constraint * 4;
138 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
145 //---------------------------------------------------------------------------
147 /// TargetInstrInfo - Interface to description of machine instructions
149 class TargetInstrInfo {
150 const TargetInstrDescriptor* desc; // raw array to allow static init'n
151 unsigned NumOpcodes; // number of entries in the desc array
152 unsigned numRealOpCodes; // number of non-dummy op codes
154 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
155 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
157 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
158 virtual ~TargetInstrInfo();
160 // Invariant opcodes: All instruction sets have these as their low opcodes.
166 unsigned getNumOpcodes() const { return NumOpcodes; }
168 /// get - Return the machine instruction descriptor that corresponds to the
169 /// specified instruction opcode.
171 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
172 assert((unsigned)Opcode < NumOpcodes);
176 const char *getName(MachineOpCode Opcode) const {
177 return get(Opcode).Name;
180 int getNumOperands(MachineOpCode Opcode) const {
181 return get(Opcode).numOperands;
184 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
185 return get(Opcode).schedClass;
188 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
189 return get(Opcode).ImplicitUses;
192 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
193 return get(Opcode).ImplicitDefs;
198 // Query instruction class flags according to the machine-independent
199 // flags listed above.
201 bool isReturn(MachineOpCode Opcode) const {
202 return get(Opcode).Flags & M_RET_FLAG;
205 bool isPredicated(MachineOpCode Opcode) const {
206 return get(Opcode).Flags & M_PREDICATED;
208 bool isCommutableInstr(MachineOpCode Opcode) const {
209 return get(Opcode).Flags & M_COMMUTABLE;
211 bool isTerminatorInstr(unsigned Opcode) const {
212 return get(Opcode).Flags & M_TERMINATOR_FLAG;
215 bool isBranch(MachineOpCode Opcode) const {
216 return get(Opcode).Flags & M_BRANCH_FLAG;
219 /// isBarrier - Returns true if the specified instruction stops control flow
220 /// from executing the instruction immediately following it. Examples include
221 /// unconditional branches and return instructions.
222 bool isBarrier(MachineOpCode Opcode) const {
223 return get(Opcode).Flags & M_BARRIER_FLAG;
226 bool isCall(MachineOpCode Opcode) const {
227 return get(Opcode).Flags & M_CALL_FLAG;
229 bool isLoad(MachineOpCode Opcode) const {
230 return get(Opcode).Flags & M_LOAD_FLAG;
232 bool isStore(MachineOpCode Opcode) const {
233 return get(Opcode).Flags & M_STORE_FLAG;
236 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
237 /// which must be filled by the code generator.
238 bool hasDelaySlot(unsigned Opcode) const {
239 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
242 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
243 /// custom insertion support when the DAG scheduler is inserting it into a
244 /// machine basic block.
245 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
246 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
249 bool hasVariableOperands(MachineOpCode Opcode) const {
250 return get(Opcode).Flags & M_VARIABLE_OPS;
253 /// getOperandConstraint - Returns the value of the specific constraint if
254 /// it is set. Returns -1 if it is not set.
255 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
256 TOI::OperandConstraint Constraint) const {
257 return get(Opcode).getOperandConstraint(OpNum, Constraint);
260 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
261 /// dest operand. Returns -1 if there isn't one.
262 int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
264 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
265 /// instruction if it has one. This is used by codegen passes that update
266 /// DWARF line number info as they modify the code.
267 virtual unsigned getDWARF_LABELOpcode() const {
271 /// Return true if the instruction is a register to register move
272 /// and leave the source and dest operands in the passed parameters.
273 virtual bool isMoveInstr(const MachineInstr& MI,
275 unsigned& destReg) const {
279 /// isLoadFromStackSlot - If the specified machine instruction is a direct
280 /// load from a stack slot, return the virtual or physical register number of
281 /// the destination along with the FrameIndex of the loaded stack slot. If
282 /// not, return 0. This predicate must return 0 if the instruction has
283 /// any side effects other than loading from the stack slot.
284 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
288 /// isStoreToStackSlot - If the specified machine instruction is a direct
289 /// store to a stack slot, return the virtual or physical register number of
290 /// the source reg along with the FrameIndex of the loaded stack slot. If
291 /// not, return 0. This predicate must return 0 if the instruction has
292 /// any side effects other than storing to the stack slot.
293 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
297 /// convertToThreeAddress - This method must be implemented by targets that
298 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
299 /// may be able to convert a two-address instruction into one or moretrue
300 /// three-address instructions on demand. This allows the X86 target (for
301 /// example) to convert ADD and SHL instructions into LEA instructions if they
302 /// would require register copies due to two-addressness.
304 /// This method returns a null pointer if the transformation cannot be
305 /// performed, otherwise it returns the last new instruction.
307 virtual MachineInstr *
308 convertToThreeAddress(MachineFunction::iterator &MFI,
309 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
313 /// commuteInstruction - If a target has any instructions that are commutable,
314 /// but require converting to a different instruction or making non-trivial
315 /// changes to commute them, this method can overloaded to do this. The
316 /// default implementation of this method simply swaps the first two operands
317 /// of MI and returns it.
319 /// If a target wants to make more aggressive changes, they can construct and
320 /// return a new machine instruction. If an instruction cannot commute, it
321 /// can also return null.
323 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
325 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
326 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
327 /// implemented for a target). Upon success, this returns false and returns
328 /// with the following information in various cases:
330 /// 1. If this block ends with no branches (it just falls through to its succ)
331 /// just return false, leaving TBB/FBB null.
332 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
333 /// the destination block.
334 /// 3. If this block ends with an conditional branch, it returns the 'true'
335 /// destination in TBB, the 'false' destination in FBB, and a list of
336 /// operands that evaluate the condition. These operands can be passed to
337 /// other TargetInstrInfo methods to create new branches.
339 /// Note that RemoveBranch and InsertBranch must be implemented to support
340 /// cases where this method returns success.
342 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
343 MachineBasicBlock *&FBB,
344 std::vector<MachineOperand> &Cond) const {
348 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
349 /// this is only invoked in cases where AnalyzeBranch returns success.
350 virtual void RemoveBranch(MachineBasicBlock &MBB) const {
351 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
354 /// InsertBranch - Insert a branch into the end of the specified
355 /// MachineBasicBlock. This operands to this method are the same as those
356 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
357 /// returns success and when an unconditional branch (TBB is non-null, FBB is
358 /// null, Cond is empty) needs to be inserted.
359 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
360 MachineBasicBlock *FBB,
361 const std::vector<MachineOperand> &Cond) const {
362 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
365 /// BlockHasNoFallThrough - Return true if the specified block does not
366 /// fall-through into its successor block. This is primarily used when a
367 /// branch is unanalyzable. It is useful for things like unconditional
368 /// indirect branches (jump tables).
369 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
373 /// ReverseBranchCondition - Reverses the branch condition of the specified
374 /// condition list, returning false on success and true if it cannot be
376 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
380 /// insertNoop - Insert a noop into the instruction stream at the specified
382 virtual void insertNoop(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator MI) const {
384 assert(0 && "Target didn't implement insertNoop!");
388 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
390 virtual const TargetRegisterClass *getPointerRegClass() const {
391 assert(0 && "Target didn't implement getPointerRegClass!");
396 } // End llvm namespace