1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
33 template<class T> class SmallVectorImpl;
35 //===----------------------------------------------------------------------===//
36 // Machine Operand Flags and Description
37 //===----------------------------------------------------------------------===//
40 // Operand constraints: only "tied_to" for now.
41 enum OperandConstraint {
42 TIED_TO = 0 // Must be allocated the same register as.
45 /// OperandFlags - These are flags set on operands, but should be considered
46 /// private, all access should go through the TargetOperandInfo accessors.
47 /// See the accessors for a description of what these are.
49 LookupPtrRegClass = 1 << 0,
55 /// TargetOperandInfo - This holds information about one operand of a machine
56 /// instruction, indicating the register class for register operands, etc.
58 class TargetOperandInfo {
60 /// RegClass - This specifies the register class enumeration of the operand
61 /// if the operand is a register. If not, this contains 0.
62 unsigned short RegClass;
64 /// Lower 16 bits are used to specify which constraints are set. The higher 16
65 /// bits are used to specify the value of constraints (4 bits each).
66 unsigned int Constraints;
67 /// Currently no other information.
69 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
70 /// requires a callback to look up its register class.
71 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
73 /// isPredicate - Set if this is one of the operands that made up of
74 /// the predicate operand that controls an M_PREDICATED instruction.
75 bool isPredicate() const { return Flags & TOI::Predicate; }
77 /// isOptionalDef - Set if this operand is a optional def.
79 bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
83 //===----------------------------------------------------------------------===//
84 // Machine Instruction Flags and Description
85 //===----------------------------------------------------------------------===//
87 const unsigned M_BRANCH_FLAG = 1 << 0;
88 const unsigned M_CALL_FLAG = 1 << 1;
89 const unsigned M_RET_FLAG = 1 << 2;
90 const unsigned M_BARRIER_FLAG = 1 << 3;
91 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
93 /// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
94 /// from memory. This should only be set on instructions that load a value from
95 /// memory and return it in their only virtual register definition.
96 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
98 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
99 /// modify memory. Instructions with this flag set are not necessarily simple
100 /// store instructions, they may store a modified value based on their operands,
101 /// or may not actually modify anything, for example.
102 const unsigned M_MAY_STORE_FLAG = 1 << 6;
104 const unsigned M_INDIRECT_FLAG = 1 << 7;
105 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
107 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
108 // changed into a 3-address instruction if the first two operands cannot be
109 // assigned to the same register. The target must implement the
110 // TargetInstrInfo::convertToThreeAddress method for this instruction.
111 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
113 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
114 // Z), which produces the same result if Y and Z are exchanged.
115 const unsigned M_COMMUTABLE = 1 << 10;
117 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
118 // block? Typically this is things like return and branch instructions.
119 // Various passes use this to insert code into the bottom of a basic block, but
120 // before control flow occurs.
121 const unsigned M_TERMINATOR_FLAG = 1 << 11;
123 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
124 // insertion support when the DAG scheduler is inserting it into a machine basic
126 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
128 const unsigned M_VARIADIC = 1 << 13;
130 // M_PREDICABLE - Set if this instruction has a predicate operand that
131 // controls execution. It may be set to 'always'.
132 const unsigned M_PREDICABLE = 1 << 14;
134 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
135 // at any time, e.g. constant generation, load from constant pool.
136 const unsigned M_REMATERIALIZIBLE = 1 << 15;
138 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
139 // (e.g. instructions with unique labels attached).
140 const unsigned M_NOT_DUPLICABLE = 1 << 16;
142 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
144 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
145 // are not captured by any operands of the instruction or other flags, and when
146 // *all* instances of the instruction of that opcode have no side effects.
148 // Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
149 // both! If neither flag is set, then the instruction *always* has side effects.
150 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
152 // M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
153 // side effects. The virtual method "isReallySideEffectFree" is called to
154 // determine this. Load instructions are an example of where this is useful. In
155 // general, loads always have side effects. However, loads from constant pools
156 // don't. We let the specific back end make this determination.
158 // Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
159 // both! If neither flag is set, then the instruction *always* has side effects.
160 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
164 class TargetInstrDescriptor {
166 unsigned short Opcode; // The opcode number.
167 unsigned short NumOperands; // Num of args (may be more if variable_ops)
168 unsigned short NumDefs; // Num of args that are definitions.
169 unsigned short SchedClass; // enum identifying instr sched class
170 const char * Name; // Name of the instruction record in td file.
171 unsigned Flags; // flags identifying machine instr class
172 unsigned TSFlags; // Target Specific Flag values
173 const unsigned *ImplicitUses; // Registers implicitly read by this instr
174 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
175 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
177 /// getOperandConstraint - Returns the value of the specific constraint if
178 /// it is set. Returns -1 if it is not set.
179 int getOperandConstraint(unsigned OpNum,
180 TOI::OperandConstraint Constraint) const {
181 assert((OpNum < NumOperands || isVariadic()) &&
182 "Invalid operand # of TargetInstrInfo");
183 if (OpNum < NumOperands &&
184 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
185 unsigned Pos = 16 + Constraint * 4;
186 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
191 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
192 /// dest operand. Returns -1 if there isn't one.
193 int findTiedToSrcOperand(unsigned OpNum) const;
195 /// getName - Return the name of the record in the .td file for this
196 /// instruction, for example "ADD8ri".
197 const char *getName() const {
201 /// getNumOperands - Return the number of declared MachineOperands for this
202 /// MachineInstruction. Note that variadic (isVariadic() returns true)
203 /// instructions may have additional operands at the end of the list, and note
204 /// that the machine instruction may include implicit register def/uses as
206 unsigned getNumOperands() const {
210 /// getNumDefs - Return the number of MachineOperands that are register
211 /// definitions. Register definitions always occur at the start of the
212 /// machine operand list. This is the number of "outs" in the .td file.
213 unsigned getNumDefs() const {
217 /// isVariadic - Return true if this instruction can have a variable number of
218 /// operands. In this case, the variable operands will be after the normal
219 /// operands but before the implicit definitions and uses (if any are
221 bool isVariadic() const {
222 return Flags & M_VARIADIC;
225 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
226 /// ARM instructions which can set condition code if 's' bit is set.
227 bool hasOptionalDef() const {
228 return Flags & M_HAS_OPTIONAL_DEF;
231 const unsigned *getImplicitUses() const {
235 const unsigned *getImplicitDefs() const {
239 bool isReturn() const {
240 return Flags & M_RET_FLAG;
243 bool isCall() const {
244 return Flags & M_CALL_FLAG;
247 bool isTerminator() const {
248 return Flags & M_TERMINATOR_FLAG;
251 bool isBranch() const {
252 return Flags & M_BRANCH_FLAG;
255 bool isIndirectBranch() const {
256 return Flags & M_INDIRECT_FLAG;
259 bool isPredicable() const {
260 return Flags & M_PREDICABLE;
263 bool isNotDuplicable() const {
264 return Flags & M_NOT_DUPLICABLE;
267 bool isCommutableInstr() const {
268 return Flags & M_COMMUTABLE;
271 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
272 /// custom insertion support when the DAG scheduler is inserting it into a
273 /// machine basic block.
274 bool usesCustomDAGSchedInsertionHook() const {
275 return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
278 /// isSimpleLoad - Return true for instructions that are simple loads from
279 /// memory. This should only be set on instructions that load a value from
280 /// memory and return it in their only virtual register definition.
281 /// Instructions that return a value loaded from memory and then modified in
282 /// some way should not return true for this.
283 bool isSimpleLoad() const {
284 return Flags & M_SIMPLE_LOAD_FLAG;
287 /// mayStore - Return true if this instruction could possibly modify memory.
288 /// Instructions with this flag set are not necessarily simple store
289 /// instructions, they may store a modified value based on their operands, or
290 /// may not actually modify anything, for example.
291 bool mayStore() const {
292 return Flags & M_MAY_STORE_FLAG;
295 /// isBarrier - Returns true if the specified instruction stops control flow
296 /// from executing the instruction immediately following it. Examples include
297 /// unconditional branches and return instructions.
298 bool isBarrier() const {
299 return Flags & M_BARRIER_FLAG;
302 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
303 /// which must be filled by the code generator.
304 bool hasDelaySlot() const {
305 return Flags & M_DELAY_SLOT_FLAG;
308 unsigned getSchedClass() const {
314 //---------------------------------------------------------------------------
316 /// TargetInstrInfo - Interface to description of machine instructions
318 class TargetInstrInfo {
319 const TargetInstrDescriptor* desc; // raw array to allow static init'n
320 unsigned NumOpcodes; // number of entries in the desc array
321 unsigned numRealOpCodes; // number of non-dummy op codes
323 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
324 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
326 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
327 virtual ~TargetInstrInfo();
329 // Invariant opcodes: All instruction sets have these as their low opcodes.
338 unsigned getNumOpcodes() const { return NumOpcodes; }
340 /// get - Return the machine instruction descriptor that corresponds to the
341 /// specified instruction opcode.
343 const TargetInstrDescriptor& get(unsigned Opcode) const {
344 assert(Opcode < NumOpcodes);
348 /// isTriviallyReMaterializable - Return true if the instruction is trivially
349 /// rematerializable, meaning it has no side effects and requires no operands
350 /// that aren't always available.
351 bool isTriviallyReMaterializable(MachineInstr *MI) const {
352 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) &&
353 isReallyTriviallyReMaterializable(MI);
356 /// hasUnmodelledSideEffects - Returns true if the instruction has side
357 /// effects that are not captured by any operands of the instruction or other
359 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
360 const TargetInstrDescriptor *TID = MI->getDesc();
361 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
362 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
363 return !isReallySideEffectFree(MI); // May have side effects
366 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
367 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
368 /// instruction itself is actually trivially rematerializable, considering
369 /// its operands. This is used for targets that have instructions that are
370 /// only trivially rematerializable for specific uses. This predicate must
371 /// return false if the instruction has any side effects other than
372 /// producing a value, or if it requres any address registers that are not
373 /// always available.
374 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
378 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
379 /// method is called to determine if the specific instance of this
380 /// instruction has side effects. This is useful in cases of instructions,
381 /// like loads, which generally always have side effects. A load from a
382 /// constant pool doesn't have side effects, though. So we need to
383 /// differentiate it from the general case.
384 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
388 /// getOperandConstraint - Returns the value of the specific constraint if
389 /// it is set. Returns -1 if it is not set.
390 int getOperandConstraint(unsigned Opcode, unsigned OpNum,
391 TOI::OperandConstraint Constraint) const {
392 return get(Opcode).getOperandConstraint(OpNum, Constraint);
395 /// Return true if the instruction is a register to register move
396 /// and leave the source and dest operands in the passed parameters.
397 virtual bool isMoveInstr(const MachineInstr& MI,
399 unsigned& destReg) const {
403 /// isLoadFromStackSlot - If the specified machine instruction is a direct
404 /// load from a stack slot, return the virtual or physical register number of
405 /// the destination along with the FrameIndex of the loaded stack slot. If
406 /// not, return 0. This predicate must return 0 if the instruction has
407 /// any side effects other than loading from the stack slot.
408 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
412 /// isStoreToStackSlot - If the specified machine instruction is a direct
413 /// store to a stack slot, return the virtual or physical register number of
414 /// the source reg along with the FrameIndex of the loaded stack slot. If
415 /// not, return 0. This predicate must return 0 if the instruction has
416 /// any side effects other than storing to the stack slot.
417 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
421 /// convertToThreeAddress - This method must be implemented by targets that
422 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
423 /// may be able to convert a two-address instruction into one or more true
424 /// three-address instructions on demand. This allows the X86 target (for
425 /// example) to convert ADD and SHL instructions into LEA instructions if they
426 /// would require register copies due to two-addressness.
428 /// This method returns a null pointer if the transformation cannot be
429 /// performed, otherwise it returns the last new instruction.
431 virtual MachineInstr *
432 convertToThreeAddress(MachineFunction::iterator &MFI,
433 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
437 /// commuteInstruction - If a target has any instructions that are commutable,
438 /// but require converting to a different instruction or making non-trivial
439 /// changes to commute them, this method can overloaded to do this. The
440 /// default implementation of this method simply swaps the first two operands
441 /// of MI and returns it.
443 /// If a target wants to make more aggressive changes, they can construct and
444 /// return a new machine instruction. If an instruction cannot commute, it
445 /// can also return null.
447 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
449 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
450 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
451 /// implemented for a target). Upon success, this returns false and returns
452 /// with the following information in various cases:
454 /// 1. If this block ends with no branches (it just falls through to its succ)
455 /// just return false, leaving TBB/FBB null.
456 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
457 /// the destination block.
458 /// 3. If this block ends with an conditional branch and it falls through to
459 /// an successor block, it sets TBB to be the branch destination block and a
460 /// list of operands that evaluate the condition. These
461 /// operands can be passed to other TargetInstrInfo methods to create new
463 /// 4. If this block ends with an conditional branch and an unconditional
464 /// block, it returns the 'true' destination in TBB, the 'false' destination
465 /// in FBB, and a list of operands that evaluate the condition. These
466 /// operands can be passed to other TargetInstrInfo methods to create new
469 /// Note that RemoveBranch and InsertBranch must be implemented to support
470 /// cases where this method returns success.
472 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
473 MachineBasicBlock *&FBB,
474 std::vector<MachineOperand> &Cond) const {
478 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
479 /// this is only invoked in cases where AnalyzeBranch returns success. It
480 /// returns the number of instructions that were removed.
481 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
482 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
486 /// InsertBranch - Insert a branch into the end of the specified
487 /// MachineBasicBlock. This operands to this method are the same as those
488 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
489 /// returns success and when an unconditional branch (TBB is non-null, FBB is
490 /// null, Cond is empty) needs to be inserted. It returns the number of
491 /// instructions inserted.
492 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
493 MachineBasicBlock *FBB,
494 const std::vector<MachineOperand> &Cond) const {
495 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
499 /// copyRegToReg - Add a copy between a pair of registers
500 virtual void copyRegToReg(MachineBasicBlock &MBB,
501 MachineBasicBlock::iterator MI,
502 unsigned DestReg, unsigned SrcReg,
503 const TargetRegisterClass *DestRC,
504 const TargetRegisterClass *SrcRC) const {
505 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
508 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
509 MachineBasicBlock::iterator MI,
510 unsigned SrcReg, bool isKill, int FrameIndex,
511 const TargetRegisterClass *RC) const {
512 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
515 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
516 SmallVectorImpl<MachineOperand> &Addr,
517 const TargetRegisterClass *RC,
518 SmallVectorImpl<MachineInstr*> &NewMIs) const {
519 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
522 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
523 MachineBasicBlock::iterator MI,
524 unsigned DestReg, int FrameIndex,
525 const TargetRegisterClass *RC) const {
526 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
529 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
530 SmallVectorImpl<MachineOperand> &Addr,
531 const TargetRegisterClass *RC,
532 SmallVectorImpl<MachineInstr*> &NewMIs) const {
533 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
536 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
537 /// saved registers and returns true if it isn't possible / profitable to do
538 /// so by issuing a series of store instructions via
539 /// storeRegToStackSlot(). Returns false otherwise.
540 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
541 MachineBasicBlock::iterator MI,
542 const std::vector<CalleeSavedInfo> &CSI) const {
546 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
547 /// saved registers and returns true if it isn't possible / profitable to do
548 /// so by issuing a series of load instructions via loadRegToStackSlot().
549 /// Returns false otherwise.
550 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
551 MachineBasicBlock::iterator MI,
552 const std::vector<CalleeSavedInfo> &CSI) const {
556 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
557 /// slot into the specified machine instruction for the specified operand(s).
558 /// If this is possible, a new instruction is returned with the specified
559 /// operand folded, otherwise NULL is returned. The client is responsible for
560 /// removing the old instruction and adding the new one in the instruction
562 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
563 SmallVectorImpl<unsigned> &Ops,
564 int FrameIndex) const {
568 /// foldMemoryOperand - Same as the previous version except it allows folding
569 /// of any load and store from / to any address, not just from a specific
571 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
572 SmallVectorImpl<unsigned> &Ops,
573 MachineInstr* LoadMI) const {
577 /// canFoldMemoryOperand - Returns true if the specified load / store is
578 /// folding is possible.
580 bool canFoldMemoryOperand(MachineInstr *MI,
581 SmallVectorImpl<unsigned> &Ops) const{
585 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
586 /// a store or a load and a store into two or more instruction. If this is
587 /// possible, returns true as well as the new instructions by reference.
588 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
589 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
590 SmallVectorImpl<MachineInstr*> &NewMIs) const{
594 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
595 SmallVectorImpl<SDNode*> &NewNodes) const {
599 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
600 /// instruction after load / store are unfolded from an instruction of the
601 /// specified opcode. It returns zero if the specified unfolding is not
603 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
604 bool UnfoldLoad, bool UnfoldStore) const {
608 /// BlockHasNoFallThrough - Return true if the specified block does not
609 /// fall-through into its successor block. This is primarily used when a
610 /// branch is unanalyzable. It is useful for things like unconditional
611 /// indirect branches (jump tables).
612 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
616 /// ReverseBranchCondition - Reverses the branch condition of the specified
617 /// condition list, returning false on success and true if it cannot be
619 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
623 /// insertNoop - Insert a noop into the instruction stream at the specified
625 virtual void insertNoop(MachineBasicBlock &MBB,
626 MachineBasicBlock::iterator MI) const {
627 assert(0 && "Target didn't implement insertNoop!");
631 /// isPredicated - Returns true if the instruction is already predicated.
633 virtual bool isPredicated(const MachineInstr *MI) const {
637 /// isUnpredicatedTerminator - Returns true if the instruction is a
638 /// terminator instruction that has not been predicated.
639 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
641 /// PredicateInstruction - Convert the instruction into a predicated
642 /// instruction. It returns true if the operation was successful.
644 bool PredicateInstruction(MachineInstr *MI,
645 const std::vector<MachineOperand> &Pred) const = 0;
647 /// SubsumesPredicate - Returns true if the first specified predicate
648 /// subsumes the second, e.g. GE subsumes GT.
650 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
651 const std::vector<MachineOperand> &Pred2) const {
655 /// DefinesPredicate - If the specified instruction defines any predicate
656 /// or condition code register(s) used for predication, returns true as well
657 /// as the definition predicate(s) by reference.
658 virtual bool DefinesPredicate(MachineInstr *MI,
659 std::vector<MachineOperand> &Pred) const {
663 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
665 virtual const TargetRegisterClass *getPointerRegClass() const {
666 assert(0 && "Target didn't implement getPointerRegClass!");
668 return 0; // Must return a value in order to compile with VS 2005
672 /// TargetInstrInfoImpl - This is the default implementation of
673 /// TargetInstrInfo, which just provides a couple of default implementations
674 /// for various methods. This separated out because it is implemented in
675 /// libcodegen, not in libtarget.
676 class TargetInstrInfoImpl : public TargetInstrInfo {
678 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
679 : TargetInstrInfo(desc, NumOpcodes) {}
681 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
682 virtual bool PredicateInstruction(MachineInstr *MI,
683 const std::vector<MachineOperand> &Pred) const;
687 } // End llvm namespace