1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "llvm/Target/TargetMachine.h"
11 #include "llvm/Support/DataTypes.h"
13 class MachineInstrDescriptor;
16 typedef int InstrSchedClass;
18 // Global variable holding an array of descriptors for machine instructions.
19 // The actual object needs to be created separately for each target machine.
20 // This variable is initialized and reset by class MachineInstrInfo.
22 // FIXME: This should be a property of the target so that more than one target
23 // at a time can be active...
25 extern const MachineInstrDescriptor *TargetInstrDescriptors;
28 //---------------------------------------------------------------------------
29 // struct MachineInstrDescriptor:
30 // Predefined information about each machine instruction.
31 // Designed to initialized statically.
33 // class MachineInstructionInfo
34 // Interface to description of machine instructions
36 //---------------------------------------------------------------------------
39 const unsigned int M_NOP_FLAG = 1;
40 const unsigned int M_BRANCH_FLAG = 1 << 1;
41 const unsigned int M_CALL_FLAG = 1 << 2;
42 const unsigned int M_RET_FLAG = 1 << 3;
43 const unsigned int M_ARITH_FLAG = 1 << 4;
44 const unsigned int M_CC_FLAG = 1 << 6;
45 const unsigned int M_LOGICAL_FLAG = 1 << 6;
46 const unsigned int M_INT_FLAG = 1 << 7;
47 const unsigned int M_FLOAT_FLAG = 1 << 8;
48 const unsigned int M_CONDL_FLAG = 1 << 9;
49 const unsigned int M_LOAD_FLAG = 1 << 10;
50 const unsigned int M_PREFETCH_FLAG = 1 << 11;
51 const unsigned int M_STORE_FLAG = 1 << 12;
52 const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
55 struct MachineInstrDescriptor {
56 string opCodeString; // Assembly language mnemonic for the opcode.
57 int numOperands; // Number of args; -1 if variable #args
58 int resultPos; // Position of the result; -1 if no result
59 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
60 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
61 // smallest -ve value is -(maxImmedConst+1).
62 unsigned int numDelaySlots; // Number of delay slots after instruction
63 unsigned int latency; // Latency in machine cycles
64 InstrSchedClass schedClass; // enum identifying instr sched class
65 unsigned int iclass; // flags identifying machine instr class
69 class MachineInstrInfo : public NonCopyableV {
71 const MachineInstrDescriptor* desc; // raw array to allow static init'n
72 unsigned int descSize; // number of entries in the desc array
73 unsigned int numRealOpCodes; // number of non-dummy op codes
76 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
77 unsigned numRealOpCodes);
78 virtual ~MachineInstrInfo();
80 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
81 unsigned getNumTotalOpCodes() const { return descSize; }
83 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
84 assert(opCode >= 0 && opCode < (int)descSize);
88 int getNumOperands(MachineOpCode opCode) const {
89 return getDescriptor(opCode).numOperands;
92 int getResultPos(MachineOpCode opCode) const {
93 return getDescriptor(opCode).resultPos;
96 unsigned getNumDelaySlots(MachineOpCode opCode) const {
97 return getDescriptor(opCode).numDelaySlots;
100 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
101 return getDescriptor(opCode).schedClass;
105 // Query instruction class flags according to the machine-independent
106 // flags listed above.
108 unsigned int getIClass(MachineOpCode opCode) const {
109 return getDescriptor(opCode).iclass;
111 bool isNop(MachineOpCode opCode) const {
112 return getDescriptor(opCode).iclass & M_NOP_FLAG;
114 bool isBranch(MachineOpCode opCode) const {
115 return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
117 bool isCall(MachineOpCode opCode) const {
118 return getDescriptor(opCode).iclass & M_CALL_FLAG;
120 bool isReturn(MachineOpCode opCode) const {
121 return getDescriptor(opCode).iclass & M_RET_FLAG;
123 bool isControlFlow(MachineOpCode opCode) const {
124 return getDescriptor(opCode).iclass & M_BRANCH_FLAG
125 || getDescriptor(opCode).iclass & M_CALL_FLAG
126 || getDescriptor(opCode).iclass & M_RET_FLAG;
128 bool isArith(MachineOpCode opCode) const {
129 return getDescriptor(opCode).iclass & M_RET_FLAG;
131 bool isCCInstr(MachineOpCode opCode) const {
132 return getDescriptor(opCode).iclass & M_CC_FLAG;
134 bool isLogical(MachineOpCode opCode) const {
135 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
137 bool isIntInstr(MachineOpCode opCode) const {
138 return getDescriptor(opCode).iclass & M_INT_FLAG;
140 bool isFloatInstr(MachineOpCode opCode) const {
141 return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
143 bool isConditional(MachineOpCode opCode) const {
144 return getDescriptor(opCode).iclass & M_CONDL_FLAG;
146 bool isLoad(MachineOpCode opCode) const {
147 return getDescriptor(opCode).iclass & M_LOAD_FLAG;
149 bool isPrefetch(MachineOpCode opCode) const {
150 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
152 bool isLoadOrPrefetch(MachineOpCode opCode) const {
153 return getDescriptor(opCode).iclass & M_LOAD_FLAG
154 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
156 bool isStore(MachineOpCode opCode) const {
157 return getDescriptor(opCode).iclass & M_STORE_FLAG;
159 bool isMemoryAccess(MachineOpCode opCode) const {
160 return getDescriptor(opCode).iclass & M_LOAD_FLAG
161 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG
162 || getDescriptor(opCode).iclass & M_STORE_FLAG;
164 bool isDummyPhiInstr(MachineOpCode opCode) const {
165 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
169 // delete this later *******
170 bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
173 // Check if an instruction can be issued before its operands are ready,
174 // or if a subsequent instruction that uses its result can be issued
175 // before the results are ready.
176 // Default to true since most instructions on many architectures allow this.
178 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
182 virtual bool hasResultInterlock(MachineOpCode opCode) const {
187 // Latencies for individual instructions and instruction pairs
189 virtual int minLatency(MachineOpCode opCode) const {
190 return getDescriptor(opCode).latency;
193 virtual int maxLatency(MachineOpCode opCode) const {
194 return getDescriptor(opCode).latency;
197 // Check if the specified constant fits in the immediate field
198 // of this machine instruction
200 virtual bool constantFitsInImmedField(MachineOpCode opCode,
201 int64_t intValue) const;
203 // Return the largest +ve constant that can be held in the IMMMED field
204 // of this machine instruction.
205 // isSignExtended is set to true if the value is sign-extended before use
206 // (this is true for all immediate fields in SPARC instructions).
207 // Return 0 if the instruction has no IMMED field.
209 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
210 bool &isSignExtended) const {
211 isSignExtended = getDescriptor(opCode).immedIsSignExtended;
212 return getDescriptor(opCode).maxImmedConst;