1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
23 class InstrItineraryData;
26 class MachineMemOperand;
30 class ScheduleHazardRecognizer;
32 class TargetRegisterClass;
33 class TargetRegisterInfo;
35 template<class T> class SmallVectorImpl;
38 //---------------------------------------------------------------------------
40 /// TargetInstrInfo - Interface to description of machine instruction set
42 class TargetInstrInfo {
43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
44 unsigned NumOpcodes; // Number of entries in the desc array
46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
50 virtual ~TargetInstrInfo();
52 unsigned getNumOpcodes() const { return NumOpcodes; }
54 /// get - Return the machine instruction descriptor that corresponds to the
55 /// specified instruction opcode.
57 const TargetInstrDesc &get(unsigned Opcode) const {
58 assert(Opcode < NumOpcodes && "Invalid opcode!");
59 return Descriptors[Opcode];
62 /// isTriviallyReMaterializable - Return true if the instruction is trivially
63 /// rematerializable, meaning it has no side effects and requires no operands
64 /// that aren't always available.
65 bool isTriviallyReMaterializable(const MachineInstr *MI,
66 AliasAnalysis *AA = 0) const {
67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
68 (MI->getDesc().isRematerializable() &&
69 (isReallyTriviallyReMaterializable(MI, AA) ||
70 isReallyTriviallyReMaterializableGeneric(MI, AA)));
74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
76 /// specify whether the instruction is actually trivially rematerializable,
77 /// taking into consideration its operands. This predicate must return false
78 /// if the instruction has any side effects other than producing a value, or
79 /// if it requres any address registers that are not always available.
80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
81 AliasAnalysis *AA) const {
86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
87 /// for which the M_REMATERIALIZABLE flag is set and the target hook
88 /// isReallyTriviallyReMaterializable returns false, this function does
89 /// target-independent tests to determine if the instruction is really
90 /// trivially rematerializable.
91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
92 AliasAnalysis *AA) const;
95 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
96 /// extension instruction. That is, it's like a copy where it's legal for the
97 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
98 /// true, then it's expected the pre-extension value is available as a subreg
99 /// of the result register. This also returns the sub-register index in
101 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
102 unsigned &SrcReg, unsigned &DstReg,
103 unsigned &SubIdx) const {
107 /// isLoadFromStackSlot - If the specified machine instruction is a direct
108 /// load from a stack slot, return the virtual or physical register number of
109 /// the destination along with the FrameIndex of the loaded stack slot. If
110 /// not, return 0. This predicate must return 0 if the instruction has
111 /// any side effects other than loading from the stack slot.
112 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
113 int &FrameIndex) const {
117 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
118 /// stack locations as well. This uses a heuristic so it isn't
119 /// reliable for correctness.
120 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
121 int &FrameIndex) const {
125 /// hasLoadFromStackSlot - If the specified machine instruction has
126 /// a load from a stack slot, return true along with the FrameIndex
127 /// of the loaded stack slot and the machine mem operand containing
128 /// the reference. If not, return false. Unlike
129 /// isLoadFromStackSlot, this returns true for any instructions that
130 /// loads from the stack. This is just a hint, as some cases may be
132 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
133 const MachineMemOperand *&MMO,
134 int &FrameIndex) const {
138 /// isStoreToStackSlot - If the specified machine instruction is a direct
139 /// store to a stack slot, return the virtual or physical register number of
140 /// the source reg along with the FrameIndex of the loaded stack slot. If
141 /// not, return 0. This predicate must return 0 if the instruction has
142 /// any side effects other than storing to the stack slot.
143 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
144 int &FrameIndex) const {
148 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
149 /// stack locations as well. This uses a heuristic so it isn't
150 /// reliable for correctness.
151 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
152 int &FrameIndex) const {
156 /// hasStoreToStackSlot - If the specified machine instruction has a
157 /// store to a stack slot, return true along with the FrameIndex of
158 /// the loaded stack slot and the machine mem operand containing the
159 /// reference. If not, return false. Unlike isStoreToStackSlot,
160 /// this returns true for any instructions that stores to the
161 /// stack. This is just a hint, as some cases may be missed.
162 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
163 const MachineMemOperand *&MMO,
164 int &FrameIndex) const {
168 /// reMaterialize - Re-issue the specified 'original' instruction at the
169 /// specific location targeting a new destination register.
170 /// The register in Orig->getOperand(0).getReg() will be substituted by
171 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
173 virtual void reMaterialize(MachineBasicBlock &MBB,
174 MachineBasicBlock::iterator MI,
175 unsigned DestReg, unsigned SubIdx,
176 const MachineInstr *Orig,
177 const TargetRegisterInfo &TRI) const = 0;
179 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
180 /// two-addrss instruction inserted by two-address pass.
181 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
183 const TargetRegisterInfo &TRI) const {
187 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
188 /// MachineFunction::CloneMachineInstr(), but the target may update operands
189 /// that are required to be unique.
191 /// The instruction must be duplicable as indicated by isNotDuplicable().
192 virtual MachineInstr *duplicate(MachineInstr *Orig,
193 MachineFunction &MF) const = 0;
195 /// convertToThreeAddress - This method must be implemented by targets that
196 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
197 /// may be able to convert a two-address instruction into one or more true
198 /// three-address instructions on demand. This allows the X86 target (for
199 /// example) to convert ADD and SHL instructions into LEA instructions if they
200 /// would require register copies due to two-addressness.
202 /// This method returns a null pointer if the transformation cannot be
203 /// performed, otherwise it returns the last new instruction.
205 virtual MachineInstr *
206 convertToThreeAddress(MachineFunction::iterator &MFI,
207 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
211 /// commuteInstruction - If a target has any instructions that are
212 /// commutable but require converting to different instructions or making
213 /// non-trivial changes to commute them, this method can overloaded to do
214 /// that. The default implementation simply swaps the commutable operands.
215 /// If NewMI is false, MI is modified in place and returned; otherwise, a
216 /// new machine instruction is created and returned. Do not call this
217 /// method for a non-commutable instruction, but there may be some cases
218 /// where this method fails and returns null.
219 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
220 bool NewMI = false) const = 0;
222 /// findCommutedOpIndices - If specified MI is commutable, return the two
223 /// operand indices that would swap value. Return false if the instruction
224 /// is not in a form which this routine understands.
225 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
226 unsigned &SrcOpIdx2) const = 0;
228 /// produceSameValue - Return true if two machine instructions would produce
229 /// identical values. By default, this is only true when the two instructions
230 /// are deemed identical except for defs.
231 virtual bool produceSameValue(const MachineInstr *MI0,
232 const MachineInstr *MI1) const = 0;
234 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
235 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
236 /// implemented for a target). Upon success, this returns false and returns
237 /// with the following information in various cases:
239 /// 1. If this block ends with no branches (it just falls through to its succ)
240 /// just return false, leaving TBB/FBB null.
241 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
242 /// the destination block.
243 /// 3. If this block ends with a conditional branch and it falls through to a
244 /// successor block, it sets TBB to be the branch destination block and a
245 /// list of operands that evaluate the condition. These operands can be
246 /// passed to other TargetInstrInfo methods to create new branches.
247 /// 4. If this block ends with a conditional branch followed by an
248 /// unconditional branch, it returns the 'true' destination in TBB, the
249 /// 'false' destination in FBB, and a list of operands that evaluate the
250 /// condition. These operands can be passed to other TargetInstrInfo
251 /// methods to create new branches.
253 /// Note that RemoveBranch and InsertBranch must be implemented to support
254 /// cases where this method returns success.
256 /// If AllowModify is true, then this routine is allowed to modify the basic
257 /// block (e.g. delete instructions after the unconditional branch).
259 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
260 MachineBasicBlock *&FBB,
261 SmallVectorImpl<MachineOperand> &Cond,
262 bool AllowModify = false) const {
266 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
267 /// This is only invoked in cases where AnalyzeBranch returns success. It
268 /// returns the number of instructions that were removed.
269 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
270 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
274 /// InsertBranch - Insert branch code into the end of the specified
275 /// MachineBasicBlock. The operands to this method are the same as those
276 /// returned by AnalyzeBranch. This is only invoked in cases where
277 /// AnalyzeBranch returns success. It returns the number of instructions
280 /// It is also invoked by tail merging to add unconditional branches in
281 /// cases where AnalyzeBranch doesn't apply because there was no original
282 /// branch to analyze. At least this much must be implemented, else tail
283 /// merging needs to be disabled.
284 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
285 MachineBasicBlock *FBB,
286 const SmallVectorImpl<MachineOperand> &Cond,
288 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
292 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
293 /// after it, replacing it with an unconditional branch to NewDest. This is
294 /// used by the tail merging pass.
295 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
296 MachineBasicBlock *NewDest) const = 0;
298 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
299 /// block at the specified instruction (i.e. instruction would be the start
300 /// of a new basic block).
301 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
302 MachineBasicBlock::iterator MBBI) const {
306 /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs"
307 /// of the specified basic block.
309 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
313 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
314 /// checks for the case where two basic blocks from true and false path
315 /// of a if-then-else (diamond) are predicated on mutally exclusive
318 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs,
319 MachineBasicBlock &FMBB, unsigned NumFInstrs) const {
323 /// isProfitableToDupForIfCvt - Return true if it's profitable for
324 /// if-converter to duplicate a specific number of instructions in the
325 /// specified MBB to enable if-conversion.
327 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs) const {
331 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
332 virtual void copyPhysReg(MachineBasicBlock &MBB,
333 MachineBasicBlock::iterator MI, DebugLoc DL,
334 unsigned DestReg, unsigned SrcReg,
335 bool KillSrc) const {
336 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
339 /// storeRegToStackSlot - Store the specified register of the given register
340 /// class to the specified stack frame index. The store instruction is to be
341 /// added to the given machine basic block before the specified machine
342 /// instruction. If isKill is true, the register operand is the last use and
343 /// must be marked kill.
344 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
345 MachineBasicBlock::iterator MI,
346 unsigned SrcReg, bool isKill, int FrameIndex,
347 const TargetRegisterClass *RC,
348 const TargetRegisterInfo *TRI) const {
349 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
352 /// loadRegFromStackSlot - Load the specified register of the given register
353 /// class from the specified stack frame index. The load instruction is to be
354 /// added to the given machine basic block before the specified machine
356 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator MI,
358 unsigned DestReg, int FrameIndex,
359 const TargetRegisterClass *RC,
360 const TargetRegisterInfo *TRI) const {
361 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
364 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
365 /// saved registers and returns true if it isn't possible / profitable to do
366 /// so by issuing a series of store instructions via
367 /// storeRegToStackSlot(). Returns false otherwise.
368 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
369 MachineBasicBlock::iterator MI,
370 const std::vector<CalleeSavedInfo> &CSI,
371 const TargetRegisterInfo *TRI) const {
375 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
376 /// saved registers and returns true if it isn't possible / profitable to do
377 /// so by issuing a series of load instructions via loadRegToStackSlot().
378 /// Returns false otherwise.
379 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
380 MachineBasicBlock::iterator MI,
381 const std::vector<CalleeSavedInfo> &CSI,
382 const TargetRegisterInfo *TRI) const {
386 /// emitFrameIndexDebugValue - Emit a target-dependent form of
387 /// DBG_VALUE encoding the address of a frame index. Addresses would
388 /// normally be lowered the same way as other addresses on the target,
389 /// e.g. in load instructions. For targets that do not support this
390 /// the debug info is simply lost.
391 /// If you add this for a target you should handle this DBG_VALUE in the
392 /// target-specific AsmPrinter code as well; you will probably get invalid
393 /// assembly output if you don't.
394 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
402 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
403 /// slot into the specified machine instruction for the specified operand(s).
404 /// If this is possible, a new instruction is returned with the specified
405 /// operand folded, otherwise NULL is returned.
406 /// The new instruction is inserted before MI, and the client is responsible
407 /// for removing the old instruction.
408 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
409 const SmallVectorImpl<unsigned> &Ops,
410 int FrameIndex) const;
412 /// foldMemoryOperand - Same as the previous version except it allows folding
413 /// of any load and store from / to any address, not just from a specific
415 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
416 const SmallVectorImpl<unsigned> &Ops,
417 MachineInstr* LoadMI) const;
420 /// foldMemoryOperandImpl - Target-dependent implementation for
421 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
422 /// take care of adding a MachineMemOperand to the newly created instruction.
423 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
425 const SmallVectorImpl<unsigned> &Ops,
426 int FrameIndex) const {
430 /// foldMemoryOperandImpl - Target-dependent implementation for
431 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
432 /// take care of adding a MachineMemOperand to the newly created instruction.
433 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
435 const SmallVectorImpl<unsigned> &Ops,
436 MachineInstr* LoadMI) const {
441 /// canFoldMemoryOperand - Returns true for the specified load / store if
442 /// folding is possible.
444 bool canFoldMemoryOperand(const MachineInstr *MI,
445 const SmallVectorImpl<unsigned> &Ops) const =0;
447 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
448 /// a store or a load and a store into two or more instruction. If this is
449 /// possible, returns true as well as the new instructions by reference.
450 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
451 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
452 SmallVectorImpl<MachineInstr*> &NewMIs) const{
456 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
457 SmallVectorImpl<SDNode*> &NewNodes) const {
461 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
462 /// instruction after load / store are unfolded from an instruction of the
463 /// specified opcode. It returns zero if the specified unfolding is not
464 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
465 /// index of the operand which will hold the register holding the loaded
467 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
468 bool UnfoldLoad, bool UnfoldStore,
469 unsigned *LoadRegIndex = 0) const {
473 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
474 /// to determine if two loads are loading from the same base address. It
475 /// should only return true if the base pointers are the same and the
476 /// only differences between the two addresses are the offset. It also returns
477 /// the offsets by reference.
478 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
479 int64_t &Offset1, int64_t &Offset2) const {
483 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
484 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
485 /// be scheduled togther. On some targets if two loads are loading from
486 /// addresses in the same cache line, it's better if they are scheduled
487 /// together. This function takes two integers that represent the load offsets
488 /// from the common base address. It returns true if it decides it's desirable
489 /// to schedule the two loads together. "NumLoads" is the number of loads that
490 /// have already been scheduled after Load1.
491 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
492 int64_t Offset1, int64_t Offset2,
493 unsigned NumLoads) const {
497 /// ReverseBranchCondition - Reverses the branch condition of the specified
498 /// condition list, returning false on success and true if it cannot be
501 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
505 /// insertNoop - Insert a noop into the instruction stream at the specified
507 virtual void insertNoop(MachineBasicBlock &MBB,
508 MachineBasicBlock::iterator MI) const;
511 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
512 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
513 // Default to just using 'nop' string.
517 /// isPredicated - Returns true if the instruction is already predicated.
519 virtual bool isPredicated(const MachineInstr *MI) const {
523 /// isUnpredicatedTerminator - Returns true if the instruction is a
524 /// terminator instruction that has not been predicated.
525 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
527 /// PredicateInstruction - Convert the instruction into a predicated
528 /// instruction. It returns true if the operation was successful.
530 bool PredicateInstruction(MachineInstr *MI,
531 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
533 /// SubsumesPredicate - Returns true if the first specified predicate
534 /// subsumes the second, e.g. GE subsumes GT.
536 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
537 const SmallVectorImpl<MachineOperand> &Pred2) const {
541 /// DefinesPredicate - If the specified instruction defines any predicate
542 /// or condition code register(s) used for predication, returns true as well
543 /// as the definition predicate(s) by reference.
544 virtual bool DefinesPredicate(MachineInstr *MI,
545 std::vector<MachineOperand> &Pred) const {
549 /// isPredicable - Return true if the specified instruction can be predicated.
550 /// By default, this returns true for every instruction with a
551 /// PredicateOperand.
552 virtual bool isPredicable(MachineInstr *MI) const {
553 return MI->getDesc().isPredicable();
556 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
557 /// instruction that defines the specified register class.
558 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
562 /// isSchedulingBoundary - Test if the given instruction should be
563 /// considered a scheduling boundary. This primarily includes labels and
565 virtual bool isSchedulingBoundary(const MachineInstr *MI,
566 const MachineBasicBlock *MBB,
567 const MachineFunction &MF) const = 0;
569 /// GetInstSize - Returns the size of the specified Instruction.
571 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
572 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
576 /// GetFunctionSizeInBytes - Returns the size of the specified
579 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
581 /// Measure the specified inline asm to determine an approximation of its
583 virtual unsigned getInlineAsmLength(const char *Str,
584 const MCAsmInfo &MAI) const;
586 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer
587 /// to use for this target when scheduling the machine instructions after
588 /// register allocation.
589 virtual ScheduleHazardRecognizer*
590 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0;
593 /// TargetInstrInfoImpl - This is the default implementation of
594 /// TargetInstrInfo, which just provides a couple of default implementations
595 /// for various methods. This separated out because it is implemented in
596 /// libcodegen, not in libtarget.
597 class TargetInstrInfoImpl : public TargetInstrInfo {
599 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
600 : TargetInstrInfo(desc, NumOpcodes) {}
602 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
603 MachineBasicBlock *NewDest) const;
604 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
605 bool NewMI = false) const;
606 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
607 unsigned &SrcOpIdx2) const;
608 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
609 const SmallVectorImpl<unsigned> &Ops) const;
610 virtual bool PredicateInstruction(MachineInstr *MI,
611 const SmallVectorImpl<MachineOperand> &Pred) const;
612 virtual void reMaterialize(MachineBasicBlock &MBB,
613 MachineBasicBlock::iterator MI,
614 unsigned DestReg, unsigned SubReg,
615 const MachineInstr *Orig,
616 const TargetRegisterInfo &TRI) const;
617 virtual MachineInstr *duplicate(MachineInstr *Orig,
618 MachineFunction &MF) const;
619 virtual bool produceSameValue(const MachineInstr *MI0,
620 const MachineInstr *MI1) const;
621 virtual bool isSchedulingBoundary(const MachineInstr *MI,
622 const MachineBasicBlock *MBB,
623 const MachineFunction &MF) const;
624 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
626 virtual ScheduleHazardRecognizer *
627 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
630 } // End llvm namespace