1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
23 class InstrItineraryData;
26 class MachineMemOperand;
27 class MachineRegisterInfo;
31 class ScheduleHazardRecognizer;
33 class TargetRegisterClass;
34 class TargetRegisterInfo;
36 template<class T> class SmallVectorImpl;
39 //---------------------------------------------------------------------------
41 /// TargetInstrInfo - Interface to description of machine instruction set
43 class TargetInstrInfo {
44 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
45 unsigned NumOpcodes; // Number of entries in the desc array
47 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
48 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
50 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
51 virtual ~TargetInstrInfo();
53 unsigned getNumOpcodes() const { return NumOpcodes; }
55 /// get - Return the machine instruction descriptor that corresponds to the
56 /// specified instruction opcode.
58 const TargetInstrDesc &get(unsigned Opcode) const {
59 assert(Opcode < NumOpcodes && "Invalid opcode!");
60 return Descriptors[Opcode];
63 /// isTriviallyReMaterializable - Return true if the instruction is trivially
64 /// rematerializable, meaning it has no side effects and requires no operands
65 /// that aren't always available.
66 bool isTriviallyReMaterializable(const MachineInstr *MI,
67 AliasAnalysis *AA = 0) const {
68 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
69 (MI->getDesc().isRematerializable() &&
70 (isReallyTriviallyReMaterializable(MI, AA) ||
71 isReallyTriviallyReMaterializableGeneric(MI, AA)));
75 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
76 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
77 /// specify whether the instruction is actually trivially rematerializable,
78 /// taking into consideration its operands. This predicate must return false
79 /// if the instruction has any side effects other than producing a value, or
80 /// if it requres any address registers that are not always available.
81 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
82 AliasAnalysis *AA) const {
87 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
88 /// for which the M_REMATERIALIZABLE flag is set and the target hook
89 /// isReallyTriviallyReMaterializable returns false, this function does
90 /// target-independent tests to determine if the instruction is really
91 /// trivially rematerializable.
92 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
93 AliasAnalysis *AA) const;
96 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
97 /// extension instruction. That is, it's like a copy where it's legal for the
98 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
99 /// true, then it's expected the pre-extension value is available as a subreg
100 /// of the result register. This also returns the sub-register index in
102 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
103 unsigned &SrcReg, unsigned &DstReg,
104 unsigned &SubIdx) const {
108 /// isLoadFromStackSlot - If the specified machine instruction is a direct
109 /// load from a stack slot, return the virtual or physical register number of
110 /// the destination along with the FrameIndex of the loaded stack slot. If
111 /// not, return 0. This predicate must return 0 if the instruction has
112 /// any side effects other than loading from the stack slot.
113 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
114 int &FrameIndex) const {
118 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
119 /// stack locations as well. This uses a heuristic so it isn't
120 /// reliable for correctness.
121 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
122 int &FrameIndex) const {
126 /// hasLoadFromStackSlot - If the specified machine instruction has
127 /// a load from a stack slot, return true along with the FrameIndex
128 /// of the loaded stack slot and the machine mem operand containing
129 /// the reference. If not, return false. Unlike
130 /// isLoadFromStackSlot, this returns true for any instructions that
131 /// loads from the stack. This is just a hint, as some cases may be
133 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
134 const MachineMemOperand *&MMO,
135 int &FrameIndex) const {
139 /// isStoreToStackSlot - If the specified machine instruction is a direct
140 /// store to a stack slot, return the virtual or physical register number of
141 /// the source reg along with the FrameIndex of the loaded stack slot. If
142 /// not, return 0. This predicate must return 0 if the instruction has
143 /// any side effects other than storing to the stack slot.
144 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
145 int &FrameIndex) const {
149 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
150 /// stack locations as well. This uses a heuristic so it isn't
151 /// reliable for correctness.
152 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
153 int &FrameIndex) const {
157 /// hasStoreToStackSlot - If the specified machine instruction has a
158 /// store to a stack slot, return true along with the FrameIndex of
159 /// the loaded stack slot and the machine mem operand containing the
160 /// reference. If not, return false. Unlike isStoreToStackSlot,
161 /// this returns true for any instructions that stores to the
162 /// stack. This is just a hint, as some cases may be missed.
163 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
164 const MachineMemOperand *&MMO,
165 int &FrameIndex) const {
169 /// reMaterialize - Re-issue the specified 'original' instruction at the
170 /// specific location targeting a new destination register.
171 /// The register in Orig->getOperand(0).getReg() will be substituted by
172 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
174 virtual void reMaterialize(MachineBasicBlock &MBB,
175 MachineBasicBlock::iterator MI,
176 unsigned DestReg, unsigned SubIdx,
177 const MachineInstr *Orig,
178 const TargetRegisterInfo &TRI) const = 0;
180 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
181 /// two-addrss instruction inserted by two-address pass.
182 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
184 const TargetRegisterInfo &TRI) const {
188 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
189 /// MachineFunction::CloneMachineInstr(), but the target may update operands
190 /// that are required to be unique.
192 /// The instruction must be duplicable as indicated by isNotDuplicable().
193 virtual MachineInstr *duplicate(MachineInstr *Orig,
194 MachineFunction &MF) const = 0;
196 /// convertToThreeAddress - This method must be implemented by targets that
197 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
198 /// may be able to convert a two-address instruction into one or more true
199 /// three-address instructions on demand. This allows the X86 target (for
200 /// example) to convert ADD and SHL instructions into LEA instructions if they
201 /// would require register copies due to two-addressness.
203 /// This method returns a null pointer if the transformation cannot be
204 /// performed, otherwise it returns the last new instruction.
206 virtual MachineInstr *
207 convertToThreeAddress(MachineFunction::iterator &MFI,
208 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
212 /// commuteInstruction - If a target has any instructions that are
213 /// commutable but require converting to different instructions or making
214 /// non-trivial changes to commute them, this method can overloaded to do
215 /// that. The default implementation simply swaps the commutable operands.
216 /// If NewMI is false, MI is modified in place and returned; otherwise, a
217 /// new machine instruction is created and returned. Do not call this
218 /// method for a non-commutable instruction, but there may be some cases
219 /// where this method fails and returns null.
220 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
221 bool NewMI = false) const = 0;
223 /// findCommutedOpIndices - If specified MI is commutable, return the two
224 /// operand indices that would swap value. Return false if the instruction
225 /// is not in a form which this routine understands.
226 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
227 unsigned &SrcOpIdx2) const = 0;
229 /// produceSameValue - Return true if two machine instructions would produce
230 /// identical values. By default, this is only true when the two instructions
231 /// are deemed identical except for defs.
232 virtual bool produceSameValue(const MachineInstr *MI0,
233 const MachineInstr *MI1) const = 0;
235 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
236 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
237 /// implemented for a target). Upon success, this returns false and returns
238 /// with the following information in various cases:
240 /// 1. If this block ends with no branches (it just falls through to its succ)
241 /// just return false, leaving TBB/FBB null.
242 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
243 /// the destination block.
244 /// 3. If this block ends with a conditional branch and it falls through to a
245 /// successor block, it sets TBB to be the branch destination block and a
246 /// list of operands that evaluate the condition. These operands can be
247 /// passed to other TargetInstrInfo methods to create new branches.
248 /// 4. If this block ends with a conditional branch followed by an
249 /// unconditional branch, it returns the 'true' destination in TBB, the
250 /// 'false' destination in FBB, and a list of operands that evaluate the
251 /// condition. These operands can be passed to other TargetInstrInfo
252 /// methods to create new branches.
254 /// Note that RemoveBranch and InsertBranch must be implemented to support
255 /// cases where this method returns success.
257 /// If AllowModify is true, then this routine is allowed to modify the basic
258 /// block (e.g. delete instructions after the unconditional branch).
260 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
261 MachineBasicBlock *&FBB,
262 SmallVectorImpl<MachineOperand> &Cond,
263 bool AllowModify = false) const {
267 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
268 /// This is only invoked in cases where AnalyzeBranch returns success. It
269 /// returns the number of instructions that were removed.
270 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
271 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
275 /// InsertBranch - Insert branch code into the end of the specified
276 /// MachineBasicBlock. The operands to this method are the same as those
277 /// returned by AnalyzeBranch. This is only invoked in cases where
278 /// AnalyzeBranch returns success. It returns the number of instructions
281 /// It is also invoked by tail merging to add unconditional branches in
282 /// cases where AnalyzeBranch doesn't apply because there was no original
283 /// branch to analyze. At least this much must be implemented, else tail
284 /// merging needs to be disabled.
285 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
286 MachineBasicBlock *FBB,
287 const SmallVectorImpl<MachineOperand> &Cond,
289 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
293 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
294 /// after it, replacing it with an unconditional branch to NewDest. This is
295 /// used by the tail merging pass.
296 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
297 MachineBasicBlock *NewDest) const = 0;
299 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
300 /// block at the specified instruction (i.e. instruction would be the start
301 /// of a new basic block).
302 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
303 MachineBasicBlock::iterator MBBI) const {
307 /// isProfitableToIfCvt - Return true if it's profitable to predicate
308 /// instructions with accumulated instruction latency of "NumCycles"
309 /// of the specified basic block, where the probability of the instructions
310 /// being executed is given by Probability, and Confidence is a measure
311 /// of our confidence that it will be properly predicted.
313 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
314 unsigned ExtraPredCycles,
315 float Probability, float Confidence) const {
319 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
320 /// checks for the case where two basic blocks from true and false path
321 /// of a if-then-else (diamond) are predicated on mutally exclusive
322 /// predicates, where the probability of the true path being taken is given
323 /// by Probability, and Confidence is a measure of our confidence that it
324 /// will be properly predicted.
326 isProfitableToIfCvt(MachineBasicBlock &TMBB,
327 unsigned NumTCycles, unsigned ExtraTCycles,
328 MachineBasicBlock &FMBB,
329 unsigned NumFCycles, unsigned ExtraFCycles,
330 float Probability, float Confidence) const {
334 /// isProfitableToDupForIfCvt - Return true if it's profitable for
335 /// if-converter to duplicate instructions of specified accumulated
336 /// instruction latencies in the specified MBB to enable if-conversion.
337 /// The probability of the instructions being executed is given by
338 /// Probability, and Confidence is a measure of our confidence that it
339 /// will be properly predicted.
341 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
342 float Probability, float Confidence) const {
346 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
347 virtual void copyPhysReg(MachineBasicBlock &MBB,
348 MachineBasicBlock::iterator MI, DebugLoc DL,
349 unsigned DestReg, unsigned SrcReg,
350 bool KillSrc) const {
351 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
354 /// storeRegToStackSlot - Store the specified register of the given register
355 /// class to the specified stack frame index. The store instruction is to be
356 /// added to the given machine basic block before the specified machine
357 /// instruction. If isKill is true, the register operand is the last use and
358 /// must be marked kill.
359 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator MI,
361 unsigned SrcReg, bool isKill, int FrameIndex,
362 const TargetRegisterClass *RC,
363 const TargetRegisterInfo *TRI) const {
364 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
367 /// loadRegFromStackSlot - Load the specified register of the given register
368 /// class from the specified stack frame index. The load instruction is to be
369 /// added to the given machine basic block before the specified machine
371 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
372 MachineBasicBlock::iterator MI,
373 unsigned DestReg, int FrameIndex,
374 const TargetRegisterClass *RC,
375 const TargetRegisterInfo *TRI) const {
376 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
379 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
380 /// saved registers and returns true if it isn't possible / profitable to do
381 /// so by issuing a series of store instructions via
382 /// storeRegToStackSlot(). Returns false otherwise.
383 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
384 MachineBasicBlock::iterator MI,
385 const std::vector<CalleeSavedInfo> &CSI,
386 const TargetRegisterInfo *TRI) const {
390 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
391 /// saved registers and returns true if it isn't possible / profitable to do
392 /// so by issuing a series of load instructions via loadRegToStackSlot().
393 /// Returns false otherwise.
394 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
395 MachineBasicBlock::iterator MI,
396 const std::vector<CalleeSavedInfo> &CSI,
397 const TargetRegisterInfo *TRI) const {
401 /// emitFrameIndexDebugValue - Emit a target-dependent form of
402 /// DBG_VALUE encoding the address of a frame index. Addresses would
403 /// normally be lowered the same way as other addresses on the target,
404 /// e.g. in load instructions. For targets that do not support this
405 /// the debug info is simply lost.
406 /// If you add this for a target you should handle this DBG_VALUE in the
407 /// target-specific AsmPrinter code as well; you will probably get invalid
408 /// assembly output if you don't.
409 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
417 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
418 /// slot into the specified machine instruction for the specified operand(s).
419 /// If this is possible, a new instruction is returned with the specified
420 /// operand folded, otherwise NULL is returned.
421 /// The new instruction is inserted before MI, and the client is responsible
422 /// for removing the old instruction.
423 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
424 const SmallVectorImpl<unsigned> &Ops,
425 int FrameIndex) const;
427 /// foldMemoryOperand - Same as the previous version except it allows folding
428 /// of any load and store from / to any address, not just from a specific
430 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
431 const SmallVectorImpl<unsigned> &Ops,
432 MachineInstr* LoadMI) const;
435 /// foldMemoryOperandImpl - Target-dependent implementation for
436 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
437 /// take care of adding a MachineMemOperand to the newly created instruction.
438 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
440 const SmallVectorImpl<unsigned> &Ops,
441 int FrameIndex) const {
445 /// foldMemoryOperandImpl - Target-dependent implementation for
446 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
447 /// take care of adding a MachineMemOperand to the newly created instruction.
448 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
450 const SmallVectorImpl<unsigned> &Ops,
451 MachineInstr* LoadMI) const {
456 /// canFoldMemoryOperand - Returns true for the specified load / store if
457 /// folding is possible.
459 bool canFoldMemoryOperand(const MachineInstr *MI,
460 const SmallVectorImpl<unsigned> &Ops) const =0;
462 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
463 /// a store or a load and a store into two or more instruction. If this is
464 /// possible, returns true as well as the new instructions by reference.
465 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
466 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
467 SmallVectorImpl<MachineInstr*> &NewMIs) const{
471 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
472 SmallVectorImpl<SDNode*> &NewNodes) const {
476 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
477 /// instruction after load / store are unfolded from an instruction of the
478 /// specified opcode. It returns zero if the specified unfolding is not
479 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
480 /// index of the operand which will hold the register holding the loaded
482 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
483 bool UnfoldLoad, bool UnfoldStore,
484 unsigned *LoadRegIndex = 0) const {
488 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
489 /// to determine if two loads are loading from the same base address. It
490 /// should only return true if the base pointers are the same and the
491 /// only differences between the two addresses are the offset. It also returns
492 /// the offsets by reference.
493 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
494 int64_t &Offset1, int64_t &Offset2) const {
498 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
499 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
500 /// be scheduled togther. On some targets if two loads are loading from
501 /// addresses in the same cache line, it's better if they are scheduled
502 /// together. This function takes two integers that represent the load offsets
503 /// from the common base address. It returns true if it decides it's desirable
504 /// to schedule the two loads together. "NumLoads" is the number of loads that
505 /// have already been scheduled after Load1.
506 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
507 int64_t Offset1, int64_t Offset2,
508 unsigned NumLoads) const {
512 /// ReverseBranchCondition - Reverses the branch condition of the specified
513 /// condition list, returning false on success and true if it cannot be
516 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
520 /// insertNoop - Insert a noop into the instruction stream at the specified
522 virtual void insertNoop(MachineBasicBlock &MBB,
523 MachineBasicBlock::iterator MI) const;
526 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
527 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
528 // Default to just using 'nop' string.
532 /// isPredicated - Returns true if the instruction is already predicated.
534 virtual bool isPredicated(const MachineInstr *MI) const {
538 /// isUnpredicatedTerminator - Returns true if the instruction is a
539 /// terminator instruction that has not been predicated.
540 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
542 /// PredicateInstruction - Convert the instruction into a predicated
543 /// instruction. It returns true if the operation was successful.
545 bool PredicateInstruction(MachineInstr *MI,
546 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
548 /// SubsumesPredicate - Returns true if the first specified predicate
549 /// subsumes the second, e.g. GE subsumes GT.
551 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
552 const SmallVectorImpl<MachineOperand> &Pred2) const {
556 /// DefinesPredicate - If the specified instruction defines any predicate
557 /// or condition code register(s) used for predication, returns true as well
558 /// as the definition predicate(s) by reference.
559 virtual bool DefinesPredicate(MachineInstr *MI,
560 std::vector<MachineOperand> &Pred) const {
564 /// isPredicable - Return true if the specified instruction can be predicated.
565 /// By default, this returns true for every instruction with a
566 /// PredicateOperand.
567 virtual bool isPredicable(MachineInstr *MI) const {
568 return MI->getDesc().isPredicable();
571 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
572 /// instruction that defines the specified register class.
573 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
577 /// isSchedulingBoundary - Test if the given instruction should be
578 /// considered a scheduling boundary. This primarily includes labels and
580 virtual bool isSchedulingBoundary(const MachineInstr *MI,
581 const MachineBasicBlock *MBB,
582 const MachineFunction &MF) const = 0;
584 /// Measure the specified inline asm to determine an approximation of its
586 virtual unsigned getInlineAsmLength(const char *Str,
587 const MCAsmInfo &MAI) const;
589 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer
590 /// to use for this target when scheduling the machine instructions after
591 /// register allocation.
592 virtual ScheduleHazardRecognizer*
593 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const = 0;
595 /// AnalyzeCompare - For a comparison instruction, return the source register
596 /// in SrcReg and the value it compares against in CmpValue. Return true if
597 /// the comparison instruction can be analyzed.
598 virtual bool AnalyzeCompare(const MachineInstr *MI,
599 unsigned &SrcReg, int &Mask, int &Value) const {
603 /// OptimizeCompareInstr - See if the comparison instruction can be converted
604 /// into something more efficient. E.g., on ARM most instructions can set the
605 /// flags register, obviating the need for a separate CMP. Update the iterator
606 /// *only* if a transformation took place.
607 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
608 unsigned SrcReg, int Mask, int Value,
609 const MachineRegisterInfo *MRI,
610 MachineBasicBlock::iterator &) const {
614 /// getNumMicroOps - Return the number of u-operations the given machine
615 /// instruction will be decoded to on the target cpu.
616 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
617 const MachineInstr *MI) const;
619 /// getOperandLatency - Compute and return the use operand latency of a given
620 /// pair of def and use.
621 /// In most cases, the static scheduling itinerary was enough to determine the
622 /// operand latency. But it may not be possible for instructions with variable
623 /// number of defs / uses.
624 virtual int getOperandLatency(const InstrItineraryData *ItinData,
625 const MachineInstr *DefMI, unsigned DefIdx,
626 const MachineInstr *UseMI, unsigned UseIdx) const;
628 virtual int getOperandLatency(const InstrItineraryData *ItinData,
629 SDNode *DefNode, unsigned DefIdx,
630 SDNode *UseNode, unsigned UseIdx) const;
632 /// getInstrLatency - Compute the instruction latency of a given instruction.
633 /// If the instruction has higher cost when predicated, it's returned via
635 virtual int getInstrLatency(const InstrItineraryData *ItinData,
636 const MachineInstr *MI,
637 unsigned *PredCost = 0) const;
639 virtual int getInstrLatency(const InstrItineraryData *ItinData,
642 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
643 /// and an use in the current loop, return true if the target considered
644 /// it 'high'. This is used by optimization passes such as machine LICM to
645 /// determine whether it makes sense to hoist an instruction out even in
646 /// high register pressure situation.
648 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
649 const MachineRegisterInfo *MRI,
650 const MachineInstr *DefMI, unsigned DefIdx,
651 const MachineInstr *UseMI, unsigned UseIdx) const {
655 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
656 /// if the target considered it 'low'.
658 bool hasLowDefLatency(const InstrItineraryData *ItinData,
659 const MachineInstr *DefMI, unsigned DefIdx) const;
662 /// TargetInstrInfoImpl - This is the default implementation of
663 /// TargetInstrInfo, which just provides a couple of default implementations
664 /// for various methods. This separated out because it is implemented in
665 /// libcodegen, not in libtarget.
666 class TargetInstrInfoImpl : public TargetInstrInfo {
668 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
669 : TargetInstrInfo(desc, NumOpcodes) {}
671 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
672 MachineBasicBlock *NewDest) const;
673 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
674 bool NewMI = false) const;
675 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
676 unsigned &SrcOpIdx2) const;
677 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
678 const SmallVectorImpl<unsigned> &Ops) const;
679 virtual bool PredicateInstruction(MachineInstr *MI,
680 const SmallVectorImpl<MachineOperand> &Pred) const;
681 virtual void reMaterialize(MachineBasicBlock &MBB,
682 MachineBasicBlock::iterator MI,
683 unsigned DestReg, unsigned SubReg,
684 const MachineInstr *Orig,
685 const TargetRegisterInfo &TRI) const;
686 virtual MachineInstr *duplicate(MachineInstr *Orig,
687 MachineFunction &MF) const;
688 virtual bool produceSameValue(const MachineInstr *MI0,
689 const MachineInstr *MI1) const;
690 virtual bool isSchedulingBoundary(const MachineInstr *MI,
691 const MachineBasicBlock *MBB,
692 const MachineFunction &MF) const;
694 virtual ScheduleHazardRecognizer *
695 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const;
698 } // End llvm namespace