1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class MachineCodeForInstruction;
28 class TargetRegisterClass;
31 //---------------------------------------------------------------------------
32 // Data types used to define information about a single machine instruction
33 //---------------------------------------------------------------------------
35 typedef short MachineOpCode;
36 typedef unsigned InstrSchedClass;
38 //---------------------------------------------------------------------------
39 // struct TargetInstrDescriptor:
40 // Predefined information about each machine instruction.
41 // Designed to initialized statically.
44 const unsigned M_BRANCH_FLAG = 1 << 0;
45 const unsigned M_CALL_FLAG = 1 << 1;
46 const unsigned M_RET_FLAG = 1 << 2;
47 const unsigned M_BARRIER_FLAG = 1 << 3;
48 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
49 const unsigned M_LOAD_FLAG = 1 << 5;
50 const unsigned M_STORE_FLAG = 1 << 6;
52 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
53 // changed into a 3-address instruction if the first two operands cannot be
54 // assigned to the same register. The target must implement the
55 // TargetInstrInfo::convertToThreeAddress method for this instruction.
56 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
58 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
59 // Z), which produces the same result if Y and Z are exchanged.
60 const unsigned M_COMMUTABLE = 1 << 8;
62 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
63 // block? Typically this is things like return and branch instructions.
64 // Various passes use this to insert code into the bottom of a basic block, but
65 // before control flow occurs.
66 const unsigned M_TERMINATOR_FLAG = 1 << 9;
68 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
69 // insertion support when the DAG scheduler is inserting it into a machine basic
71 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
73 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
74 // operands in addition to the minimum number operands specified.
75 const unsigned M_VARIABLE_OPS = 1 << 11;
77 // M_PREDICATED - Set if this instruction has a predicate that controls its
79 const unsigned M_PREDICATED = 1 << 12;
81 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
82 // at any time, e.g. constant generation, load from constant pool.
83 const unsigned M_REMATERIALIZIBLE = 1 << 13;
86 // Machine operand flags
87 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
88 // requires a callback to look up its register class.
89 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
91 /// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate
92 /// operand that controls an M_PREDICATED instruction.
93 const unsigned M_PREDICATE_OPERAND = 1 << 1;
96 // Operand constraints: only "tied_to" for now.
97 enum OperandConstraint {
98 TIED_TO = 0 // Must be allocated the same register as.
102 /// TargetOperandInfo - This holds information about one operand of a machine
103 /// instruction, indicating the register class for register operands, etc.
105 class TargetOperandInfo {
107 /// RegClass - This specifies the register class enumeration of the operand
108 /// if the operand is a register. If not, this contains 0.
109 unsigned short RegClass;
110 unsigned short Flags;
111 /// Lower 16 bits are used to specify which constraints are set. The higher 16
112 /// bits are used to specify the value of constraints (4 bits each).
113 unsigned int Constraints;
114 /// Currently no other information.
118 class TargetInstrDescriptor {
120 MachineOpCode Opcode; // The opcode.
121 unsigned short numOperands; // Num of args (may be more if variable_ops).
122 const char * Name; // Assembly language mnemonic for the opcode.
123 InstrSchedClass schedClass; // enum identifying instr sched class
124 unsigned Flags; // flags identifying machine instr class
125 unsigned TSFlags; // Target Specific Flag values
126 const unsigned *ImplicitUses; // Registers implicitly read by this instr
127 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
128 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
130 /// getOperandConstraint - Returns the value of the specific constraint if
131 /// it is set. Returns -1 if it is not set.
132 int getOperandConstraint(unsigned OpNum,
133 TOI::OperandConstraint Constraint) const {
134 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
135 "Invalid operand # of TargetInstrInfo");
136 if (OpNum < numOperands &&
137 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
138 unsigned Pos = 16 + Constraint * 4;
139 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
144 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
145 /// dest operand. Returns -1 if there isn't one.
146 int findTiedToSrcOperand(unsigned OpNum) const;
150 //---------------------------------------------------------------------------
152 /// TargetInstrInfo - Interface to description of machine instructions
154 class TargetInstrInfo {
155 const TargetInstrDescriptor* desc; // raw array to allow static init'n
156 unsigned NumOpcodes; // number of entries in the desc array
157 unsigned numRealOpCodes; // number of non-dummy op codes
159 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
160 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
162 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
163 virtual ~TargetInstrInfo();
165 // Invariant opcodes: All instruction sets have these as their low opcodes.
172 unsigned getNumOpcodes() const { return NumOpcodes; }
174 /// get - Return the machine instruction descriptor that corresponds to the
175 /// specified instruction opcode.
177 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
178 assert((unsigned)Opcode < NumOpcodes);
182 const char *getName(MachineOpCode Opcode) const {
183 return get(Opcode).Name;
186 int getNumOperands(MachineOpCode Opcode) const {
187 return get(Opcode).numOperands;
190 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
191 return get(Opcode).schedClass;
194 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
195 return get(Opcode).ImplicitUses;
198 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
199 return get(Opcode).ImplicitDefs;
204 // Query instruction class flags according to the machine-independent
205 // flags listed above.
207 bool isReturn(MachineOpCode Opcode) const {
208 return get(Opcode).Flags & M_RET_FLAG;
211 bool isPredicated(MachineOpCode Opcode) const {
212 return get(Opcode).Flags & M_PREDICATED;
214 bool isReMaterializable(MachineOpCode Opcode) const {
215 return get(Opcode).Flags & M_REMATERIALIZIBLE;
217 bool isCommutableInstr(MachineOpCode Opcode) const {
218 return get(Opcode).Flags & M_COMMUTABLE;
220 bool isTerminatorInstr(unsigned Opcode) const {
221 return get(Opcode).Flags & M_TERMINATOR_FLAG;
224 bool isBranch(MachineOpCode Opcode) const {
225 return get(Opcode).Flags & M_BRANCH_FLAG;
228 /// isBarrier - Returns true if the specified instruction stops control flow
229 /// from executing the instruction immediately following it. Examples include
230 /// unconditional branches and return instructions.
231 bool isBarrier(MachineOpCode Opcode) const {
232 return get(Opcode).Flags & M_BARRIER_FLAG;
235 bool isCall(MachineOpCode Opcode) const {
236 return get(Opcode).Flags & M_CALL_FLAG;
238 bool isLoad(MachineOpCode Opcode) const {
239 return get(Opcode).Flags & M_LOAD_FLAG;
241 bool isStore(MachineOpCode Opcode) const {
242 return get(Opcode).Flags & M_STORE_FLAG;
245 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
246 /// which must be filled by the code generator.
247 bool hasDelaySlot(unsigned Opcode) const {
248 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
251 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
252 /// custom insertion support when the DAG scheduler is inserting it into a
253 /// machine basic block.
254 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
255 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
258 bool hasVariableOperands(MachineOpCode Opcode) const {
259 return get(Opcode).Flags & M_VARIABLE_OPS;
262 /// getOperandConstraint - Returns the value of the specific constraint if
263 /// it is set. Returns -1 if it is not set.
264 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
265 TOI::OperandConstraint Constraint) const {
266 return get(Opcode).getOperandConstraint(OpNum, Constraint);
269 /// Return true if the instruction is a register to register move
270 /// and leave the source and dest operands in the passed parameters.
271 virtual bool isMoveInstr(const MachineInstr& MI,
273 unsigned& destReg) const {
277 /// isLoadFromStackSlot - If the specified machine instruction is a direct
278 /// load from a stack slot, return the virtual or physical register number of
279 /// the destination along with the FrameIndex of the loaded stack slot. If
280 /// not, return 0. This predicate must return 0 if the instruction has
281 /// any side effects other than loading from the stack slot.
282 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
286 /// isStoreToStackSlot - If the specified machine instruction is a direct
287 /// store to a stack slot, return the virtual or physical register number of
288 /// the source reg along with the FrameIndex of the loaded stack slot. If
289 /// not, return 0. This predicate must return 0 if the instruction has
290 /// any side effects other than storing to the stack slot.
291 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
295 /// convertToThreeAddress - This method must be implemented by targets that
296 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
297 /// may be able to convert a two-address instruction into one or moretrue
298 /// three-address instructions on demand. This allows the X86 target (for
299 /// example) to convert ADD and SHL instructions into LEA instructions if they
300 /// would require register copies due to two-addressness.
302 /// This method returns a null pointer if the transformation cannot be
303 /// performed, otherwise it returns the last new instruction.
305 virtual MachineInstr *
306 convertToThreeAddress(MachineFunction::iterator &MFI,
307 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
311 /// commuteInstruction - If a target has any instructions that are commutable,
312 /// but require converting to a different instruction or making non-trivial
313 /// changes to commute them, this method can overloaded to do this. The
314 /// default implementation of this method simply swaps the first two operands
315 /// of MI and returns it.
317 /// If a target wants to make more aggressive changes, they can construct and
318 /// return a new machine instruction. If an instruction cannot commute, it
319 /// can also return null.
321 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
323 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
324 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
325 /// implemented for a target). Upon success, this returns false and returns
326 /// with the following information in various cases:
328 /// 1. If this block ends with no branches (it just falls through to its succ)
329 /// just return false, leaving TBB/FBB null.
330 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
331 /// the destination block.
332 /// 3. If this block ends with an conditional branch, it returns the 'true'
333 /// destination in TBB, the 'false' destination in FBB, and a list of
334 /// operands that evaluate the condition. These operands can be passed to
335 /// other TargetInstrInfo methods to create new branches.
337 /// Note that RemoveBranch and InsertBranch must be implemented to support
338 /// cases where this method returns success.
340 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
341 MachineBasicBlock *&FBB,
342 std::vector<MachineOperand> &Cond) const {
346 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
347 /// this is only invoked in cases where AnalyzeBranch returns success.
348 virtual void RemoveBranch(MachineBasicBlock &MBB) const {
349 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
352 /// InsertBranch - Insert a branch into the end of the specified
353 /// MachineBasicBlock. This operands to this method are the same as those
354 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
355 /// returns success and when an unconditional branch (TBB is non-null, FBB is
356 /// null, Cond is empty) needs to be inserted.
357 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
358 MachineBasicBlock *FBB,
359 const std::vector<MachineOperand> &Cond) const {
360 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
363 /// BlockHasNoFallThrough - Return true if the specified block does not
364 /// fall-through into its successor block. This is primarily used when a
365 /// branch is unanalyzable. It is useful for things like unconditional
366 /// indirect branches (jump tables).
367 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
371 /// ReverseBranchCondition - Reverses the branch condition of the specified
372 /// condition list, returning false on success and true if it cannot be
374 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
378 /// insertNoop - Insert a noop into the instruction stream at the specified
380 virtual void insertNoop(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator MI) const {
382 assert(0 && "Target didn't implement insertNoop!");
386 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
388 virtual const TargetRegisterClass *getPointerRegClass() const {
389 assert(0 && "Target didn't implement getPointerRegClass!");
391 return 0; // Must return a value in order to compile with VS 2005
395 } // End llvm namespace