1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "llvm/Target/TargetMachine.h"
11 #include "Support/DataTypes.h"
14 class MachineInstrDescriptor;
21 typedef int InstrSchedClass;
23 // Global variable holding an array of descriptors for machine instructions.
24 // The actual object needs to be created separately for each target machine.
25 // This variable is initialized and reset by class MachineInstrInfo.
27 // FIXME: This should be a property of the target so that more than one target
28 // at a time can be active...
30 extern const MachineInstrDescriptor *TargetInstrDescriptors;
33 //---------------------------------------------------------------------------
34 // struct MachineInstrDescriptor:
35 // Predefined information about each machine instruction.
36 // Designed to initialized statically.
38 // class MachineInstructionInfo
39 // Interface to description of machine instructions
41 //---------------------------------------------------------------------------
44 const unsigned int M_NOP_FLAG = 1;
45 const unsigned int M_BRANCH_FLAG = 1 << 1;
46 const unsigned int M_CALL_FLAG = 1 << 2;
47 const unsigned int M_RET_FLAG = 1 << 3;
48 const unsigned int M_ARITH_FLAG = 1 << 4;
49 const unsigned int M_CC_FLAG = 1 << 6;
50 const unsigned int M_LOGICAL_FLAG = 1 << 6;
51 const unsigned int M_INT_FLAG = 1 << 7;
52 const unsigned int M_FLOAT_FLAG = 1 << 8;
53 const unsigned int M_CONDL_FLAG = 1 << 9;
54 const unsigned int M_LOAD_FLAG = 1 << 10;
55 const unsigned int M_PREFETCH_FLAG = 1 << 11;
56 const unsigned int M_STORE_FLAG = 1 << 12;
57 const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
58 const unsigned int M_PSEUDO_FLAG = 1 << 14;
61 struct MachineInstrDescriptor {
62 string opCodeString; // Assembly language mnemonic for the opcode.
63 int numOperands; // Number of args; -1 if variable #args
64 int resultPos; // Position of the result; -1 if no result
65 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
66 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
67 // smallest -ve value is -(maxImmedConst+1).
68 unsigned int numDelaySlots; // Number of delay slots after instruction
69 unsigned int latency; // Latency in machine cycles
70 InstrSchedClass schedClass; // enum identifying instr sched class
71 unsigned int iclass; // flags identifying machine instr class
75 class MachineInstrInfo : public NonCopyableV {
77 const TargetMachine& target;
80 const MachineInstrDescriptor* desc; // raw array to allow static init'n
81 unsigned int descSize; // number of entries in the desc array
82 unsigned int numRealOpCodes; // number of non-dummy op codes
85 MachineInstrInfo(const TargetMachine& tgt,
86 const MachineInstrDescriptor *desc, unsigned descSize,
87 unsigned numRealOpCodes);
88 virtual ~MachineInstrInfo();
90 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
91 unsigned getNumTotalOpCodes() const { return descSize; }
93 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
94 assert(opCode >= 0 && opCode < (int)descSize);
98 int getNumOperands(MachineOpCode opCode) const {
99 return getDescriptor(opCode).numOperands;
102 int getResultPos(MachineOpCode opCode) const {
103 return getDescriptor(opCode).resultPos;
106 unsigned getNumDelaySlots(MachineOpCode opCode) const {
107 return getDescriptor(opCode).numDelaySlots;
110 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
111 return getDescriptor(opCode).schedClass;
115 // Query instruction class flags according to the machine-independent
116 // flags listed above.
118 unsigned int getIClass(MachineOpCode opCode) const {
119 return getDescriptor(opCode).iclass;
121 bool isNop(MachineOpCode opCode) const {
122 return getDescriptor(opCode).iclass & M_NOP_FLAG;
124 bool isBranch(MachineOpCode opCode) const {
125 return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
127 bool isCall(MachineOpCode opCode) const {
128 return getDescriptor(opCode).iclass & M_CALL_FLAG;
130 bool isReturn(MachineOpCode opCode) const {
131 return getDescriptor(opCode).iclass & M_RET_FLAG;
133 bool isControlFlow(MachineOpCode opCode) const {
134 return getDescriptor(opCode).iclass & M_BRANCH_FLAG
135 || getDescriptor(opCode).iclass & M_CALL_FLAG
136 || getDescriptor(opCode).iclass & M_RET_FLAG;
138 bool isArith(MachineOpCode opCode) const {
139 return getDescriptor(opCode).iclass & M_RET_FLAG;
141 bool isCCInstr(MachineOpCode opCode) const {
142 return getDescriptor(opCode).iclass & M_CC_FLAG;
144 bool isLogical(MachineOpCode opCode) const {
145 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
147 bool isIntInstr(MachineOpCode opCode) const {
148 return getDescriptor(opCode).iclass & M_INT_FLAG;
150 bool isFloatInstr(MachineOpCode opCode) const {
151 return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
153 bool isConditional(MachineOpCode opCode) const {
154 return getDescriptor(opCode).iclass & M_CONDL_FLAG;
156 bool isLoad(MachineOpCode opCode) const {
157 return getDescriptor(opCode).iclass & M_LOAD_FLAG;
159 bool isPrefetch(MachineOpCode opCode) const {
160 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
162 bool isLoadOrPrefetch(MachineOpCode opCode) const {
163 return getDescriptor(opCode).iclass & M_LOAD_FLAG
164 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
166 bool isStore(MachineOpCode opCode) const {
167 return getDescriptor(opCode).iclass & M_STORE_FLAG;
169 bool isMemoryAccess(MachineOpCode opCode) const {
170 return getDescriptor(opCode).iclass & M_LOAD_FLAG
171 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG
172 || getDescriptor(opCode).iclass & M_STORE_FLAG;
174 bool isDummyPhiInstr(const MachineOpCode opCode) const {
175 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
179 // delete this later *******
180 bool isPhi(const MachineOpCode opCode) const
181 { return isDummyPhiInstr(opCode); }
183 bool isPseudoInstr(const MachineOpCode opCode) const {
184 return getDescriptor(opCode).iclass & M_PSEUDO_FLAG;
189 // Check if an instruction can be issued before its operands are ready,
190 // or if a subsequent instruction that uses its result can be issued
191 // before the results are ready.
192 // Default to true since most instructions on many architectures allow this.
194 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
198 virtual bool hasResultInterlock(MachineOpCode opCode) const {
203 // Latencies for individual instructions and instruction pairs
205 virtual int minLatency(MachineOpCode opCode) const {
206 return getDescriptor(opCode).latency;
209 virtual int maxLatency(MachineOpCode opCode) const {
210 return getDescriptor(opCode).latency;
214 // Which operand holds an immediate constant? Returns -1 if none
216 virtual int getImmmedConstantPos(MachineOpCode opCode) const {
217 return -1; // immediate position is machine specific, so say -1 == "none"
220 // Check if the specified constant fits in the immediate field
221 // of this machine instruction
223 virtual bool constantFitsInImmedField(MachineOpCode opCode,
224 int64_t intValue) const;
226 // Return the largest +ve constant that can be held in the IMMMED field
227 // of this machine instruction.
228 // isSignExtended is set to true if the value is sign-extended before use
229 // (this is true for all immediate fields in SPARC instructions).
230 // Return 0 if the instruction has no IMMED field.
232 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
233 bool &isSignExtended) const {
234 isSignExtended = getDescriptor(opCode).immedIsSignExtended;
235 return getDescriptor(opCode).maxImmedConst;
238 //-------------------------------------------------------------------------
239 // Code generation support for creating individual machine instructions
240 //-------------------------------------------------------------------------
242 // Create an instruction sequence to put the constant `val' into
243 // the virtual register `dest'. `val' may be a Constant or a
244 // GlobalValue, viz., the constant address of a global variable or function.
245 // The generated instructions are returned in `minstrVec'.
246 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
248 virtual void CreateCodeToLoadConst(Value* val,
250 vector<MachineInstr*>& minstrVec,
251 vector<TmpInstruction*>& temps) const =0;
253 // Create an instruction sequence to copy an integer value `val'
254 // to a floating point value `dest' by copying to memory and back.
255 // val must be an integral type. dest must be a Float or Double.
256 // The generated instructions are returned in `minstrVec'.
257 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
259 virtual void CreateCodeToCopyIntToFloat(Method* method,
262 vector<MachineInstr*>& minstrVec,
263 vector<TmpInstruction*>& tempVec,
264 TargetMachine& target) const = 0;
266 // Similarly, create an instruction sequence to copy an FP value
267 // `val' to an integer value `dest' by copying to memory and back.
268 // See the previous function for information about return values.
270 virtual void CreateCodeToCopyFloatToInt(Method* method,
273 vector<MachineInstr*>& minstrVec,
274 vector<TmpInstruction*>& tempVec,
275 TargetMachine& target) const = 0;
278 // create copy instruction(s)
280 CreateCopyInstructionsByType(const TargetMachine& target,
283 vector<MachineInstr*>& minstrVec) const = 0;