1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineCombinerPattern.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
26 class InstrItineraryData;
29 class MachineMemOperand;
30 class MachineRegisterInfo;
34 class MCSymbolRefExpr;
35 class RandomNumberGenerator;
37 class ScheduleHazardRecognizer;
40 class TargetRegisterClass;
41 class TargetRegisterInfo;
42 class BranchProbability;
43 class TargetSubtargetInfo;
46 template<class T> class SmallVectorImpl;
49 //---------------------------------------------------------------------------
51 /// TargetInstrInfo - Interface to description of machine instruction set
53 class TargetInstrInfo : public MCInstrInfo {
54 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
55 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
57 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
58 : CallFrameSetupOpcode(CFSetupOpcode),
59 CallFrameDestroyOpcode(CFDestroyOpcode) {
62 virtual ~TargetInstrInfo();
64 /// getRegClass - Givem a machine instruction descriptor, returns the register
65 /// class constraint for OpNum, or NULL.
66 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
68 const TargetRegisterInfo *TRI,
69 const MachineFunction &MF) const;
71 /// isTriviallyReMaterializable - Return true if the instruction is trivially
72 /// rematerializable, meaning it has no side effects and requires no operands
73 /// that aren't always available.
74 bool isTriviallyReMaterializable(const MachineInstr *MI,
75 AliasAnalysis *AA = nullptr) const {
76 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
77 (MI->getDesc().isRematerializable() &&
78 (isReallyTriviallyReMaterializable(MI, AA) ||
79 isReallyTriviallyReMaterializableGeneric(MI, AA)));
83 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
84 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
85 /// specify whether the instruction is actually trivially rematerializable,
86 /// taking into consideration its operands. This predicate must return false
87 /// if the instruction has any side effects other than producing a value, or
88 /// if it requres any address registers that are not always available.
89 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
90 AliasAnalysis *AA) const {
95 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
96 /// for which the M_REMATERIALIZABLE flag is set and the target hook
97 /// isReallyTriviallyReMaterializable returns false, this function does
98 /// target-independent tests to determine if the instruction is really
99 /// trivially rematerializable.
100 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
101 AliasAnalysis *AA) const;
104 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
105 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
106 /// targets use pseudo instructions in order to abstract away the difference
107 /// between operating with a frame pointer and operating without, through the
108 /// use of these two instructions.
110 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
111 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
113 /// Returns the actual stack pointer adjustment made by an instruction
114 /// as part of a call sequence. By default, only call frame setup/destroy
115 /// instructions adjust the stack, but targets may want to override this
116 /// to enable more fine-grained adjustment, or adjust by a different value.
117 virtual int getSPAdjust(const MachineInstr *MI) const;
119 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
120 /// extension instruction. That is, it's like a copy where it's legal for the
121 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
122 /// true, then it's expected the pre-extension value is available as a subreg
123 /// of the result register. This also returns the sub-register index in
125 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
126 unsigned &SrcReg, unsigned &DstReg,
127 unsigned &SubIdx) const {
131 /// isLoadFromStackSlot - If the specified machine instruction is a direct
132 /// load from a stack slot, return the virtual or physical register number of
133 /// the destination along with the FrameIndex of the loaded stack slot. If
134 /// not, return 0. This predicate must return 0 if the instruction has
135 /// any side effects other than loading from the stack slot.
136 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
137 int &FrameIndex) const {
141 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
142 /// stack locations as well. This uses a heuristic so it isn't
143 /// reliable for correctness.
144 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
145 int &FrameIndex) const {
149 /// hasLoadFromStackSlot - If the specified machine instruction has
150 /// a load from a stack slot, return true along with the FrameIndex
151 /// of the loaded stack slot and the machine mem operand containing
152 /// the reference. If not, return false. Unlike
153 /// isLoadFromStackSlot, this returns true for any instructions that
154 /// loads from the stack. This is just a hint, as some cases may be
156 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
157 const MachineMemOperand *&MMO,
158 int &FrameIndex) const;
160 /// isStoreToStackSlot - If the specified machine instruction is a direct
161 /// store to a stack slot, return the virtual or physical register number of
162 /// the source reg along with the FrameIndex of the loaded stack slot. If
163 /// not, return 0. This predicate must return 0 if the instruction has
164 /// any side effects other than storing to the stack slot.
165 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
166 int &FrameIndex) const {
170 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
171 /// stack locations as well. This uses a heuristic so it isn't
172 /// reliable for correctness.
173 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
174 int &FrameIndex) const {
178 /// hasStoreToStackSlot - If the specified machine instruction has a
179 /// store to a stack slot, return true along with the FrameIndex of
180 /// the loaded stack slot and the machine mem operand containing the
181 /// reference. If not, return false. Unlike isStoreToStackSlot,
182 /// this returns true for any instructions that stores to the
183 /// stack. This is just a hint, as some cases may be missed.
184 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
185 const MachineMemOperand *&MMO,
186 int &FrameIndex) const;
188 /// isStackSlotCopy - Return true if the specified machine instruction
189 /// is a copy of one stack slot to another and has no other effect.
190 /// Provide the identity of the two frame indices.
191 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
192 int &SrcFrameIndex) const {
196 /// Compute the size in bytes and offset within a stack slot of a spilled
197 /// register or subregister.
199 /// \param [out] Size in bytes of the spilled value.
200 /// \param [out] Offset in bytes within the stack slot.
201 /// \returns true if both Size and Offset are successfully computed.
203 /// Not all subregisters have computable spill slots. For example,
204 /// subregisters registers may not be byte-sized, and a pair of discontiguous
205 /// subregisters has no single offset.
207 /// Targets with nontrivial bigendian implementations may need to override
208 /// this, particularly to support spilled vector registers.
209 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
210 unsigned &Size, unsigned &Offset,
211 const TargetMachine *TM) const;
213 /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move
216 /// Targets for different archs need to override this, and different
217 /// micro-architectures can also be finely tuned inside.
218 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const {
219 return MI->isAsCheapAsAMove();
222 /// reMaterialize - Re-issue the specified 'original' instruction at the
223 /// specific location targeting a new destination register.
224 /// The register in Orig->getOperand(0).getReg() will be substituted by
225 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
227 virtual void reMaterialize(MachineBasicBlock &MBB,
228 MachineBasicBlock::iterator MI,
229 unsigned DestReg, unsigned SubIdx,
230 const MachineInstr *Orig,
231 const TargetRegisterInfo &TRI) const;
233 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
234 /// MachineFunction::CloneMachineInstr(), but the target may update operands
235 /// that are required to be unique.
237 /// The instruction must be duplicable as indicated by isNotDuplicable().
238 virtual MachineInstr *duplicate(MachineInstr *Orig,
239 MachineFunction &MF) const;
241 /// convertToThreeAddress - This method must be implemented by targets that
242 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
243 /// may be able to convert a two-address instruction into one or more true
244 /// three-address instructions on demand. This allows the X86 target (for
245 /// example) to convert ADD and SHL instructions into LEA instructions if they
246 /// would require register copies due to two-addressness.
248 /// This method returns a null pointer if the transformation cannot be
249 /// performed, otherwise it returns the last new instruction.
251 virtual MachineInstr *
252 convertToThreeAddress(MachineFunction::iterator &MFI,
253 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
257 /// commuteInstruction - If a target has any instructions that are
258 /// commutable but require converting to different instructions or making
259 /// non-trivial changes to commute them, this method can overloaded to do
260 /// that. The default implementation simply swaps the commutable operands.
261 /// If NewMI is false, MI is modified in place and returned; otherwise, a
262 /// new machine instruction is created and returned. Do not call this
263 /// method for a non-commutable instruction, but there may be some cases
264 /// where this method fails and returns null.
265 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
266 bool NewMI = false) const;
268 /// findCommutedOpIndices - If specified MI is commutable, return the two
269 /// operand indices that would swap value. Return false if the instruction
270 /// is not in a form which this routine understands.
271 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
272 unsigned &SrcOpIdx2) const;
274 /// A pair composed of a register and a sub-register index.
275 /// Used to give some type checking when modeling Reg:SubReg.
276 struct RegSubRegPair {
279 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
280 : Reg(Reg), SubReg(SubReg) {}
282 /// A pair composed of a pair of a register and a sub-register index,
283 /// and another sub-register index.
284 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
285 struct RegSubRegPairAndIdx : RegSubRegPair {
287 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
289 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
292 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
294 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
295 /// the list is modeled as <Reg:SubReg, SubIdx>.
296 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
298 /// - vreg1:sub1, sub0
299 /// - vreg2<:0>, sub1
301 /// \returns true if it is possible to build such an input sequence
302 /// with the pair \p MI, \p DefIdx. False otherwise.
304 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
306 /// \note The generic implementation does not provide any support for
307 /// MI.isRegSequenceLike(). In other words, one has to override
308 /// getRegSequenceLikeInputs for target specific instructions.
310 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
311 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
313 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
315 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
316 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
317 /// - vreg1:sub1, sub0
319 /// \returns true if it is possible to build such an input sequence
320 /// with the pair \p MI, \p DefIdx. False otherwise.
322 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
324 /// \note The generic implementation does not provide any support for
325 /// MI.isExtractSubregLike(). In other words, one has to override
326 /// getExtractSubregLikeInputs for target specific instructions.
328 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
329 RegSubRegPairAndIdx &InputReg) const;
331 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
333 /// \p [out] BaseReg and \p [out] InsertedReg contain
334 /// the equivalent inputs of INSERT_SUBREG.
335 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
336 /// - BaseReg: vreg0:sub0
337 /// - InsertedReg: vreg1:sub1, sub3
339 /// \returns true if it is possible to build such an input sequence
340 /// with the pair \p MI, \p DefIdx. False otherwise.
342 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
344 /// \note The generic implementation does not provide any support for
345 /// MI.isInsertSubregLike(). In other words, one has to override
346 /// getInsertSubregLikeInputs for target specific instructions.
348 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
349 RegSubRegPair &BaseReg,
350 RegSubRegPairAndIdx &InsertedReg) const;
353 /// produceSameValue - Return true if two machine instructions would produce
354 /// identical values. By default, this is only true when the two instructions
355 /// are deemed identical except for defs. If this function is called when the
356 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
357 /// aggressive checks.
358 virtual bool produceSameValue(const MachineInstr *MI0,
359 const MachineInstr *MI1,
360 const MachineRegisterInfo *MRI = nullptr) const;
362 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
363 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
364 /// implemented for a target). Upon success, this returns false and returns
365 /// with the following information in various cases:
367 /// 1. If this block ends with no branches (it just falls through to its succ)
368 /// just return false, leaving TBB/FBB null.
369 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
370 /// the destination block.
371 /// 3. If this block ends with a conditional branch and it falls through to a
372 /// successor block, it sets TBB to be the branch destination block and a
373 /// list of operands that evaluate the condition. These operands can be
374 /// passed to other TargetInstrInfo methods to create new branches.
375 /// 4. If this block ends with a conditional branch followed by an
376 /// unconditional branch, it returns the 'true' destination in TBB, the
377 /// 'false' destination in FBB, and a list of operands that evaluate the
378 /// condition. These operands can be passed to other TargetInstrInfo
379 /// methods to create new branches.
381 /// Note that RemoveBranch and InsertBranch must be implemented to support
382 /// cases where this method returns success.
384 /// If AllowModify is true, then this routine is allowed to modify the basic
385 /// block (e.g. delete instructions after the unconditional branch).
387 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
388 MachineBasicBlock *&FBB,
389 SmallVectorImpl<MachineOperand> &Cond,
390 bool AllowModify = false) const {
394 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
395 /// This is only invoked in cases where AnalyzeBranch returns success. It
396 /// returns the number of instructions that were removed.
397 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
398 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
401 /// InsertBranch - Insert branch code into the end of the specified
402 /// MachineBasicBlock. The operands to this method are the same as those
403 /// returned by AnalyzeBranch. This is only invoked in cases where
404 /// AnalyzeBranch returns success. It returns the number of instructions
407 /// It is also invoked by tail merging to add unconditional branches in
408 /// cases where AnalyzeBranch doesn't apply because there was no original
409 /// branch to analyze. At least this much must be implemented, else tail
410 /// merging needs to be disabled.
411 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
412 MachineBasicBlock *FBB,
413 const SmallVectorImpl<MachineOperand> &Cond,
415 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
418 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
419 /// after it, replacing it with an unconditional branch to NewDest. This is
420 /// used by the tail merging pass.
421 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
422 MachineBasicBlock *NewDest) const;
424 /// getUnconditionalBranch - Get an instruction that performs an unconditional
425 /// branch to the given symbol.
427 getUnconditionalBranch(MCInst &MI,
428 const MCSymbolRefExpr *BranchTarget) const {
429 llvm_unreachable("Target didn't implement "
430 "TargetInstrInfo::getUnconditionalBranch!");
433 /// getTrap - Get a machine trap instruction
434 virtual void getTrap(MCInst &MI) const {
435 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!");
438 /// getJumpInstrTableEntryBound - Get a number of bytes that suffices to hold
439 /// either the instruction returned by getUnconditionalBranch or the
440 /// instruction returned by getTrap. This only makes sense because
441 /// getUnconditionalBranch returns a single, specific instruction. This
442 /// information is needed by the jumptable construction code, since it must
443 /// decide how many bytes to use for a jumptable entry so it can generate the
446 /// Note that if the jumptable instruction requires alignment, then that
447 /// alignment should be factored into this required bound so that the
448 /// resulting bound gives the right alignment for the instruction.
449 virtual unsigned getJumpInstrTableEntryBound() const {
450 // This method gets called by LLVMTargetMachine always, so it can't fail
451 // just because there happens to be no implementation for this target.
452 // Any code that tries to use a jumptable annotation without defining
453 // getUnconditionalBranch on the appropriate Target will fail anyway, and
454 // the value returned here won't matter in that case.
458 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
459 /// block at the specified instruction (i.e. instruction would be the start
460 /// of a new basic block).
461 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
462 MachineBasicBlock::iterator MBBI) const {
466 /// isProfitableToIfCvt - Return true if it's profitable to predicate
467 /// instructions with accumulated instruction latency of "NumCycles"
468 /// of the specified basic block, where the probability of the instructions
469 /// being executed is given by Probability, and Confidence is a measure
470 /// of our confidence that it will be properly predicted.
472 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
473 unsigned ExtraPredCycles,
474 const BranchProbability &Probability) const {
478 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
479 /// checks for the case where two basic blocks from true and false path
480 /// of a if-then-else (diamond) are predicated on mutally exclusive
481 /// predicates, where the probability of the true path being taken is given
482 /// by Probability, and Confidence is a measure of our confidence that it
483 /// will be properly predicted.
485 isProfitableToIfCvt(MachineBasicBlock &TMBB,
486 unsigned NumTCycles, unsigned ExtraTCycles,
487 MachineBasicBlock &FMBB,
488 unsigned NumFCycles, unsigned ExtraFCycles,
489 const BranchProbability &Probability) const {
493 /// isProfitableToDupForIfCvt - Return true if it's profitable for
494 /// if-converter to duplicate instructions of specified accumulated
495 /// instruction latencies in the specified MBB to enable if-conversion.
496 /// The probability of the instructions being executed is given by
497 /// Probability, and Confidence is a measure of our confidence that it
498 /// will be properly predicted.
500 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
501 const BranchProbability &Probability) const {
505 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate
506 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
507 /// exclusive predicates.
515 /// This may be profitable is conditional instructions are always executed.
516 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
517 MachineBasicBlock &FMBB) const {
521 /// canInsertSelect - Return true if it is possible to insert a select
522 /// instruction that chooses between TrueReg and FalseReg based on the
523 /// condition code in Cond.
525 /// When successful, also return the latency in cycles from TrueReg,
526 /// FalseReg, and Cond to the destination register. In most cases, a select
527 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
529 /// Some x86 implementations have 2-cycle cmov instructions.
531 /// @param MBB Block where select instruction would be inserted.
532 /// @param Cond Condition returned by AnalyzeBranch.
533 /// @param TrueReg Virtual register to select when Cond is true.
534 /// @param FalseReg Virtual register to select when Cond is false.
535 /// @param CondCycles Latency from Cond+Branch to select output.
536 /// @param TrueCycles Latency from TrueReg to select output.
537 /// @param FalseCycles Latency from FalseReg to select output.
538 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
539 const SmallVectorImpl<MachineOperand> &Cond,
540 unsigned TrueReg, unsigned FalseReg,
542 int &TrueCycles, int &FalseCycles) const {
546 /// insertSelect - Insert a select instruction into MBB before I that will
547 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
550 /// This function can only be called after canInsertSelect() returned true.
551 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
552 /// that the same flags or registers required by Cond are available at the
555 /// @param MBB Block where select instruction should be inserted.
556 /// @param I Insertion point.
557 /// @param DL Source location for debugging.
558 /// @param DstReg Virtual register to be defined by select instruction.
559 /// @param Cond Condition as computed by AnalyzeBranch.
560 /// @param TrueReg Virtual register to copy when Cond is true.
561 /// @param FalseReg Virtual register to copy when Cons is false.
562 virtual void insertSelect(MachineBasicBlock &MBB,
563 MachineBasicBlock::iterator I, DebugLoc DL,
565 const SmallVectorImpl<MachineOperand> &Cond,
566 unsigned TrueReg, unsigned FalseReg) const {
567 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
570 /// analyzeSelect - Analyze the given select instruction, returning true if
571 /// it cannot be understood. It is assumed that MI->isSelect() is true.
573 /// When successful, return the controlling condition and the operands that
574 /// determine the true and false result values.
576 /// Result = SELECT Cond, TrueOp, FalseOp
578 /// Some targets can optimize select instructions, for example by predicating
579 /// the instruction defining one of the operands. Such targets should set
582 /// @param MI Select instruction to analyze.
583 /// @param Cond Condition controlling the select.
584 /// @param TrueOp Operand number of the value selected when Cond is true.
585 /// @param FalseOp Operand number of the value selected when Cond is false.
586 /// @param Optimizable Returned as true if MI is optimizable.
587 /// @returns False on success.
588 virtual bool analyzeSelect(const MachineInstr *MI,
589 SmallVectorImpl<MachineOperand> &Cond,
590 unsigned &TrueOp, unsigned &FalseOp,
591 bool &Optimizable) const {
592 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
596 /// optimizeSelect - Given a select instruction that was understood by
597 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
598 /// merging it with one of its operands. Returns NULL on failure.
600 /// When successful, returns the new select instruction. The client is
601 /// responsible for deleting MI.
603 /// If both sides of the select can be optimized, PreferFalse is used to pick
606 /// @param MI Optimizable select instruction.
607 /// @param NewMIs Set that record all MIs in the basic block up to \p
608 /// MI. Has to be updated with any newly created MI or deleted ones.
609 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
610 /// @returns Optimized instruction or NULL.
611 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
612 SmallPtrSetImpl<MachineInstr *> &NewMIs,
613 bool PreferFalse = false) const {
614 // This function must be implemented if Optimizable is ever set.
615 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
618 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
620 /// This function should support copies within any legal register class as
621 /// well as any cross-class copies created during instruction selection.
623 /// The source and destination registers may overlap, which may require a
624 /// careful implementation when multiple copy instructions are required for
625 /// large registers. See for example the ARM target.
626 virtual void copyPhysReg(MachineBasicBlock &MBB,
627 MachineBasicBlock::iterator MI, DebugLoc DL,
628 unsigned DestReg, unsigned SrcReg,
629 bool KillSrc) const {
630 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
633 /// storeRegToStackSlot - Store the specified register of the given register
634 /// class to the specified stack frame index. The store instruction is to be
635 /// added to the given machine basic block before the specified machine
636 /// instruction. If isKill is true, the register operand is the last use and
637 /// must be marked kill.
638 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
639 MachineBasicBlock::iterator MI,
640 unsigned SrcReg, bool isKill, int FrameIndex,
641 const TargetRegisterClass *RC,
642 const TargetRegisterInfo *TRI) const {
643 llvm_unreachable("Target didn't implement "
644 "TargetInstrInfo::storeRegToStackSlot!");
647 /// loadRegFromStackSlot - Load the specified register of the given register
648 /// class from the specified stack frame index. The load instruction is to be
649 /// added to the given machine basic block before the specified machine
651 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
652 MachineBasicBlock::iterator MI,
653 unsigned DestReg, int FrameIndex,
654 const TargetRegisterClass *RC,
655 const TargetRegisterInfo *TRI) const {
656 llvm_unreachable("Target didn't implement "
657 "TargetInstrInfo::loadRegFromStackSlot!");
660 /// expandPostRAPseudo - This function is called for all pseudo instructions
661 /// that remain after register allocation. Many pseudo instructions are
662 /// created to help register allocation. This is the place to convert them
663 /// into real instructions. The target can edit MI in place, or it can insert
664 /// new instructions and erase MI. The function should return true if
665 /// anything was changed.
666 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
670 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
671 /// slot into the specified machine instruction for the specified operand(s).
672 /// If this is possible, a new instruction is returned with the specified
673 /// operand folded, otherwise NULL is returned.
674 /// The new instruction is inserted before MI, and the client is responsible
675 /// for removing the old instruction.
676 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
677 const SmallVectorImpl<unsigned> &Ops,
678 int FrameIndex) const;
680 /// foldMemoryOperand - Same as the previous version except it allows folding
681 /// of any load and store from / to any address, not just from a specific
683 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
684 const SmallVectorImpl<unsigned> &Ops,
685 MachineInstr* LoadMI) const;
687 /// hasPattern - return true when there is potentially a faster code sequence
688 /// for an instruction chain ending in \p Root. All potential pattern are
689 /// returned in the \p Pattern vector. Pattern should be sorted in priority
690 /// order since the pattern evaluator stops checking as soon as it finds a
692 /// \param Root - Instruction that could be combined with one of its operands
693 /// \param Pattern - Vector of possible combination pattern
695 virtual bool hasPattern(
697 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
701 /// genAlternativeCodeSequence - when hasPattern() finds a pattern this
702 /// function generates the instructions that could replace the original code
703 /// sequence. The client has to decide whether the actual replacementment is
704 /// beneficial or not.
705 /// \param Root - Instruction that could be combined with one of its operands
706 /// \param P - Combination pattern for Root
707 /// \param InsInstrs - Vector of new instructions that implement P
708 /// \param DelInstrs - Old instructions, including Root, that could be replaced
710 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
711 /// InsInstr that defines it
712 virtual void genAlternativeCodeSequence(
713 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
714 SmallVectorImpl<MachineInstr *> &InsInstrs,
715 SmallVectorImpl<MachineInstr *> &DelInstrs,
716 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
720 /// useMachineCombiner - return true when a target supports MachineCombiner
721 virtual bool useMachineCombiner() const { return false; }
724 /// foldMemoryOperandImpl - Target-dependent implementation for
725 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
726 /// take care of adding a MachineMemOperand to the newly created instruction.
727 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
729 const SmallVectorImpl<unsigned> &Ops,
730 int FrameIndex) const {
734 /// foldMemoryOperandImpl - Target-dependent implementation for
735 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
736 /// take care of adding a MachineMemOperand to the newly created instruction.
737 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
739 const SmallVectorImpl<unsigned> &Ops,
740 MachineInstr* LoadMI) const {
744 /// \brief Target-dependent implementation of getRegSequenceInputs.
746 /// \returns true if it is possible to build the equivalent
747 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
749 /// \pre MI.isRegSequenceLike().
751 /// \see TargetInstrInfo::getRegSequenceInputs.
752 virtual bool getRegSequenceLikeInputs(
753 const MachineInstr &MI, unsigned DefIdx,
754 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
758 /// \brief Target-dependent implementation of getExtractSubregInputs.
760 /// \returns true if it is possible to build the equivalent
761 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
763 /// \pre MI.isExtractSubregLike().
765 /// \see TargetInstrInfo::getExtractSubregInputs.
766 virtual bool getExtractSubregLikeInputs(
767 const MachineInstr &MI, unsigned DefIdx,
768 RegSubRegPairAndIdx &InputReg) const {
772 /// \brief Target-dependent implementation of getInsertSubregInputs.
774 /// \returns true if it is possible to build the equivalent
775 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
777 /// \pre MI.isInsertSubregLike().
779 /// \see TargetInstrInfo::getInsertSubregInputs.
781 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
782 RegSubRegPair &BaseReg,
783 RegSubRegPairAndIdx &InsertedReg) const {
788 /// canFoldMemoryOperand - Returns true for the specified load / store if
789 /// folding is possible.
791 bool canFoldMemoryOperand(const MachineInstr *MI,
792 const SmallVectorImpl<unsigned> &Ops) const;
794 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
795 /// a store or a load and a store into two or more instruction. If this is
796 /// possible, returns true as well as the new instructions by reference.
797 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
798 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
799 SmallVectorImpl<MachineInstr*> &NewMIs) const{
803 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
804 SmallVectorImpl<SDNode*> &NewNodes) const {
808 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
809 /// instruction after load / store are unfolded from an instruction of the
810 /// specified opcode. It returns zero if the specified unfolding is not
811 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
812 /// index of the operand which will hold the register holding the loaded
814 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
815 bool UnfoldLoad, bool UnfoldStore,
816 unsigned *LoadRegIndex = nullptr) const {
820 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
821 /// to determine if two loads are loading from the same base address. It
822 /// should only return true if the base pointers are the same and the
823 /// only differences between the two addresses are the offset. It also returns
824 /// the offsets by reference.
825 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
826 int64_t &Offset1, int64_t &Offset2) const {
830 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
831 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
832 /// be scheduled togther. On some targets if two loads are loading from
833 /// addresses in the same cache line, it's better if they are scheduled
834 /// together. This function takes two integers that represent the load offsets
835 /// from the common base address. It returns true if it decides it's desirable
836 /// to schedule the two loads together. "NumLoads" is the number of loads that
837 /// have already been scheduled after Load1.
838 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
839 int64_t Offset1, int64_t Offset2,
840 unsigned NumLoads) const {
844 /// \brief Get the base register and byte offset of a load/store instr.
845 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
846 unsigned &BaseReg, unsigned &Offset,
847 const TargetRegisterInfo *TRI) const {
851 virtual bool enableClusterLoads() const { return false; }
853 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
854 MachineInstr *SecondLdSt,
855 unsigned NumLoads) const {
859 /// \brief Can this target fuse the given instructions if they are scheduled
861 virtual bool shouldScheduleAdjacent(MachineInstr* First,
862 MachineInstr *Second) const {
866 /// ReverseBranchCondition - Reverses the branch condition of the specified
867 /// condition list, returning false on success and true if it cannot be
870 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
874 /// insertNoop - Insert a noop into the instruction stream at the specified
876 virtual void insertNoop(MachineBasicBlock &MBB,
877 MachineBasicBlock::iterator MI) const;
879 /// insertNoop - Insert a type of noop into the instruction stream at the
880 /// specified point to introduce fine-grained diversity. A target may randomly
881 /// choose from a pool of valid noops using the provided RNG.
882 virtual void insertNoop(MachineBasicBlock &MBB,
883 MachineBasicBlock::iterator MI,
884 RandomNumberGenerator&) const {
888 /// Return the noop instruction to use for a noop.
889 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
892 /// isPredicated - Returns true if the instruction is already predicated.
894 virtual bool isPredicated(const MachineInstr *MI) const {
898 /// isUnpredicatedTerminator - Returns true if the instruction is a
899 /// terminator instruction that has not been predicated.
900 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
902 /// PredicateInstruction - Convert the instruction into a predicated
903 /// instruction. It returns true if the operation was successful.
905 bool PredicateInstruction(MachineInstr *MI,
906 const SmallVectorImpl<MachineOperand> &Pred) const;
908 /// SubsumesPredicate - Returns true if the first specified predicate
909 /// subsumes the second, e.g. GE subsumes GT.
911 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
912 const SmallVectorImpl<MachineOperand> &Pred2) const {
916 /// DefinesPredicate - If the specified instruction defines any predicate
917 /// or condition code register(s) used for predication, returns true as well
918 /// as the definition predicate(s) by reference.
919 virtual bool DefinesPredicate(MachineInstr *MI,
920 std::vector<MachineOperand> &Pred) const {
924 /// isPredicable - Return true if the specified instruction can be predicated.
925 /// By default, this returns true for every instruction with a
926 /// PredicateOperand.
927 virtual bool isPredicable(MachineInstr *MI) const {
928 return MI->getDesc().isPredicable();
931 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
932 /// instruction that defines the specified register class.
933 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
937 /// isSchedulingBoundary - Test if the given instruction should be
938 /// considered a scheduling boundary. This primarily includes labels and
940 virtual bool isSchedulingBoundary(const MachineInstr *MI,
941 const MachineBasicBlock *MBB,
942 const MachineFunction &MF) const;
944 /// Measure the specified inline asm to determine an approximation of its
946 virtual unsigned getInlineAsmLength(const char *Str,
947 const MCAsmInfo &MAI) const;
949 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
950 /// use for this target when scheduling the machine instructions before
951 /// register allocation.
952 virtual ScheduleHazardRecognizer*
953 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
954 const ScheduleDAG *DAG) const;
956 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer
957 /// to use for this target when scheduling the machine instructions before
958 /// register allocation.
959 virtual ScheduleHazardRecognizer*
960 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
961 const ScheduleDAG *DAG) const;
963 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
964 /// recognizer to use for this target when scheduling the machine instructions
965 /// after register allocation.
966 virtual ScheduleHazardRecognizer*
967 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
968 const ScheduleDAG *DAG) const;
970 /// Provide a global flag for disabling the PreRA hazard recognizer that
971 /// targets may choose to honor.
972 bool usePreRAHazardRecognizer() const;
974 /// analyzeCompare - For a comparison instruction, return the source registers
975 /// in SrcReg and SrcReg2 if having two register operands, and the value it
976 /// compares against in CmpValue. Return true if the comparison instruction
978 virtual bool analyzeCompare(const MachineInstr *MI,
979 unsigned &SrcReg, unsigned &SrcReg2,
980 int &Mask, int &Value) const {
984 /// optimizeCompareInstr - See if the comparison instruction can be converted
985 /// into something more efficient. E.g., on ARM most instructions can set the
986 /// flags register, obviating the need for a separate CMP.
987 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
988 unsigned SrcReg, unsigned SrcReg2,
990 const MachineRegisterInfo *MRI) const {
993 virtual bool optimizeCondBranch(MachineInstr *MI) const { return false; }
995 /// optimizeLoadInstr - Try to remove the load by folding it to a register
996 /// operand at the use. We fold the load instructions if and only if the
997 /// def and use are in the same BB. We only look at one load and see
998 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
999 /// defined by the load we are trying to fold. DefMI returns the machine
1000 /// instruction that defines FoldAsLoadDefReg, and the function returns
1001 /// the machine instruction generated due to folding.
1002 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
1003 const MachineRegisterInfo *MRI,
1004 unsigned &FoldAsLoadDefReg,
1005 MachineInstr *&DefMI) const {
1009 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
1010 /// instruction, try to fold the immediate into the use instruction.
1011 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1012 /// then the caller may assume that DefMI has been erased from its parent
1013 /// block. The caller may assume that it will not be erased by this
1014 /// function otherwise.
1015 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1016 unsigned Reg, MachineRegisterInfo *MRI) const {
1020 /// getNumMicroOps - Return the number of u-operations the given machine
1021 /// instruction will be decoded to on the target cpu. The itinerary's
1022 /// IssueWidth is the number of microops that can be dispatched each
1023 /// cycle. An instruction with zero microops takes no dispatch resources.
1024 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1025 const MachineInstr *MI) const;
1027 /// isZeroCost - Return true for pseudo instructions that don't consume any
1028 /// machine resources in their current form. These are common cases that the
1029 /// scheduler should consider free, rather than conservatively handling them
1030 /// as instructions with no itinerary.
1031 bool isZeroCost(unsigned Opcode) const {
1032 return Opcode <= TargetOpcode::COPY;
1035 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1036 SDNode *DefNode, unsigned DefIdx,
1037 SDNode *UseNode, unsigned UseIdx) const;
1039 /// getOperandLatency - Compute and return the use operand latency of a given
1040 /// pair of def and use.
1041 /// In most cases, the static scheduling itinerary was enough to determine the
1042 /// operand latency. But it may not be possible for instructions with variable
1043 /// number of defs / uses.
1045 /// This is a raw interface to the itinerary that may be directly overriden by
1046 /// a target. Use computeOperandLatency to get the best estimate of latency.
1047 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1048 const MachineInstr *DefMI, unsigned DefIdx,
1049 const MachineInstr *UseMI,
1050 unsigned UseIdx) const;
1052 /// computeOperandLatency - Compute and return the latency of the given data
1053 /// dependent def and use when the operand indices are already known.
1054 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
1055 const MachineInstr *DefMI, unsigned DefIdx,
1056 const MachineInstr *UseMI, unsigned UseIdx)
1059 /// getInstrLatency - Compute the instruction latency of a given instruction.
1060 /// If the instruction has higher cost when predicated, it's returned via
1062 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1063 const MachineInstr *MI,
1064 unsigned *PredCost = nullptr) const;
1066 virtual unsigned getPredicationCost(const MachineInstr *MI) const;
1068 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1069 SDNode *Node) const;
1071 /// Return the default expected latency for a def based on it's opcode.
1072 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1073 const MachineInstr *DefMI) const;
1075 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1076 const MachineInstr *DefMI) const;
1078 /// isHighLatencyDef - Return true if this opcode has high latency to its
1080 virtual bool isHighLatencyDef(int opc) const { return false; }
1082 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
1083 /// and an use in the current loop, return true if the target considered
1084 /// it 'high'. This is used by optimization passes such as machine LICM to
1085 /// determine whether it makes sense to hoist an instruction out even in
1086 /// high register pressure situation.
1088 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
1089 const MachineRegisterInfo *MRI,
1090 const MachineInstr *DefMI, unsigned DefIdx,
1091 const MachineInstr *UseMI, unsigned UseIdx) const {
1095 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
1096 /// if the target considered it 'low'.
1098 bool hasLowDefLatency(const InstrItineraryData *ItinData,
1099 const MachineInstr *DefMI, unsigned DefIdx) const;
1101 /// verifyInstruction - Perform target specific instruction verification.
1103 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
1107 /// getExecutionDomain - Return the current execution domain and bit mask of
1108 /// possible domains for instruction.
1110 /// Some micro-architectures have multiple execution domains, and multiple
1111 /// opcodes that perform the same operation in different domains. For
1112 /// example, the x86 architecture provides the por, orps, and orpd
1113 /// instructions that all do the same thing. There is a latency penalty if a
1114 /// register is written in one domain and read in another.
1116 /// This function returns a pair (domain, mask) containing the execution
1117 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1118 /// function can be used to change the opcode to one of the domains in the
1119 /// bit mask. Instructions whose execution domain can't be changed should
1120 /// return a 0 mask.
1122 /// The execution domain numbers don't have any special meaning except domain
1123 /// 0 is used for instructions that are not associated with any interesting
1124 /// execution domain.
1126 virtual std::pair<uint16_t, uint16_t>
1127 getExecutionDomain(const MachineInstr *MI) const {
1128 return std::make_pair(0, 0);
1131 /// setExecutionDomain - Change the opcode of MI to execute in Domain.
1133 /// The bit (1 << Domain) must be set in the mask returned from
1134 /// getExecutionDomain(MI).
1136 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
1139 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance
1140 /// before an instruction with an unwanted partial register update.
1142 /// Some instructions only write part of a register, and implicitly need to
1143 /// read the other parts of the register. This may cause unwanted stalls
1144 /// preventing otherwise unrelated instructions from executing in parallel in
1145 /// an out-of-order CPU.
1147 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1148 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1149 /// the instruction needs to wait for the old value of the register to become
1152 /// addps %xmm1, %xmm0
1153 /// movaps %xmm0, (%rax)
1154 /// cvtsi2ss %rbx, %xmm0
1156 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1157 /// instruction before it can issue, even though the high bits of %xmm0
1158 /// probably aren't needed.
1160 /// This hook returns the preferred clearance before MI, measured in
1161 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1162 /// instructions before MI. It should only return a positive value for
1163 /// unwanted dependencies. If the old bits of the defined register have
1164 /// useful values, or if MI is determined to otherwise read the dependency,
1165 /// the hook should return 0.
1167 /// The unwanted dependency may be handled by:
1169 /// 1. Allocating the same register for an MI def and use. That makes the
1170 /// unwanted dependency identical to a required dependency.
1172 /// 2. Allocating a register for the def that has no defs in the previous N
1175 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1176 /// allows the target to insert a dependency breaking instruction.
1179 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
1180 const TargetRegisterInfo *TRI) const {
1181 // The default implementation returns 0 for no partial register dependency.
1185 /// \brief Return the minimum clearance before an instruction that reads an
1186 /// unused register.
1188 /// For example, AVX instructions may copy part of an register operand into
1189 /// the unused high bits of the destination register.
1191 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1193 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1194 /// false dependence on any previous write to %xmm0.
1196 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1197 /// does not take an operand index. Instead sets \p OpNum to the index of the
1198 /// unused register.
1199 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
1200 const TargetRegisterInfo *TRI) const {
1201 // The default implementation returns 0 for no undef register dependency.
1205 /// breakPartialRegDependency - Insert a dependency-breaking instruction
1206 /// before MI to eliminate an unwanted dependency on OpNum.
1208 /// If it wasn't possible to avoid a def in the last N instructions before MI
1209 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1210 /// unwanted dependency.
1212 /// On x86, an xorps instruction can be used as a dependency breaker:
1214 /// addps %xmm1, %xmm0
1215 /// movaps %xmm0, (%rax)
1216 /// xorps %xmm0, %xmm0
1217 /// cvtsi2ss %rbx, %xmm0
1219 /// An <imp-kill> operand should be added to MI if an instruction was
1220 /// inserted. This ties the instructions together in the post-ra scheduler.
1223 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
1224 const TargetRegisterInfo *TRI) const {}
1226 /// Create machine specific model for scheduling.
1227 virtual DFAPacketizer *
1228 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1232 // areMemAccessesTriviallyDisjoint - Sometimes, it is possible for the target
1233 // to tell, even without aliasing information, that two MIs access different
1234 // memory addresses. This function returns true if two MIs access different
1235 // memory addresses, and false otherwise.
1237 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
1238 AliasAnalysis *AA = nullptr) const {
1239 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1240 "MIa must load from or modify a memory location");
1241 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1242 "MIb must load from or modify a memory location");
1247 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
1250 } // End llvm namespace