1 //===-- llvm/Target/MachineInstrInstrInfo.h - Instruction Infor ---*-C++-*-===//
3 // This file describes the target machine instructions to the code generator.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "Support/DataTypes.h"
13 class MachineInstrDescriptor;
20 class MachineCodeForInstruction;
22 //---------------------------------------------------------------------------
23 // Data types used to define information about a single machine instruction
24 //---------------------------------------------------------------------------
26 typedef int MachineOpCode;
27 typedef unsigned InstrSchedClass;
29 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
32 //---------------------------------------------------------------------------
33 // struct MachineInstrDescriptor:
34 // Predefined information about each machine instruction.
35 // Designed to initialized statically.
37 // class MachineInstructionInfo
38 // Interface to description of machine instructions
40 //---------------------------------------------------------------------------
42 const unsigned M_NOP_FLAG = 1 << 0;
43 const unsigned M_BRANCH_FLAG = 1 << 1;
44 const unsigned M_CALL_FLAG = 1 << 2;
45 const unsigned M_RET_FLAG = 1 << 3;
46 const unsigned M_ARITH_FLAG = 1 << 4;
47 const unsigned M_CC_FLAG = 1 << 6;
48 const unsigned M_LOGICAL_FLAG = 1 << 6;
49 const unsigned M_INT_FLAG = 1 << 7;
50 const unsigned M_FLOAT_FLAG = 1 << 8;
51 const unsigned M_CONDL_FLAG = 1 << 9;
52 const unsigned M_LOAD_FLAG = 1 << 10;
53 const unsigned M_PREFETCH_FLAG = 1 << 11;
54 const unsigned M_STORE_FLAG = 1 << 12;
55 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
56 const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
57 // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
58 const unsigned M_2_ADDR_FLAG = 1 << 15;
60 struct MachineInstrDescriptor {
61 const char * Name; // Assembly language mnemonic for the opcode.
62 int numOperands; // Number of args; -1 if variable #args
63 int resultPos; // Position of the result; -1 if no result
64 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
65 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
66 // smallest -ve value is -(maxImmedConst+1).
67 unsigned numDelaySlots; // Number of delay slots after instruction
68 unsigned latency; // Latency in machine cycles
69 InstrSchedClass schedClass; // enum identifying instr sched class
70 unsigned Flags; // flags identifying machine instr class
71 unsigned TSFlags; // Target Specific Flag values
72 const unsigned *ImplicitUses; // Registers implicitly read by this instr
73 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
77 class MachineInstrInfo {
78 const MachineInstrDescriptor* desc; // raw array to allow static init'n
79 unsigned descSize; // number of entries in the desc array
80 unsigned numRealOpCodes; // number of non-dummy op codes
82 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT
83 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT
85 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
86 unsigned numRealOpCodes);
87 virtual ~MachineInstrInfo();
89 // Invariant: All instruction sets use opcode #0 as the PHI instruction and
90 // opcode #1 as the noop instruction.
95 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
96 unsigned getNumTotalOpCodes() const { return descSize; }
98 /// get - Return the machine instruction descriptor that corresponds to the
99 /// specified instruction opcode.
101 const MachineInstrDescriptor& get(MachineOpCode opCode) const {
102 assert(opCode >= 0 && opCode < (int)descSize);
106 /// print - Print out the specified machine instruction in the appropriate
107 /// target specific assembly language. If this method is not overridden, the
108 /// default implementation uses the crummy machine independant printer.
110 virtual void print(const MachineInstr *MI, std::ostream &O,
111 const TargetMachine &TM) const;
113 const char *getName(MachineOpCode opCode) const {
114 return get(opCode).Name;
117 int getNumOperands(MachineOpCode opCode) const {
118 return get(opCode).numOperands;
121 int getResultPos(MachineOpCode opCode) const {
122 return get(opCode).resultPos;
125 unsigned getNumDelaySlots(MachineOpCode opCode) const {
126 return get(opCode).numDelaySlots;
129 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
130 return get(opCode).schedClass;
134 // Query instruction class flags according to the machine-independent
135 // flags listed above.
137 bool isNop(MachineOpCode opCode) const {
138 return get(opCode).Flags & M_NOP_FLAG;
140 bool isBranch(MachineOpCode opCode) const {
141 return get(opCode).Flags & M_BRANCH_FLAG;
143 bool isCall(MachineOpCode opCode) const {
144 return get(opCode).Flags & M_CALL_FLAG;
146 bool isReturn(MachineOpCode opCode) const {
147 return get(opCode).Flags & M_RET_FLAG;
149 bool isControlFlow(MachineOpCode opCode) const {
150 return get(opCode).Flags & M_BRANCH_FLAG
151 || get(opCode).Flags & M_CALL_FLAG
152 || get(opCode).Flags & M_RET_FLAG;
154 bool isArith(MachineOpCode opCode) const {
155 return get(opCode).Flags & M_ARITH_FLAG;
157 bool isCCInstr(MachineOpCode opCode) const {
158 return get(opCode).Flags & M_CC_FLAG;
160 bool isLogical(MachineOpCode opCode) const {
161 return get(opCode).Flags & M_LOGICAL_FLAG;
163 bool isIntInstr(MachineOpCode opCode) const {
164 return get(opCode).Flags & M_INT_FLAG;
166 bool isFloatInstr(MachineOpCode opCode) const {
167 return get(opCode).Flags & M_FLOAT_FLAG;
169 bool isConditional(MachineOpCode opCode) const {
170 return get(opCode).Flags & M_CONDL_FLAG;
172 bool isLoad(MachineOpCode opCode) const {
173 return get(opCode).Flags & M_LOAD_FLAG;
175 bool isPrefetch(MachineOpCode opCode) const {
176 return get(opCode).Flags & M_PREFETCH_FLAG;
178 bool isLoadOrPrefetch(MachineOpCode opCode) const {
179 return get(opCode).Flags & M_LOAD_FLAG
180 || get(opCode).Flags & M_PREFETCH_FLAG;
182 bool isStore(MachineOpCode opCode) const {
183 return get(opCode).Flags & M_STORE_FLAG;
185 bool isMemoryAccess(MachineOpCode opCode) const {
186 return get(opCode).Flags & M_LOAD_FLAG
187 || get(opCode).Flags & M_PREFETCH_FLAG
188 || get(opCode).Flags & M_STORE_FLAG;
190 bool isDummyPhiInstr(const MachineOpCode opCode) const {
191 return get(opCode).Flags & M_DUMMY_PHI_FLAG;
193 bool isPseudoInstr(const MachineOpCode opCode) const {
194 return get(opCode).Flags & M_PSEUDO_FLAG;
196 bool isTwoAddrInstr(const MachineOpCode opCode) const {
197 return get(opCode).Flags & M_2_ADDR_FLAG;
200 // Check if an instruction can be issued before its operands are ready,
201 // or if a subsequent instruction that uses its result can be issued
202 // before the results are ready.
203 // Default to true since most instructions on many architectures allow this.
205 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
209 virtual bool hasResultInterlock(MachineOpCode opCode) const {
214 // Latencies for individual instructions and instruction pairs
216 virtual int minLatency(MachineOpCode opCode) const {
217 return get(opCode).latency;
220 virtual int maxLatency(MachineOpCode opCode) const {
221 return get(opCode).latency;
225 // Which operand holds an immediate constant? Returns -1 if none
227 virtual int getImmedConstantPos(MachineOpCode opCode) const {
228 return -1; // immediate position is machine specific, so say -1 == "none"
231 // Check if the specified constant fits in the immediate field
232 // of this machine instruction
234 virtual bool constantFitsInImmedField(MachineOpCode opCode,
235 int64_t intValue) const;
237 // Return the largest +ve constant that can be held in the IMMMED field
238 // of this machine instruction.
239 // isSignExtended is set to true if the value is sign-extended before use
240 // (this is true for all immediate fields in SPARC instructions).
241 // Return 0 if the instruction has no IMMED field.
243 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
244 bool &isSignExtended) const {
245 isSignExtended = get(opCode).immedIsSignExtended;
246 return get(opCode).maxImmedConst;
249 //-------------------------------------------------------------------------
250 // Queries about representation of LLVM quantities (e.g., constants)
251 //-------------------------------------------------------------------------
253 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
254 /// from memory into a register, i.e., cannot be set bitwise in register and
255 /// cannot use immediate fields of instructions. Note that this only makes
256 /// sense for primitive types.
258 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
260 // Test if this constant may not fit in the immediate field of the
261 // machine instructions (probably) generated for this instruction.
263 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
264 const Instruction* I) const {
265 return true; // safe but very conservative
268 //-------------------------------------------------------------------------
269 // Code generation support for creating individual machine instructions
270 //-------------------------------------------------------------------------
272 // Get certain common op codes for the current target. this and all the
273 // Create* methods below should be moved to a machine code generation class
275 virtual MachineOpCode getNOPOpCode() const = 0;
277 // Create an instruction sequence to put the constant `val' into
278 // the virtual register `dest'. `val' may be a Constant or a
279 // GlobalValue, viz., the constant address of a global variable or function.
280 // The generated instructions are returned in `mvec'.
281 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
282 // Symbolic constants or constants that must be accessed from memory
283 // are added to the constant pool via MachineFunction::get(F).
285 virtual void CreateCodeToLoadConst(const TargetMachine& target,
289 std::vector<MachineInstr*>& mvec,
290 MachineCodeForInstruction& mcfi) const=0;
292 // Create an instruction sequence to copy an integer value `val'
293 // to a floating point value `dest' by copying to memory and back.
294 // val must be an integral type. dest must be a Float or Double.
295 // The generated instructions are returned in `mvec'.
296 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
297 // Any stack space required is allocated via mcff.
299 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
303 std::vector<MachineInstr*>& mvec,
304 MachineCodeForInstruction& mcfi)const=0;
306 // Similarly, create an instruction sequence to copy an FP value
307 // `val' to an integer value `dest' by copying to memory and back.
308 // The generated instructions are returned in `mvec'.
309 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
310 // Any stack space required is allocated via mcff.
312 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
316 std::vector<MachineInstr*>& mvec,
317 MachineCodeForInstruction& mcfi)const=0;
319 // Create instruction(s) to copy src to dest, for arbitrary types
320 // The generated instructions are returned in `mvec'.
321 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
322 // Any stack space required is allocated via mcff.
324 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
328 std::vector<MachineInstr*>& mvec,
329 MachineCodeForInstruction& mcfi)const=0;
331 // Create instruction sequence to produce a sign-extended register value
332 // from an arbitrary sized value (sized in bits, not bytes).
333 // The generated instructions are appended to `mvec'.
334 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
335 // Any stack space required is allocated via mcff.
337 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
342 std::vector<MachineInstr*>& mvec,
343 MachineCodeForInstruction& mcfi) const=0;
345 // Create instruction sequence to produce a zero-extended register value
346 // from an arbitrary sized value (sized in bits, not bytes).
347 // The generated instructions are appended to `mvec'.
348 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
349 // Any stack space required is allocated via mcff.
351 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
355 unsigned srcSizeInBits,
356 std::vector<MachineInstr*>& mvec,
357 MachineCodeForInstruction& mcfi) const=0;