1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
33 template<class T> class SmallVectorImpl;
35 //===----------------------------------------------------------------------===//
36 // struct TargetInstrDescriptor:
37 // Predefined information about each machine instruction.
38 // Designed to initialized statically.
41 const unsigned M_BRANCH_FLAG = 1 << 0;
42 const unsigned M_CALL_FLAG = 1 << 1;
43 const unsigned M_RET_FLAG = 1 << 2;
44 const unsigned M_BARRIER_FLAG = 1 << 3;
45 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
47 /// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
48 /// from memory. This should only be set on instructions that load a value from
49 /// memory and return it in their only virtual register definition.
50 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
52 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
53 /// modify memory. Instructions with this flag set are not necessarily simple
54 /// store instructions, they may store a modified value based on their operands,
55 /// or may not actually modify anything, for example.
56 const unsigned M_MAY_STORE_FLAG = 1 << 6;
58 const unsigned M_INDIRECT_FLAG = 1 << 7;
59 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
61 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
62 // changed into a 3-address instruction if the first two operands cannot be
63 // assigned to the same register. The target must implement the
64 // TargetInstrInfo::convertToThreeAddress method for this instruction.
65 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
67 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
68 // Z), which produces the same result if Y and Z are exchanged.
69 const unsigned M_COMMUTABLE = 1 << 10;
71 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
72 // block? Typically this is things like return and branch instructions.
73 // Various passes use this to insert code into the bottom of a basic block, but
74 // before control flow occurs.
75 const unsigned M_TERMINATOR_FLAG = 1 << 11;
77 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
78 // insertion support when the DAG scheduler is inserting it into a machine basic
80 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
82 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
83 // operands in addition to the minimum number operands specified.
84 const unsigned M_VARIABLE_OPS = 1 << 13;
86 // M_PREDICABLE - Set if this instruction has a predicate operand that
87 // controls execution. It may be set to 'always'.
88 const unsigned M_PREDICABLE = 1 << 14;
90 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
91 // at any time, e.g. constant generation, load from constant pool.
92 const unsigned M_REMATERIALIZIBLE = 1 << 15;
94 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
95 // (e.g. instructions with unique labels attached).
96 const unsigned M_NOT_DUPLICABLE = 1 << 16;
98 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
99 // ARM instructions which can set condition code if 's' bit is set.
100 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
102 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
103 // are not captured by any operands of the instruction or other flags, and when
104 // *all* instances of the instruction of that opcode have no side effects.
106 // Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
107 // both! If neither flag is set, then the instruction *always* has side effects.
108 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
110 // M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
111 // side effects. The virtual method "isReallySideEffectFree" is called to
112 // determine this. Load instructions are an example of where this is useful. In
113 // general, loads always have side effects. However, loads from constant pools
114 // don't. We let the specific back end make this determination.
116 // Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
117 // both! If neither flag is set, then the instruction *always* has side effects.
118 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
121 //===----------------------------------------------------------------------===//
122 // Machine operand flags
123 //===----------------------------------------------------------------------===//
126 // Operand constraints: only "tied_to" for now.
127 enum OperandConstraint {
128 TIED_TO = 0 // Must be allocated the same register as.
131 /// OperandFlags - These are flags set on operands, but should be considered
132 /// private, all access should go through the TargetOperandInfo accessors.
133 /// See the accessors for a description of what these are.
135 LookupPtrRegClass = 1 << 0,
141 /// TargetOperandInfo - This holds information about one operand of a machine
142 /// instruction, indicating the register class for register operands, etc.
144 class TargetOperandInfo {
146 /// RegClass - This specifies the register class enumeration of the operand
147 /// if the operand is a register. If not, this contains 0.
148 unsigned short RegClass;
149 unsigned short Flags;
150 /// Lower 16 bits are used to specify which constraints are set. The higher 16
151 /// bits are used to specify the value of constraints (4 bits each).
152 unsigned int Constraints;
153 /// Currently no other information.
155 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
156 /// requires a callback to look up its register class.
157 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
159 /// isPredicate - Set if this is one of the operands that made up of
160 /// the predicate operand that controls an M_PREDICATED instruction.
161 bool isPredicate() const { return Flags & TOI::Predicate; }
163 /// isOptionalDef - Set if this operand is a optional def.
165 bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
169 class TargetInstrDescriptor {
171 unsigned short Opcode; // The opcode.
172 unsigned short numOperands; // Num of args (may be more if variable_ops).
173 unsigned short numDefs; // Num of args that are definitions.
174 const char * Name; // Assembly language mnemonic for the opcode.
175 unsigned SchedClass; // enum identifying instr sched class
176 unsigned Flags; // flags identifying machine instr class
177 unsigned TSFlags; // Target Specific Flag values
178 const unsigned *ImplicitUses; // Registers implicitly read by this instr
179 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
180 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
182 /// getOperandConstraint - Returns the value of the specific constraint if
183 /// it is set. Returns -1 if it is not set.
184 int getOperandConstraint(unsigned OpNum,
185 TOI::OperandConstraint Constraint) const {
186 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
187 "Invalid operand # of TargetInstrInfo");
188 if (OpNum < numOperands &&
189 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
190 unsigned Pos = 16 + Constraint * 4;
191 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
196 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
197 /// dest operand. Returns -1 if there isn't one.
198 int findTiedToSrcOperand(unsigned OpNum) const;
200 bool isCall() const {
201 return Flags & M_CALL_FLAG;
204 bool isBranch() const {
205 return Flags & M_BRANCH_FLAG;
208 bool isTerminator() const {
209 return Flags & M_TERMINATOR_FLAG;
212 bool isIndirectBranch() const {
213 return Flags & M_INDIRECT_FLAG;
216 bool isPredicable() const {
217 return Flags & M_PREDICABLE;
220 bool isNotDuplicable() const {
221 return Flags & M_NOT_DUPLICABLE;
226 /// isSimpleLoad - Return true for instructions that are simple loads from
227 /// memory. This should only be set on instructions that load a value from
228 /// memory and return it in their only virtual register definition.
229 /// Instructions that return a value loaded from memory and then modified in
230 /// some way should not return true for this.
231 bool isSimpleLoad() const {
232 return Flags & M_SIMPLE_LOAD_FLAG;
235 /// mayStore - Return true if this instruction could possibly modify memory.
236 /// Instructions with this flag set are not necessarily simple store
237 /// instructions, they may store a modified value based on their operands, or
238 /// may not actually modify anything, for example.
239 bool mayStore() const {
240 return Flags & M_MAY_STORE_FLAG;
243 /// isBarrier - Returns true if the specified instruction stops control flow
244 /// from executing the instruction immediately following it. Examples include
245 /// unconditional branches and return instructions.
246 bool isBarrier() const {
247 return Flags & M_BARRIER_FLAG;
250 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
251 /// which must be filled by the code generator.
252 bool hasDelaySlot() const {
253 return Flags & M_DELAY_SLOT_FLAG;
256 unsigned getSchedClass() const {
262 //---------------------------------------------------------------------------
264 /// TargetInstrInfo - Interface to description of machine instructions
266 class TargetInstrInfo {
267 const TargetInstrDescriptor* desc; // raw array to allow static init'n
268 unsigned NumOpcodes; // number of entries in the desc array
269 unsigned numRealOpCodes; // number of non-dummy op codes
271 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
272 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
274 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
275 virtual ~TargetInstrInfo();
277 // Invariant opcodes: All instruction sets have these as their low opcodes.
286 unsigned getNumOpcodes() const { return NumOpcodes; }
288 /// get - Return the machine instruction descriptor that corresponds to the
289 /// specified instruction opcode.
291 const TargetInstrDescriptor& get(unsigned Opcode) const {
292 assert(Opcode < NumOpcodes);
296 const char *getName(unsigned Opcode) const {
297 return get(Opcode).Name;
300 int getNumOperands(unsigned Opcode) const {
301 return get(Opcode).numOperands;
304 int getNumDefs(unsigned Opcode) const {
305 return get(Opcode).numDefs;
308 const unsigned *getImplicitUses(unsigned Opcode) const {
309 return get(Opcode).ImplicitUses;
312 const unsigned *getImplicitDefs(unsigned Opcode) const {
313 return get(Opcode).ImplicitDefs;
318 // Query instruction class flags according to the machine-independent
319 // flags listed above.
321 bool isReturn(unsigned Opcode) const {
322 return get(Opcode).Flags & M_RET_FLAG;
325 bool isCommutableInstr(unsigned Opcode) const {
326 return get(Opcode).Flags & M_COMMUTABLE;
329 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
330 /// custom insertion support when the DAG scheduler is inserting it into a
331 /// machine basic block.
332 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
333 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
336 bool hasVariableOperands(unsigned Opcode) const {
337 return get(Opcode).Flags & M_VARIABLE_OPS;
340 bool hasOptionalDef(unsigned Opcode) const {
341 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
344 /// isTriviallyReMaterializable - Return true if the instruction is trivially
345 /// rematerializable, meaning it has no side effects and requires no operands
346 /// that aren't always available.
347 bool isTriviallyReMaterializable(MachineInstr *MI) const {
348 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) &&
349 isReallyTriviallyReMaterializable(MI);
352 /// hasUnmodelledSideEffects - Returns true if the instruction has side
353 /// effects that are not captured by any operands of the instruction or other
355 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
356 const TargetInstrDescriptor *TID = MI->getDesc();
357 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
358 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
359 return !isReallySideEffectFree(MI); // May have side effects
362 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
363 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
364 /// instruction itself is actually trivially rematerializable, considering
365 /// its operands. This is used for targets that have instructions that are
366 /// only trivially rematerializable for specific uses. This predicate must
367 /// return false if the instruction has any side effects other than
368 /// producing a value, or if it requres any address registers that are not
369 /// always available.
370 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
374 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
375 /// method is called to determine if the specific instance of this
376 /// instruction has side effects. This is useful in cases of instructions,
377 /// like loads, which generally always have side effects. A load from a
378 /// constant pool doesn't have side effects, though. So we need to
379 /// differentiate it from the general case.
380 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
384 /// getOperandConstraint - Returns the value of the specific constraint if
385 /// it is set. Returns -1 if it is not set.
386 int getOperandConstraint(unsigned Opcode, unsigned OpNum,
387 TOI::OperandConstraint Constraint) const {
388 return get(Opcode).getOperandConstraint(OpNum, Constraint);
391 /// Return true if the instruction is a register to register move
392 /// and leave the source and dest operands in the passed parameters.
393 virtual bool isMoveInstr(const MachineInstr& MI,
395 unsigned& destReg) const {
399 /// isLoadFromStackSlot - If the specified machine instruction is a direct
400 /// load from a stack slot, return the virtual or physical register number of
401 /// the destination along with the FrameIndex of the loaded stack slot. If
402 /// not, return 0. This predicate must return 0 if the instruction has
403 /// any side effects other than loading from the stack slot.
404 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
408 /// isStoreToStackSlot - If the specified machine instruction is a direct
409 /// store to a stack slot, return the virtual or physical register number of
410 /// the source reg along with the FrameIndex of the loaded stack slot. If
411 /// not, return 0. This predicate must return 0 if the instruction has
412 /// any side effects other than storing to the stack slot.
413 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
417 /// convertToThreeAddress - This method must be implemented by targets that
418 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
419 /// may be able to convert a two-address instruction into one or more true
420 /// three-address instructions on demand. This allows the X86 target (for
421 /// example) to convert ADD and SHL instructions into LEA instructions if they
422 /// would require register copies due to two-addressness.
424 /// This method returns a null pointer if the transformation cannot be
425 /// performed, otherwise it returns the last new instruction.
427 virtual MachineInstr *
428 convertToThreeAddress(MachineFunction::iterator &MFI,
429 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
433 /// commuteInstruction - If a target has any instructions that are commutable,
434 /// but require converting to a different instruction or making non-trivial
435 /// changes to commute them, this method can overloaded to do this. The
436 /// default implementation of this method simply swaps the first two operands
437 /// of MI and returns it.
439 /// If a target wants to make more aggressive changes, they can construct and
440 /// return a new machine instruction. If an instruction cannot commute, it
441 /// can also return null.
443 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
445 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
446 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
447 /// implemented for a target). Upon success, this returns false and returns
448 /// with the following information in various cases:
450 /// 1. If this block ends with no branches (it just falls through to its succ)
451 /// just return false, leaving TBB/FBB null.
452 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
453 /// the destination block.
454 /// 3. If this block ends with an conditional branch and it falls through to
455 /// an successor block, it sets TBB to be the branch destination block and a
456 /// list of operands that evaluate the condition. These
457 /// operands can be passed to other TargetInstrInfo methods to create new
459 /// 4. If this block ends with an conditional branch and an unconditional
460 /// block, it returns the 'true' destination in TBB, the 'false' destination
461 /// in FBB, and a list of operands that evaluate the condition. These
462 /// operands can be passed to other TargetInstrInfo methods to create new
465 /// Note that RemoveBranch and InsertBranch must be implemented to support
466 /// cases where this method returns success.
468 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
469 MachineBasicBlock *&FBB,
470 std::vector<MachineOperand> &Cond) const {
474 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
475 /// this is only invoked in cases where AnalyzeBranch returns success. It
476 /// returns the number of instructions that were removed.
477 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
478 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
482 /// InsertBranch - Insert a branch into the end of the specified
483 /// MachineBasicBlock. This operands to this method are the same as those
484 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
485 /// returns success and when an unconditional branch (TBB is non-null, FBB is
486 /// null, Cond is empty) needs to be inserted. It returns the number of
487 /// instructions inserted.
488 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
489 MachineBasicBlock *FBB,
490 const std::vector<MachineOperand> &Cond) const {
491 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
495 /// copyRegToReg - Add a copy between a pair of registers
496 virtual void copyRegToReg(MachineBasicBlock &MBB,
497 MachineBasicBlock::iterator MI,
498 unsigned DestReg, unsigned SrcReg,
499 const TargetRegisterClass *DestRC,
500 const TargetRegisterClass *SrcRC) const {
501 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
504 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
505 MachineBasicBlock::iterator MI,
506 unsigned SrcReg, bool isKill, int FrameIndex,
507 const TargetRegisterClass *RC) const {
508 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
511 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
512 SmallVectorImpl<MachineOperand> &Addr,
513 const TargetRegisterClass *RC,
514 SmallVectorImpl<MachineInstr*> &NewMIs) const {
515 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
518 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
519 MachineBasicBlock::iterator MI,
520 unsigned DestReg, int FrameIndex,
521 const TargetRegisterClass *RC) const {
522 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
525 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
526 SmallVectorImpl<MachineOperand> &Addr,
527 const TargetRegisterClass *RC,
528 SmallVectorImpl<MachineInstr*> &NewMIs) const {
529 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
532 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
533 /// saved registers and returns true if it isn't possible / profitable to do
534 /// so by issuing a series of store instructions via
535 /// storeRegToStackSlot(). Returns false otherwise.
536 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
537 MachineBasicBlock::iterator MI,
538 const std::vector<CalleeSavedInfo> &CSI) const {
542 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
543 /// saved registers and returns true if it isn't possible / profitable to do
544 /// so by issuing a series of load instructions via loadRegToStackSlot().
545 /// Returns false otherwise.
546 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
547 MachineBasicBlock::iterator MI,
548 const std::vector<CalleeSavedInfo> &CSI) const {
552 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
553 /// slot into the specified machine instruction for the specified operand(s).
554 /// If this is possible, a new instruction is returned with the specified
555 /// operand folded, otherwise NULL is returned. The client is responsible for
556 /// removing the old instruction and adding the new one in the instruction
558 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
559 SmallVectorImpl<unsigned> &Ops,
560 int FrameIndex) const {
564 /// foldMemoryOperand - Same as the previous version except it allows folding
565 /// of any load and store from / to any address, not just from a specific
567 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
568 SmallVectorImpl<unsigned> &Ops,
569 MachineInstr* LoadMI) const {
573 /// canFoldMemoryOperand - Returns true if the specified load / store is
574 /// folding is possible.
576 bool canFoldMemoryOperand(MachineInstr *MI,
577 SmallVectorImpl<unsigned> &Ops) const{
581 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
582 /// a store or a load and a store into two or more instruction. If this is
583 /// possible, returns true as well as the new instructions by reference.
584 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
585 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
586 SmallVectorImpl<MachineInstr*> &NewMIs) const{
590 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
591 SmallVectorImpl<SDNode*> &NewNodes) const {
595 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
596 /// instruction after load / store are unfolded from an instruction of the
597 /// specified opcode. It returns zero if the specified unfolding is not
599 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
600 bool UnfoldLoad, bool UnfoldStore) const {
604 /// BlockHasNoFallThrough - Return true if the specified block does not
605 /// fall-through into its successor block. This is primarily used when a
606 /// branch is unanalyzable. It is useful for things like unconditional
607 /// indirect branches (jump tables).
608 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
612 /// ReverseBranchCondition - Reverses the branch condition of the specified
613 /// condition list, returning false on success and true if it cannot be
615 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
619 /// insertNoop - Insert a noop into the instruction stream at the specified
621 virtual void insertNoop(MachineBasicBlock &MBB,
622 MachineBasicBlock::iterator MI) const {
623 assert(0 && "Target didn't implement insertNoop!");
627 /// isPredicated - Returns true if the instruction is already predicated.
629 virtual bool isPredicated(const MachineInstr *MI) const {
633 /// isUnpredicatedTerminator - Returns true if the instruction is a
634 /// terminator instruction that has not been predicated.
635 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
637 /// PredicateInstruction - Convert the instruction into a predicated
638 /// instruction. It returns true if the operation was successful.
640 bool PredicateInstruction(MachineInstr *MI,
641 const std::vector<MachineOperand> &Pred) const = 0;
643 /// SubsumesPredicate - Returns true if the first specified predicate
644 /// subsumes the second, e.g. GE subsumes GT.
646 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
647 const std::vector<MachineOperand> &Pred2) const {
651 /// DefinesPredicate - If the specified instruction defines any predicate
652 /// or condition code register(s) used for predication, returns true as well
653 /// as the definition predicate(s) by reference.
654 virtual bool DefinesPredicate(MachineInstr *MI,
655 std::vector<MachineOperand> &Pred) const {
659 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
661 virtual const TargetRegisterClass *getPointerRegClass() const {
662 assert(0 && "Target didn't implement getPointerRegClass!");
664 return 0; // Must return a value in order to compile with VS 2005
668 /// TargetInstrInfoImpl - This is the default implementation of
669 /// TargetInstrInfo, which just provides a couple of default implementations
670 /// for various methods. This separated out because it is implemented in
671 /// libcodegen, not in libtarget.
672 class TargetInstrInfoImpl : public TargetInstrInfo {
674 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
675 : TargetInstrInfo(desc, NumOpcodes) {}
677 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
678 virtual bool PredicateInstruction(MachineInstr *MI,
679 const std::vector<MachineOperand> &Pred) const;
683 } // End llvm namespace