1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
32 class MachineCodeForInstruction;
33 class TargetRegisterClass;
36 //---------------------------------------------------------------------------
37 // Data types used to define information about a single machine instruction
38 //---------------------------------------------------------------------------
40 typedef short MachineOpCode;
41 typedef unsigned InstrSchedClass;
43 //---------------------------------------------------------------------------
44 // struct TargetInstrDescriptor:
45 // Predefined information about each machine instruction.
46 // Designed to initialized statically.
49 const unsigned M_BRANCH_FLAG = 1 << 0;
50 const unsigned M_CALL_FLAG = 1 << 1;
51 const unsigned M_RET_FLAG = 1 << 2;
52 const unsigned M_BARRIER_FLAG = 1 << 3;
53 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
54 const unsigned M_LOAD_FLAG = 1 << 5;
55 const unsigned M_STORE_FLAG = 1 << 6;
57 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
58 // changed into a 3-address instruction if the first two operands cannot be
59 // assigned to the same register. The target must implement the
60 // TargetInstrInfo::convertToThreeAddress method for this instruction.
61 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
63 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
64 // Z), which produces the same result if Y and Z are exchanged.
65 const unsigned M_COMMUTABLE = 1 << 8;
67 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
68 // block? Typically this is things like return and branch instructions.
69 // Various passes use this to insert code into the bottom of a basic block, but
70 // before control flow occurs.
71 const unsigned M_TERMINATOR_FLAG = 1 << 9;
73 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
74 // insertion support when the DAG scheduler is inserting it into a machine basic
76 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
78 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
79 // operands in addition to the minimum number operands specified.
80 const unsigned M_VARIABLE_OPS = 1 << 11;
82 // M_PREDICATED - Set if this instruction has a predicate that controls its
84 const unsigned M_PREDICATED = 1 << 12;
87 // Machine operand flags
88 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
89 // requires a callback to look up its register class.
90 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
92 /// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate
93 /// operand that controls an M_PREDICATED instruction.
94 const unsigned M_PREDICATE_OPERAND = 1 << 1;
97 // Operand constraints: only "tied_to" for now.
98 enum OperandConstraint {
99 TIED_TO = 0 // Must be allocated the same register as.
103 /// TargetOperandInfo - This holds information about one operand of a machine
104 /// instruction, indicating the register class for register operands, etc.
106 class TargetOperandInfo {
108 /// RegClass - This specifies the register class enumeration of the operand
109 /// if the operand is a register. If not, this contains 0.
110 unsigned short RegClass;
111 unsigned short Flags;
112 /// Lower 16 bits are used to specify which constraints are set. The higher 16
113 /// bits are used to specify the value of constraints (4 bits each).
114 unsigned int Constraints;
115 /// Currently no other information.
119 class TargetInstrDescriptor {
121 MachineOpCode Opcode; // The opcode.
122 unsigned short numOperands; // Num of args (may be more if variable_ops).
123 const char * Name; // Assembly language mnemonic for the opcode.
124 InstrSchedClass schedClass; // enum identifying instr sched class
125 unsigned Flags; // flags identifying machine instr class
126 unsigned TSFlags; // Target Specific Flag values
127 const unsigned *ImplicitUses; // Registers implicitly read by this instr
128 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
129 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
131 /// getOperandConstraint - Returns the value of the specific constraint if
132 /// it is set. Returns -1 if it is not set.
133 int getOperandConstraint(unsigned OpNum,
134 TOI::OperandConstraint Constraint) const {
135 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
136 "Invalid operand # of TargetInstrInfo");
137 if (OpNum < numOperands &&
138 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
139 unsigned Pos = 16 + Constraint * 4;
140 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
145 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
146 /// dest operand. Returns -1 if there isn't one.
147 int findTiedToSrcOperand(unsigned OpNum) const;
151 //---------------------------------------------------------------------------
153 /// TargetInstrInfo - Interface to description of machine instructions
155 class TargetInstrInfo {
156 const TargetInstrDescriptor* desc; // raw array to allow static init'n
157 unsigned NumOpcodes; // number of entries in the desc array
158 unsigned numRealOpCodes; // number of non-dummy op codes
160 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
161 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
163 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
164 virtual ~TargetInstrInfo();
166 // Invariant opcodes: All instruction sets have these as their low opcodes.
173 unsigned getNumOpcodes() const { return NumOpcodes; }
175 /// get - Return the machine instruction descriptor that corresponds to the
176 /// specified instruction opcode.
178 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
179 assert((unsigned)Opcode < NumOpcodes);
183 const char *getName(MachineOpCode Opcode) const {
184 return get(Opcode).Name;
187 int getNumOperands(MachineOpCode Opcode) const {
188 return get(Opcode).numOperands;
191 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
192 return get(Opcode).schedClass;
195 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
196 return get(Opcode).ImplicitUses;
199 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
200 return get(Opcode).ImplicitDefs;
205 // Query instruction class flags according to the machine-independent
206 // flags listed above.
208 bool isReturn(MachineOpCode Opcode) const {
209 return get(Opcode).Flags & M_RET_FLAG;
212 bool isPredicated(MachineOpCode Opcode) const {
213 return get(Opcode).Flags & M_PREDICATED;
215 bool isCommutableInstr(MachineOpCode Opcode) const {
216 return get(Opcode).Flags & M_COMMUTABLE;
218 bool isTerminatorInstr(unsigned Opcode) const {
219 return get(Opcode).Flags & M_TERMINATOR_FLAG;
222 bool isBranch(MachineOpCode Opcode) const {
223 return get(Opcode).Flags & M_BRANCH_FLAG;
226 /// isBarrier - Returns true if the specified instruction stops control flow
227 /// from executing the instruction immediately following it. Examples include
228 /// unconditional branches and return instructions.
229 bool isBarrier(MachineOpCode Opcode) const {
230 return get(Opcode).Flags & M_BARRIER_FLAG;
233 bool isCall(MachineOpCode Opcode) const {
234 return get(Opcode).Flags & M_CALL_FLAG;
236 bool isLoad(MachineOpCode Opcode) const {
237 return get(Opcode).Flags & M_LOAD_FLAG;
239 bool isStore(MachineOpCode Opcode) const {
240 return get(Opcode).Flags & M_STORE_FLAG;
243 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
244 /// which must be filled by the code generator.
245 bool hasDelaySlot(unsigned Opcode) const {
246 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
249 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
250 /// custom insertion support when the DAG scheduler is inserting it into a
251 /// machine basic block.
252 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
253 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
256 bool hasVariableOperands(MachineOpCode Opcode) const {
257 return get(Opcode).Flags & M_VARIABLE_OPS;
260 /// getOperandConstraint - Returns the value of the specific constraint if
261 /// it is set. Returns -1 if it is not set.
262 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
263 TOI::OperandConstraint Constraint) const {
264 return get(Opcode).getOperandConstraint(OpNum, Constraint);
267 /// Return true if the instruction is a register to register move
268 /// and leave the source and dest operands in the passed parameters.
269 virtual bool isMoveInstr(const MachineInstr& MI,
271 unsigned& destReg) const {
275 /// isLoadFromStackSlot - If the specified machine instruction is a direct
276 /// load from a stack slot, return the virtual or physical register number of
277 /// the destination along with the FrameIndex of the loaded stack slot. If
278 /// not, return 0. This predicate must return 0 if the instruction has
279 /// any side effects other than loading from the stack slot.
280 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
284 /// isStoreToStackSlot - If the specified machine instruction is a direct
285 /// store to a stack slot, return the virtual or physical register number of
286 /// the source reg along with the FrameIndex of the loaded stack slot. If
287 /// not, return 0. This predicate must return 0 if the instruction has
288 /// any side effects other than storing to the stack slot.
289 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
293 /// convertToThreeAddress - This method must be implemented by targets that
294 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
295 /// may be able to convert a two-address instruction into one or moretrue
296 /// three-address instructions on demand. This allows the X86 target (for
297 /// example) to convert ADD and SHL instructions into LEA instructions if they
298 /// would require register copies due to two-addressness.
300 /// This method returns a null pointer if the transformation cannot be
301 /// performed, otherwise it returns the last new instruction.
303 virtual MachineInstr *
304 convertToThreeAddress(MachineFunction::iterator &MFI,
305 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
309 /// commuteInstruction - If a target has any instructions that are commutable,
310 /// but require converting to a different instruction or making non-trivial
311 /// changes to commute them, this method can overloaded to do this. The
312 /// default implementation of this method simply swaps the first two operands
313 /// of MI and returns it.
315 /// If a target wants to make more aggressive changes, they can construct and
316 /// return a new machine instruction. If an instruction cannot commute, it
317 /// can also return null.
319 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
321 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
322 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
323 /// implemented for a target). Upon success, this returns false and returns
324 /// with the following information in various cases:
326 /// 1. If this block ends with no branches (it just falls through to its succ)
327 /// just return false, leaving TBB/FBB null.
328 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
329 /// the destination block.
330 /// 3. If this block ends with an conditional branch, it returns the 'true'
331 /// destination in TBB, the 'false' destination in FBB, and a list of
332 /// operands that evaluate the condition. These operands can be passed to
333 /// other TargetInstrInfo methods to create new branches.
335 /// Note that RemoveBranch and InsertBranch must be implemented to support
336 /// cases where this method returns success.
338 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
339 MachineBasicBlock *&FBB,
340 std::vector<MachineOperand> &Cond) const {
344 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
345 /// this is only invoked in cases where AnalyzeBranch returns success.
346 virtual void RemoveBranch(MachineBasicBlock &MBB) const {
347 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
350 /// InsertBranch - Insert a branch into the end of the specified
351 /// MachineBasicBlock. This operands to this method are the same as those
352 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
353 /// returns success and when an unconditional branch (TBB is non-null, FBB is
354 /// null, Cond is empty) needs to be inserted.
355 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
356 MachineBasicBlock *FBB,
357 const std::vector<MachineOperand> &Cond) const {
358 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
361 /// BlockHasNoFallThrough - Return true if the specified block does not
362 /// fall-through into its successor block. This is primarily used when a
363 /// branch is unanalyzable. It is useful for things like unconditional
364 /// indirect branches (jump tables).
365 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
369 /// ReverseBranchCondition - Reverses the branch condition of the specified
370 /// condition list, returning false on success and true if it cannot be
372 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
376 /// insertNoop - Insert a noop into the instruction stream at the specified
378 virtual void insertNoop(MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator MI) const {
380 assert(0 && "Target didn't implement insertNoop!");
384 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
386 virtual const TargetRegisterClass *getPointerRegClass() const {
387 assert(0 && "Target didn't implement getPointerRegClass!");
392 } // End llvm namespace