1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class TargetRegisterClass;
24 class CalleeSavedInfo;
28 template<class T> class SmallVectorImpl;
31 //---------------------------------------------------------------------------
33 /// TargetInstrInfo - Interface to description of machine instructions
35 class TargetInstrInfo {
36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
37 unsigned NumOpcodes; // Number of entries in the desc array
39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
43 virtual ~TargetInstrInfo();
45 // Invariant opcodes: All instruction sets have these as their low opcodes.
54 unsigned getNumOpcodes() const { return NumOpcodes; }
56 /// get - Return the machine instruction descriptor that corresponds to the
57 /// specified instruction opcode.
59 const TargetInstrDesc &get(unsigned Opcode) const {
60 assert(Opcode < NumOpcodes && "Invalid opcode!");
61 return Descriptors[Opcode];
64 /// isTriviallyReMaterializable - Return true if the instruction is trivially
65 /// rematerializable, meaning it has no side effects and requires no operands
66 /// that aren't always available.
67 bool isTriviallyReMaterializable(MachineInstr *MI) const {
68 return MI->getDesc().isRematerializable() &&
69 isReallyTriviallyReMaterializable(MI);
73 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
74 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
75 /// instruction itself is actually trivially rematerializable, considering
76 /// its operands. This is used for targets that have instructions that are
77 /// only trivially rematerializable for specific uses. This predicate must
78 /// return false if the instruction has any side effects other than
79 /// producing a value, or if it requres any address registers that are not
81 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
86 /// Return true if the instruction is a register to register move
87 /// and leave the source and dest operands in the passed parameters.
88 virtual bool isMoveInstr(const MachineInstr& MI,
90 unsigned& destReg) const {
94 /// isLoadFromStackSlot - If the specified machine instruction is a direct
95 /// load from a stack slot, return the virtual or physical register number of
96 /// the destination along with the FrameIndex of the loaded stack slot. If
97 /// not, return 0. This predicate must return 0 if the instruction has
98 /// any side effects other than loading from the stack slot.
99 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
103 /// isStoreToStackSlot - If the specified machine instruction is a direct
104 /// store to a stack slot, return the virtual or physical register number of
105 /// the source reg along with the FrameIndex of the loaded stack slot. If
106 /// not, return 0. This predicate must return 0 if the instruction has
107 /// any side effects other than storing to the stack slot.
108 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
112 /// isInvariantLoad - Return true if the specified instruction (which is
113 /// marked mayLoad) is loading from a location whose value is invariant across
114 /// the function. For example, loading a value from the constant pool or from
115 /// from the argument area of a function if it does not change. This should
116 /// only return true of *all* loads the instruction does are invariant (if it
117 /// does multiple loads).
118 virtual bool isInvariantLoad(MachineInstr *MI) const {
123 /// convertToThreeAddress - This method must be implemented by targets that
124 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
125 /// may be able to convert a two-address instruction into one or more true
126 /// three-address instructions on demand. This allows the X86 target (for
127 /// example) to convert ADD and SHL instructions into LEA instructions if they
128 /// would require register copies due to two-addressness.
130 /// This method returns a null pointer if the transformation cannot be
131 /// performed, otherwise it returns the last new instruction.
133 virtual MachineInstr *
134 convertToThreeAddress(MachineFunction::iterator &MFI,
135 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
139 /// commuteInstruction - If a target has any instructions that are commutable,
140 /// but require converting to a different instruction or making non-trivial
141 /// changes to commute them, this method can overloaded to do this. The
142 /// default implementation of this method simply swaps the first two operands
143 /// of MI and returns it.
145 /// If a target wants to make more aggressive changes, they can construct and
146 /// return a new machine instruction. If an instruction cannot commute, it
147 /// can also return null.
149 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
151 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
152 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
153 /// implemented for a target). Upon success, this returns false and returns
154 /// with the following information in various cases:
156 /// 1. If this block ends with no branches (it just falls through to its succ)
157 /// just return false, leaving TBB/FBB null.
158 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
159 /// the destination block.
160 /// 3. If this block ends with an conditional branch and it falls through to
161 /// an successor block, it sets TBB to be the branch destination block and a
162 /// list of operands that evaluate the condition. These
163 /// operands can be passed to other TargetInstrInfo methods to create new
165 /// 4. If this block ends with an conditional branch and an unconditional
166 /// block, it returns the 'true' destination in TBB, the 'false' destination
167 /// in FBB, and a list of operands that evaluate the condition. These
168 /// operands can be passed to other TargetInstrInfo methods to create new
171 /// Note that RemoveBranch and InsertBranch must be implemented to support
172 /// cases where this method returns success.
174 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
175 MachineBasicBlock *&FBB,
176 std::vector<MachineOperand> &Cond) const {
180 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
181 /// this is only invoked in cases where AnalyzeBranch returns success. It
182 /// returns the number of instructions that were removed.
183 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
184 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
188 /// InsertBranch - Insert a branch into the end of the specified
189 /// MachineBasicBlock. This operands to this method are the same as those
190 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
191 /// returns success and when an unconditional branch (TBB is non-null, FBB is
192 /// null, Cond is empty) needs to be inserted. It returns the number of
193 /// instructions inserted.
194 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
195 MachineBasicBlock *FBB,
196 const std::vector<MachineOperand> &Cond) const {
197 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
201 /// copyRegToReg - Add a copy between a pair of registers
202 virtual void copyRegToReg(MachineBasicBlock &MBB,
203 MachineBasicBlock::iterator MI,
204 unsigned DestReg, unsigned SrcReg,
205 const TargetRegisterClass *DestRC,
206 const TargetRegisterClass *SrcRC) const {
207 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
210 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator MI,
212 unsigned SrcReg, bool isKill, int FrameIndex,
213 const TargetRegisterClass *RC) const {
214 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
217 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
218 SmallVectorImpl<MachineOperand> &Addr,
219 const TargetRegisterClass *RC,
220 SmallVectorImpl<MachineInstr*> &NewMIs) const {
221 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
224 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
225 MachineBasicBlock::iterator MI,
226 unsigned DestReg, int FrameIndex,
227 const TargetRegisterClass *RC) const {
228 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
231 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
232 SmallVectorImpl<MachineOperand> &Addr,
233 const TargetRegisterClass *RC,
234 SmallVectorImpl<MachineInstr*> &NewMIs) const {
235 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
238 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
239 /// saved registers and returns true if it isn't possible / profitable to do
240 /// so by issuing a series of store instructions via
241 /// storeRegToStackSlot(). Returns false otherwise.
242 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator MI,
244 const std::vector<CalleeSavedInfo> &CSI) const {
248 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
249 /// saved registers and returns true if it isn't possible / profitable to do
250 /// so by issuing a series of load instructions via loadRegToStackSlot().
251 /// Returns false otherwise.
252 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator MI,
254 const std::vector<CalleeSavedInfo> &CSI) const {
258 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
259 /// slot into the specified machine instruction for the specified operand(s).
260 /// If this is possible, a new instruction is returned with the specified
261 /// operand folded, otherwise NULL is returned. The client is responsible for
262 /// removing the old instruction and adding the new one in the instruction
264 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
265 SmallVectorImpl<unsigned> &Ops,
266 int FrameIndex) const {
270 /// foldMemoryOperand - Same as the previous version except it allows folding
271 /// of any load and store from / to any address, not just from a specific
273 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
274 SmallVectorImpl<unsigned> &Ops,
275 MachineInstr* LoadMI) const {
279 /// canFoldMemoryOperand - Returns true if the specified load / store is
280 /// folding is possible.
282 bool canFoldMemoryOperand(MachineInstr *MI,
283 SmallVectorImpl<unsigned> &Ops) const{
287 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
288 /// a store or a load and a store into two or more instruction. If this is
289 /// possible, returns true as well as the new instructions by reference.
290 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
291 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
292 SmallVectorImpl<MachineInstr*> &NewMIs) const{
296 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
297 SmallVectorImpl<SDNode*> &NewNodes) const {
301 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
302 /// instruction after load / store are unfolded from an instruction of the
303 /// specified opcode. It returns zero if the specified unfolding is not
305 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
306 bool UnfoldLoad, bool UnfoldStore) const {
310 /// BlockHasNoFallThrough - Return true if the specified block does not
311 /// fall-through into its successor block. This is primarily used when a
312 /// branch is unanalyzable. It is useful for things like unconditional
313 /// indirect branches (jump tables).
314 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
318 /// ReverseBranchCondition - Reverses the branch condition of the specified
319 /// condition list, returning false on success and true if it cannot be
321 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
325 /// insertNoop - Insert a noop into the instruction stream at the specified
327 virtual void insertNoop(MachineBasicBlock &MBB,
328 MachineBasicBlock::iterator MI) const {
329 assert(0 && "Target didn't implement insertNoop!");
333 /// isPredicated - Returns true if the instruction is already predicated.
335 virtual bool isPredicated(const MachineInstr *MI) const {
339 /// isUnpredicatedTerminator - Returns true if the instruction is a
340 /// terminator instruction that has not been predicated.
341 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
343 /// PredicateInstruction - Convert the instruction into a predicated
344 /// instruction. It returns true if the operation was successful.
346 bool PredicateInstruction(MachineInstr *MI,
347 const std::vector<MachineOperand> &Pred) const = 0;
349 /// SubsumesPredicate - Returns true if the first specified predicate
350 /// subsumes the second, e.g. GE subsumes GT.
352 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
353 const std::vector<MachineOperand> &Pred2) const {
357 /// DefinesPredicate - If the specified instruction defines any predicate
358 /// or condition code register(s) used for predication, returns true as well
359 /// as the definition predicate(s) by reference.
360 virtual bool DefinesPredicate(MachineInstr *MI,
361 std::vector<MachineOperand> &Pred) const {
365 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
367 virtual const TargetRegisterClass *getPointerRegClass() const {
368 assert(0 && "Target didn't implement getPointerRegClass!");
370 return 0; // Must return a value in order to compile with VS 2005
374 /// TargetInstrInfoImpl - This is the default implementation of
375 /// TargetInstrInfo, which just provides a couple of default implementations
376 /// for various methods. This separated out because it is implemented in
377 /// libcodegen, not in libtarget.
378 class TargetInstrInfoImpl : public TargetInstrInfo {
380 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
381 : TargetInstrInfo(desc, NumOpcodes) {}
383 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
384 virtual bool PredicateInstruction(MachineInstr *MI,
385 const std::vector<MachineOperand> &Pred) const;
389 } // End llvm namespace