1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "Support/NonCopyable.h"
11 #include "Support/DataTypes.h"
15 class MachineInstrDescriptor;
23 //---------------------------------------------------------------------------
24 // Data types used to define information about a single machine instruction
25 //---------------------------------------------------------------------------
27 typedef int MachineOpCode;
28 typedef int OpCodeMask;
29 typedef int InstrSchedClass;
31 // Global variable holding an array of descriptors for machine instructions.
32 // The actual object needs to be created separately for each target machine.
33 // This variable is initialized and reset by class MachineInstrInfo.
35 // FIXME: This should be a property of the target so that more than one target
36 // at a time can be active...
38 extern const MachineInstrDescriptor *TargetInstrDescriptors;
41 //---------------------------------------------------------------------------
42 // struct MachineInstrDescriptor:
43 // Predefined information about each machine instruction.
44 // Designed to initialized statically.
46 // class MachineInstructionInfo
47 // Interface to description of machine instructions
49 //---------------------------------------------------------------------------
52 const unsigned int M_NOP_FLAG = 1;
53 const unsigned int M_BRANCH_FLAG = 1 << 1;
54 const unsigned int M_CALL_FLAG = 1 << 2;
55 const unsigned int M_RET_FLAG = 1 << 3;
56 const unsigned int M_ARITH_FLAG = 1 << 4;
57 const unsigned int M_CC_FLAG = 1 << 6;
58 const unsigned int M_LOGICAL_FLAG = 1 << 6;
59 const unsigned int M_INT_FLAG = 1 << 7;
60 const unsigned int M_FLOAT_FLAG = 1 << 8;
61 const unsigned int M_CONDL_FLAG = 1 << 9;
62 const unsigned int M_LOAD_FLAG = 1 << 10;
63 const unsigned int M_PREFETCH_FLAG = 1 << 11;
64 const unsigned int M_STORE_FLAG = 1 << 12;
65 const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
66 const unsigned int M_PSEUDO_FLAG = 1 << 14;
69 struct MachineInstrDescriptor {
70 std::string opCodeString; // Assembly language mnemonic for the opcode.
71 int numOperands; // Number of args; -1 if variable #args
72 int resultPos; // Position of the result; -1 if no result
73 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
74 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
75 // smallest -ve value is -(maxImmedConst+1).
76 unsigned int numDelaySlots; // Number of delay slots after instruction
77 unsigned int latency; // Latency in machine cycles
78 InstrSchedClass schedClass; // enum identifying instr sched class
79 unsigned int iclass; // flags identifying machine instr class
83 class MachineInstrInfo : public NonCopyableV {
85 const TargetMachine& target;
88 const MachineInstrDescriptor* desc; // raw array to allow static init'n
89 unsigned int descSize; // number of entries in the desc array
90 unsigned int numRealOpCodes; // number of non-dummy op codes
93 MachineInstrInfo(const TargetMachine& tgt,
94 const MachineInstrDescriptor *desc, unsigned descSize,
95 unsigned numRealOpCodes);
96 virtual ~MachineInstrInfo();
98 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
99 unsigned getNumTotalOpCodes() const { return descSize; }
101 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
102 assert(opCode >= 0 && opCode < (int)descSize);
106 int getNumOperands(MachineOpCode opCode) const {
107 return getDescriptor(opCode).numOperands;
110 int getResultPos(MachineOpCode opCode) const {
111 return getDescriptor(opCode).resultPos;
114 unsigned getNumDelaySlots(MachineOpCode opCode) const {
115 return getDescriptor(opCode).numDelaySlots;
118 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
119 return getDescriptor(opCode).schedClass;
123 // Query instruction class flags according to the machine-independent
124 // flags listed above.
126 unsigned int getIClass(MachineOpCode opCode) const {
127 return getDescriptor(opCode).iclass;
129 bool isNop(MachineOpCode opCode) const {
130 return getDescriptor(opCode).iclass & M_NOP_FLAG;
132 bool isBranch(MachineOpCode opCode) const {
133 return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
135 bool isCall(MachineOpCode opCode) const {
136 return getDescriptor(opCode).iclass & M_CALL_FLAG;
138 bool isReturn(MachineOpCode opCode) const {
139 return getDescriptor(opCode).iclass & M_RET_FLAG;
141 bool isControlFlow(MachineOpCode opCode) const {
142 return getDescriptor(opCode).iclass & M_BRANCH_FLAG
143 || getDescriptor(opCode).iclass & M_CALL_FLAG
144 || getDescriptor(opCode).iclass & M_RET_FLAG;
146 bool isArith(MachineOpCode opCode) const {
147 return getDescriptor(opCode).iclass & M_RET_FLAG;
149 bool isCCInstr(MachineOpCode opCode) const {
150 return getDescriptor(opCode).iclass & M_CC_FLAG;
152 bool isLogical(MachineOpCode opCode) const {
153 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
155 bool isIntInstr(MachineOpCode opCode) const {
156 return getDescriptor(opCode).iclass & M_INT_FLAG;
158 bool isFloatInstr(MachineOpCode opCode) const {
159 return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
161 bool isConditional(MachineOpCode opCode) const {
162 return getDescriptor(opCode).iclass & M_CONDL_FLAG;
164 bool isLoad(MachineOpCode opCode) const {
165 return getDescriptor(opCode).iclass & M_LOAD_FLAG;
167 bool isPrefetch(MachineOpCode opCode) const {
168 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
170 bool isLoadOrPrefetch(MachineOpCode opCode) const {
171 return getDescriptor(opCode).iclass & M_LOAD_FLAG
172 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
174 bool isStore(MachineOpCode opCode) const {
175 return getDescriptor(opCode).iclass & M_STORE_FLAG;
177 bool isMemoryAccess(MachineOpCode opCode) const {
178 return getDescriptor(opCode).iclass & M_LOAD_FLAG
179 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG
180 || getDescriptor(opCode).iclass & M_STORE_FLAG;
182 bool isDummyPhiInstr(const MachineOpCode opCode) const {
183 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
187 // delete this later *******
188 bool isPhi(const MachineOpCode opCode) const
189 { return isDummyPhiInstr(opCode); }
191 bool isPseudoInstr(const MachineOpCode opCode) const {
192 return getDescriptor(opCode).iclass & M_PSEUDO_FLAG;
196 // Check if an instruction can be issued before its operands are ready,
197 // or if a subsequent instruction that uses its result can be issued
198 // before the results are ready.
199 // Default to true since most instructions on many architectures allow this.
201 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
205 virtual bool hasResultInterlock(MachineOpCode opCode) const {
210 // Latencies for individual instructions and instruction pairs
212 virtual int minLatency(MachineOpCode opCode) const {
213 return getDescriptor(opCode).latency;
216 virtual int maxLatency(MachineOpCode opCode) const {
217 return getDescriptor(opCode).latency;
221 // Which operand holds an immediate constant? Returns -1 if none
223 virtual int getImmmedConstantPos(MachineOpCode opCode) const {
224 return -1; // immediate position is machine specific, so say -1 == "none"
227 // Check if the specified constant fits in the immediate field
228 // of this machine instruction
230 virtual bool constantFitsInImmedField(MachineOpCode opCode,
231 int64_t intValue) const;
233 // Return the largest +ve constant that can be held in the IMMMED field
234 // of this machine instruction.
235 // isSignExtended is set to true if the value is sign-extended before use
236 // (this is true for all immediate fields in SPARC instructions).
237 // Return 0 if the instruction has no IMMED field.
239 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
240 bool &isSignExtended) const {
241 isSignExtended = getDescriptor(opCode).immedIsSignExtended;
242 return getDescriptor(opCode).maxImmedConst;
245 //-------------------------------------------------------------------------
246 // Code generation support for creating individual machine instructions
247 //-------------------------------------------------------------------------
249 // Create an instruction sequence to put the constant `val' into
250 // the virtual register `dest'. `val' may be a Constant or a
251 // GlobalValue, viz., the constant address of a global variable or function.
252 // The generated instructions are returned in `minstrVec'.
253 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
255 virtual void CreateCodeToLoadConst(Value* val,
257 std::vector<MachineInstr*>& minstrVec,
258 std::vector<TmpInstruction*> &) const = 0;
260 // Create an instruction sequence to copy an integer value `val'
261 // to a floating point value `dest' by copying to memory and back.
262 // val must be an integral type. dest must be a Float or Double.
263 // The generated instructions are returned in `minstrVec'.
264 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
266 virtual void CreateCodeToCopyIntToFloat(Method* method,
269 std::vector<MachineInstr*>& minstVec,
270 std::vector<TmpInstruction*>& tmpVec,
271 TargetMachine& target) const = 0;
273 // Similarly, create an instruction sequence to copy an FP value
274 // `val' to an integer value `dest' by copying to memory and back.
275 // See the previous function for information about return values.
277 virtual void CreateCodeToCopyFloatToInt(Method* method,
280 std::vector<MachineInstr*>& minstVec,
281 std::vector<TmpInstruction*>& tmpVec,
282 TargetMachine& target) const = 0;
285 // create copy instruction(s)
287 CreateCopyInstructionsByType(const TargetMachine& target,
290 std::vector<MachineInstr*>& minstrVec) const = 0;