1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class TargetRegisterClass;
23 class TargetRegisterInfo;
25 class CalleeSavedInfo;
29 template<class T> class SmallVectorImpl;
32 //---------------------------------------------------------------------------
34 /// TargetInstrInfo - Interface to description of machine instruction set
36 class TargetInstrInfo {
37 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
38 unsigned NumOpcodes; // Number of entries in the desc array
40 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
41 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
43 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
44 virtual ~TargetInstrInfo();
46 // Invariant opcodes: All instruction sets have these as their low opcodes.
55 /// EXTRACT_SUBREG - This instruction takes two operands: a register
56 /// that has subregisters, and a subregister index. It returns the
57 /// extracted subregister value. This is commonly used to implement
58 /// truncation operations on target architectures which support it.
61 /// INSERT_SUBREG - This instruction takes three operands: a register
62 /// that has subregisters, a register providing an insert value, and a
63 /// subregister index. It returns the value of the first register with
64 /// the value of the second register inserted. The first register is
65 /// often defined by an IMPLICIT_DEF, as is commonly used to implement
66 /// anyext operations on target architectures which support it.
69 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
72 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
73 /// that the first operand is an immediate integer constant. This constant
74 /// is often zero, as is commonly used to implement zext operations on
75 /// target architectures which support it, such as with x86-64 (with
76 /// zext from i32 to i64 via implicit zero-extension).
79 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
80 /// register-to-register copy into a specific register class. This is only
81 /// used between instruction selection and MachineInstr creation, before
82 /// virtual registers have been created for all the instructions, and it's
83 /// only needed in cases where the register classes implied by the
84 /// instructions are insufficient. The actual MachineInstrs to perform
85 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
89 unsigned getNumOpcodes() const { return NumOpcodes; }
91 /// get - Return the machine instruction descriptor that corresponds to the
92 /// specified instruction opcode.
94 const TargetInstrDesc &get(unsigned Opcode) const {
95 assert(Opcode < NumOpcodes && "Invalid opcode!");
96 return Descriptors[Opcode];
99 /// isTriviallyReMaterializable - Return true if the instruction is trivially
100 /// rematerializable, meaning it has no side effects and requires no operands
101 /// that aren't always available.
102 bool isTriviallyReMaterializable(const MachineInstr *MI) const {
103 return MI->getDesc().isRematerializable() &&
104 isReallyTriviallyReMaterializable(MI);
108 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
109 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
110 /// instruction itself is actually trivially rematerializable, considering
111 /// its operands. This is used for targets that have instructions that are
112 /// only trivially rematerializable for specific uses. This predicate must
113 /// return false if the instruction has any side effects other than
114 /// producing a value, or if it requres any address registers that are not
115 /// always available.
116 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
121 /// Return true if the instruction is a register to register move and return
122 /// the source and dest operands and their sub-register indices by reference.
123 virtual bool isMoveInstr(const MachineInstr& MI,
124 unsigned& SrcReg, unsigned& DstReg,
125 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
129 /// isLoadFromStackSlot - If the specified machine instruction is a direct
130 /// load from a stack slot, return the virtual or physical register number of
131 /// the destination along with the FrameIndex of the loaded stack slot. If
132 /// not, return 0. This predicate must return 0 if the instruction has
133 /// any side effects other than loading from the stack slot.
134 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
135 int &FrameIndex) const {
139 /// isStoreToStackSlot - If the specified machine instruction is a direct
140 /// store to a stack slot, return the virtual or physical register number of
141 /// the source reg along with the FrameIndex of the loaded stack slot. If
142 /// not, return 0. This predicate must return 0 if the instruction has
143 /// any side effects other than storing to the stack slot.
144 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
145 int &FrameIndex) const {
149 /// reMaterialize - Re-issue the specified 'original' instruction at the
150 /// specific location targeting a new destination register.
151 virtual void reMaterialize(MachineBasicBlock &MBB,
152 MachineBasicBlock::iterator MI,
154 const MachineInstr *Orig) const = 0;
156 /// isInvariantLoad - Return true if the specified instruction (which is
157 /// marked mayLoad) is loading from a location whose value is invariant across
158 /// the function. For example, loading a value from the constant pool or from
159 /// from the argument area of a function if it does not change. This should
160 /// only return true of *all* loads the instruction does are invariant (if it
161 /// does multiple loads).
162 virtual bool isInvariantLoad(const MachineInstr *MI) const {
166 /// convertToThreeAddress - This method must be implemented by targets that
167 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
168 /// may be able to convert a two-address instruction into one or more true
169 /// three-address instructions on demand. This allows the X86 target (for
170 /// example) to convert ADD and SHL instructions into LEA instructions if they
171 /// would require register copies due to two-addressness.
173 /// This method returns a null pointer if the transformation cannot be
174 /// performed, otherwise it returns the last new instruction.
176 virtual MachineInstr *
177 convertToThreeAddress(MachineFunction::iterator &MFI,
178 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
182 /// commuteInstruction - If a target has any instructions that are commutable,
183 /// but require converting to a different instruction or making non-trivial
184 /// changes to commute them, this method can overloaded to do this. The
185 /// default implementation of this method simply swaps the first two operands
186 /// of MI and returns it.
188 /// If a target wants to make more aggressive changes, they can construct and
189 /// return a new machine instruction. If an instruction cannot commute, it
190 /// can also return null.
192 /// If NewMI is true, then a new machine instruction must be created.
194 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
195 bool NewMI = false) const = 0;
197 /// CommuteChangesDestination - Return true if commuting the specified
198 /// instruction will also changes the destination operand. Also return the
199 /// current operand index of the would be new destination register by
200 /// reference. This can happen when the commutable instruction is also a
201 /// two-address instruction.
202 virtual bool CommuteChangesDestination(MachineInstr *MI,
203 unsigned &OpIdx) const = 0;
205 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
206 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
207 /// implemented for a target). Upon success, this returns false and returns
208 /// with the following information in various cases:
210 /// 1. If this block ends with no branches (it just falls through to its succ)
211 /// just return false, leaving TBB/FBB null.
212 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
213 /// the destination block.
214 /// 3. If this block ends with an conditional branch and it falls through to
215 /// an successor block, it sets TBB to be the branch destination block and
216 /// a list of operands that evaluate the condition. These
217 /// operands can be passed to other TargetInstrInfo methods to create new
219 /// 4. If this block ends with an conditional branch and an unconditional
220 /// block, it returns the 'true' destination in TBB, the 'false'
221 /// destination in FBB, and a list of operands that evaluate the condition.
222 /// These operands can be passed to other TargetInstrInfo methods to create
225 /// Note that RemoveBranch and InsertBranch must be implemented to support
226 /// cases where this method returns success.
228 /// If AllowModify is true, then this routine is allowed to modify the basic
229 /// block (e.g. delete instructions after the unconditional branch).
231 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
232 MachineBasicBlock *&FBB,
233 SmallVectorImpl<MachineOperand> &Cond,
234 bool AllowModify = false) const {
238 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
239 /// This is only invoked in cases where AnalyzeBranch returns success. It
240 /// returns the number of instructions that were removed.
241 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
242 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
246 /// InsertBranch - Insert a branch into the end of the specified
247 /// MachineBasicBlock. This operands to this method are the same as those
248 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
249 /// returns success and when an unconditional branch (TBB is non-null, FBB is
250 /// null, Cond is empty) needs to be inserted. It returns the number of
251 /// instructions inserted.
253 /// It is also invoked by tail merging to add unconditional branches in
254 /// cases where AnalyzeBranch doesn't apply because there was no original
255 /// branch to analyze. At least this much must be implemented, else tail
256 /// merging needs to be disabled.
257 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
258 MachineBasicBlock *FBB,
259 const SmallVectorImpl<MachineOperand> &Cond) const {
260 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
264 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
265 /// returns false if the target does not how to copy between the specified
267 virtual bool copyRegToReg(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator MI,
269 unsigned DestReg, unsigned SrcReg,
270 const TargetRegisterClass *DestRC,
271 const TargetRegisterClass *SrcRC) const {
272 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
276 /// storeRegToStackSlot - Store the specified register of the given register
277 /// class to the specified stack frame index. The store instruction is to be
278 /// added to the given machine basic block before the specified machine
279 /// instruction. If isKill is true, the register operand is the last use and
280 /// must be marked kill.
281 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
282 MachineBasicBlock::iterator MI,
283 unsigned SrcReg, bool isKill, int FrameIndex,
284 const TargetRegisterClass *RC) const {
285 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
288 /// storeRegToAddr - Store the specified register of the given register class
289 /// to the specified address. The store instruction is to be added to the
290 /// given machine basic block before the specified machine instruction. If
291 /// isKill is true, the register operand is the last use and must be marked
293 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
294 SmallVectorImpl<MachineOperand> &Addr,
295 const TargetRegisterClass *RC,
296 SmallVectorImpl<MachineInstr*> &NewMIs) const {
297 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
300 /// loadRegFromStackSlot - Load the specified register of the given register
301 /// class from the specified stack frame index. The load instruction is to be
302 /// added to the given machine basic block before the specified machine
304 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
305 MachineBasicBlock::iterator MI,
306 unsigned DestReg, int FrameIndex,
307 const TargetRegisterClass *RC) const {
308 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
311 /// loadRegFromAddr - Load the specified register of the given register class
312 /// class from the specified address. The load instruction is to be added to
313 /// the given machine basic block before the specified machine instruction.
314 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
315 SmallVectorImpl<MachineOperand> &Addr,
316 const TargetRegisterClass *RC,
317 SmallVectorImpl<MachineInstr*> &NewMIs) const {
318 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
321 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
322 /// saved registers and returns true if it isn't possible / profitable to do
323 /// so by issuing a series of store instructions via
324 /// storeRegToStackSlot(). Returns false otherwise.
325 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
326 MachineBasicBlock::iterator MI,
327 const std::vector<CalleeSavedInfo> &CSI) const {
331 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
332 /// saved registers and returns true if it isn't possible / profitable to do
333 /// so by issuing a series of load instructions via loadRegToStackSlot().
334 /// Returns false otherwise.
335 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
336 MachineBasicBlock::iterator MI,
337 const std::vector<CalleeSavedInfo> &CSI) const {
341 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
342 /// slot into the specified machine instruction for the specified operand(s).
343 /// If this is possible, a new instruction is returned with the specified
344 /// operand folded, otherwise NULL is returned. The client is responsible for
345 /// removing the old instruction and adding the new one in the instruction
347 MachineInstr* foldMemoryOperand(MachineFunction &MF,
349 const SmallVectorImpl<unsigned> &Ops,
350 int FrameIndex) const;
352 /// foldMemoryOperand - Same as the previous version except it allows folding
353 /// of any load and store from / to any address, not just from a specific
355 MachineInstr* foldMemoryOperand(MachineFunction &MF,
357 const SmallVectorImpl<unsigned> &Ops,
358 MachineInstr* LoadMI) const;
361 /// foldMemoryOperandImpl - Target-dependent implementation for
362 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
363 /// take care of adding a MachineMemOperand to the newly created instruction.
364 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
366 const SmallVectorImpl<unsigned> &Ops,
367 int FrameIndex) const {
371 /// foldMemoryOperandImpl - Target-dependent implementation for
372 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
373 /// take care of adding a MachineMemOperand to the newly created instruction.
374 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
376 const SmallVectorImpl<unsigned> &Ops,
377 MachineInstr* LoadMI) const {
382 /// canFoldMemoryOperand - Returns true for the specified load / store if
383 /// folding is possible.
385 bool canFoldMemoryOperand(const MachineInstr *MI,
386 const SmallVectorImpl<unsigned> &Ops) const {
390 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
391 /// a store or a load and a store into two or more instruction. If this is
392 /// possible, returns true as well as the new instructions by reference.
393 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
394 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
395 SmallVectorImpl<MachineInstr*> &NewMIs) const{
399 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
400 SmallVectorImpl<SDNode*> &NewNodes) const {
404 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
405 /// instruction after load / store are unfolded from an instruction of the
406 /// specified opcode. It returns zero if the specified unfolding is not
408 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
409 bool UnfoldLoad, bool UnfoldStore) const {
413 /// BlockHasNoFallThrough - Return true if the specified block does not
414 /// fall-through into its successor block. This is primarily used when a
415 /// branch is unanalyzable. It is useful for things like unconditional
416 /// indirect branches (jump tables).
417 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
421 /// ReverseBranchCondition - Reverses the branch condition of the specified
422 /// condition list, returning false on success and true if it cannot be
425 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
429 /// insertNoop - Insert a noop into the instruction stream at the specified
431 virtual void insertNoop(MachineBasicBlock &MBB,
432 MachineBasicBlock::iterator MI) const {
433 assert(0 && "Target didn't implement insertNoop!");
437 /// isPredicated - Returns true if the instruction is already predicated.
439 virtual bool isPredicated(const MachineInstr *MI) const {
443 /// isUnpredicatedTerminator - Returns true if the instruction is a
444 /// terminator instruction that has not been predicated.
445 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
447 /// PredicateInstruction - Convert the instruction into a predicated
448 /// instruction. It returns true if the operation was successful.
450 bool PredicateInstruction(MachineInstr *MI,
451 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
453 /// SubsumesPredicate - Returns true if the first specified predicate
454 /// subsumes the second, e.g. GE subsumes GT.
456 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
457 const SmallVectorImpl<MachineOperand> &Pred2) const {
461 /// DefinesPredicate - If the specified instruction defines any predicate
462 /// or condition code register(s) used for predication, returns true as well
463 /// as the definition predicate(s) by reference.
464 virtual bool DefinesPredicate(MachineInstr *MI,
465 std::vector<MachineOperand> &Pred) const {
469 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
470 /// instruction that defines the specified register class.
471 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
475 /// GetInstSize - Returns the size of the specified Instruction.
477 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
478 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
482 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
484 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
487 /// TargetInstrInfoImpl - This is the default implementation of
488 /// TargetInstrInfo, which just provides a couple of default implementations
489 /// for various methods. This separated out because it is implemented in
490 /// libcodegen, not in libtarget.
491 class TargetInstrInfoImpl : public TargetInstrInfo {
493 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
494 : TargetInstrInfo(desc, NumOpcodes) {}
496 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
497 bool NewMI = false) const;
498 virtual bool CommuteChangesDestination(MachineInstr *MI,
499 unsigned &OpIdx) const;
500 virtual bool PredicateInstruction(MachineInstr *MI,
501 const SmallVectorImpl<MachineOperand> &Pred) const;
502 virtual void reMaterialize(MachineBasicBlock &MBB,
503 MachineBasicBlock::iterator MI,
505 const MachineInstr *Orig) const;
506 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
509 /// getInstrOperandRegClass - Return register class of the operand of an
510 /// instruction of the specified TargetInstrDesc.
511 const TargetRegisterClass*
512 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
513 const TargetInstrDesc &II, unsigned Op);
515 } // End llvm namespace