1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class InstrItineraryData;
25 class MachineMemOperand;
26 class MachineRegisterInfo;
30 class ScheduleHazardRecognizer;
33 class TargetRegisterClass;
34 class TargetRegisterInfo;
35 class BranchProbability;
37 template<class T> class SmallVectorImpl;
40 //---------------------------------------------------------------------------
42 /// TargetInstrInfo - Interface to description of machine instruction set
44 class TargetInstrInfo : public MCInstrInfo {
45 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
46 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
48 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
49 : CallFrameSetupOpcode(CFSetupOpcode),
50 CallFrameDestroyOpcode(CFDestroyOpcode) {
53 virtual ~TargetInstrInfo();
55 /// getRegClass - Givem a machine instruction descriptor, returns the register
56 /// class constraint for OpNum, or NULL.
57 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
59 const TargetRegisterInfo *TRI) const;
61 /// isTriviallyReMaterializable - Return true if the instruction is trivially
62 /// rematerializable, meaning it has no side effects and requires no operands
63 /// that aren't always available.
64 bool isTriviallyReMaterializable(const MachineInstr *MI,
65 AliasAnalysis *AA = 0) const {
66 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
67 (MI->getDesc().isRematerializable() &&
68 (isReallyTriviallyReMaterializable(MI, AA) ||
69 isReallyTriviallyReMaterializableGeneric(MI, AA)));
73 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
74 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
75 /// specify whether the instruction is actually trivially rematerializable,
76 /// taking into consideration its operands. This predicate must return false
77 /// if the instruction has any side effects other than producing a value, or
78 /// if it requres any address registers that are not always available.
79 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
80 AliasAnalysis *AA) const {
85 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
86 /// for which the M_REMATERIALIZABLE flag is set and the target hook
87 /// isReallyTriviallyReMaterializable returns false, this function does
88 /// target-independent tests to determine if the instruction is really
89 /// trivially rematerializable.
90 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
91 AliasAnalysis *AA) const;
94 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
95 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
96 /// targets use pseudo instructions in order to abstract away the difference
97 /// between operating with a frame pointer and operating without, through the
98 /// use of these two instructions.
100 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
101 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
103 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
104 /// extension instruction. That is, it's like a copy where it's legal for the
105 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
106 /// true, then it's expected the pre-extension value is available as a subreg
107 /// of the result register. This also returns the sub-register index in
109 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
110 unsigned &SrcReg, unsigned &DstReg,
111 unsigned &SubIdx) const {
115 /// isLoadFromStackSlot - If the specified machine instruction is a direct
116 /// load from a stack slot, return the virtual or physical register number of
117 /// the destination along with the FrameIndex of the loaded stack slot. If
118 /// not, return 0. This predicate must return 0 if the instruction has
119 /// any side effects other than loading from the stack slot.
120 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
121 int &FrameIndex) const {
125 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
126 /// stack locations as well. This uses a heuristic so it isn't
127 /// reliable for correctness.
128 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
129 int &FrameIndex) const {
133 /// hasLoadFromStackSlot - If the specified machine instruction has
134 /// a load from a stack slot, return true along with the FrameIndex
135 /// of the loaded stack slot and the machine mem operand containing
136 /// the reference. If not, return false. Unlike
137 /// isLoadFromStackSlot, this returns true for any instructions that
138 /// loads from the stack. This is just a hint, as some cases may be
140 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
141 const MachineMemOperand *&MMO,
142 int &FrameIndex) const {
146 /// isStoreToStackSlot - If the specified machine instruction is a direct
147 /// store to a stack slot, return the virtual or physical register number of
148 /// the source reg along with the FrameIndex of the loaded stack slot. If
149 /// not, return 0. This predicate must return 0 if the instruction has
150 /// any side effects other than storing to the stack slot.
151 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
152 int &FrameIndex) const {
156 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
157 /// stack locations as well. This uses a heuristic so it isn't
158 /// reliable for correctness.
159 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
160 int &FrameIndex) const {
164 /// hasStoreToStackSlot - If the specified machine instruction has a
165 /// store to a stack slot, return true along with the FrameIndex of
166 /// the loaded stack slot and the machine mem operand containing the
167 /// reference. If not, return false. Unlike isStoreToStackSlot,
168 /// this returns true for any instructions that stores to the
169 /// stack. This is just a hint, as some cases may be missed.
170 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
171 const MachineMemOperand *&MMO,
172 int &FrameIndex) const {
176 /// reMaterialize - Re-issue the specified 'original' instruction at the
177 /// specific location targeting a new destination register.
178 /// The register in Orig->getOperand(0).getReg() will be substituted by
179 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
181 virtual void reMaterialize(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator MI,
183 unsigned DestReg, unsigned SubIdx,
184 const MachineInstr *Orig,
185 const TargetRegisterInfo &TRI) const = 0;
187 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
188 /// two-addrss instruction inserted by two-address pass.
189 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
191 const TargetRegisterInfo &TRI) const {
195 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
196 /// MachineFunction::CloneMachineInstr(), but the target may update operands
197 /// that are required to be unique.
199 /// The instruction must be duplicable as indicated by isNotDuplicable().
200 virtual MachineInstr *duplicate(MachineInstr *Orig,
201 MachineFunction &MF) const = 0;
203 /// convertToThreeAddress - This method must be implemented by targets that
204 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
205 /// may be able to convert a two-address instruction into one or more true
206 /// three-address instructions on demand. This allows the X86 target (for
207 /// example) to convert ADD and SHL instructions into LEA instructions if they
208 /// would require register copies due to two-addressness.
210 /// This method returns a null pointer if the transformation cannot be
211 /// performed, otherwise it returns the last new instruction.
213 virtual MachineInstr *
214 convertToThreeAddress(MachineFunction::iterator &MFI,
215 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
219 /// commuteInstruction - If a target has any instructions that are
220 /// commutable but require converting to different instructions or making
221 /// non-trivial changes to commute them, this method can overloaded to do
222 /// that. The default implementation simply swaps the commutable operands.
223 /// If NewMI is false, MI is modified in place and returned; otherwise, a
224 /// new machine instruction is created and returned. Do not call this
225 /// method for a non-commutable instruction, but there may be some cases
226 /// where this method fails and returns null.
227 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
228 bool NewMI = false) const = 0;
230 /// findCommutedOpIndices - If specified MI is commutable, return the two
231 /// operand indices that would swap value. Return false if the instruction
232 /// is not in a form which this routine understands.
233 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
234 unsigned &SrcOpIdx2) const = 0;
236 /// produceSameValue - Return true if two machine instructions would produce
237 /// identical values. By default, this is only true when the two instructions
238 /// are deemed identical except for defs. If this function is called when the
239 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
240 /// aggressive checks.
241 virtual bool produceSameValue(const MachineInstr *MI0,
242 const MachineInstr *MI1,
243 const MachineRegisterInfo *MRI = 0) const = 0;
245 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
246 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
247 /// implemented for a target). Upon success, this returns false and returns
248 /// with the following information in various cases:
250 /// 1. If this block ends with no branches (it just falls through to its succ)
251 /// just return false, leaving TBB/FBB null.
252 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
253 /// the destination block.
254 /// 3. If this block ends with a conditional branch and it falls through to a
255 /// successor block, it sets TBB to be the branch destination block and a
256 /// list of operands that evaluate the condition. These operands can be
257 /// passed to other TargetInstrInfo methods to create new branches.
258 /// 4. If this block ends with a conditional branch followed by an
259 /// unconditional branch, it returns the 'true' destination in TBB, the
260 /// 'false' destination in FBB, and a list of operands that evaluate the
261 /// condition. These operands can be passed to other TargetInstrInfo
262 /// methods to create new branches.
264 /// Note that RemoveBranch and InsertBranch must be implemented to support
265 /// cases where this method returns success.
267 /// If AllowModify is true, then this routine is allowed to modify the basic
268 /// block (e.g. delete instructions after the unconditional branch).
270 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
271 MachineBasicBlock *&FBB,
272 SmallVectorImpl<MachineOperand> &Cond,
273 bool AllowModify = false) const {
277 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
278 /// This is only invoked in cases where AnalyzeBranch returns success. It
279 /// returns the number of instructions that were removed.
280 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
281 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
285 /// InsertBranch - Insert branch code into the end of the specified
286 /// MachineBasicBlock. The operands to this method are the same as those
287 /// returned by AnalyzeBranch. This is only invoked in cases where
288 /// AnalyzeBranch returns success. It returns the number of instructions
291 /// It is also invoked by tail merging to add unconditional branches in
292 /// cases where AnalyzeBranch doesn't apply because there was no original
293 /// branch to analyze. At least this much must be implemented, else tail
294 /// merging needs to be disabled.
295 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
296 MachineBasicBlock *FBB,
297 const SmallVectorImpl<MachineOperand> &Cond,
299 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
303 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
304 /// after it, replacing it with an unconditional branch to NewDest. This is
305 /// used by the tail merging pass.
306 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
307 MachineBasicBlock *NewDest) const = 0;
309 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
310 /// block at the specified instruction (i.e. instruction would be the start
311 /// of a new basic block).
312 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MBBI) const {
317 /// isProfitableToIfCvt - Return true if it's profitable to predicate
318 /// instructions with accumulated instruction latency of "NumCycles"
319 /// of the specified basic block, where the probability of the instructions
320 /// being executed is given by Probability, and Confidence is a measure
321 /// of our confidence that it will be properly predicted.
323 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
324 unsigned ExtraPredCycles,
325 const BranchProbability &Probability) const {
329 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
330 /// checks for the case where two basic blocks from true and false path
331 /// of a if-then-else (diamond) are predicated on mutally exclusive
332 /// predicates, where the probability of the true path being taken is given
333 /// by Probability, and Confidence is a measure of our confidence that it
334 /// will be properly predicted.
336 isProfitableToIfCvt(MachineBasicBlock &TMBB,
337 unsigned NumTCycles, unsigned ExtraTCycles,
338 MachineBasicBlock &FMBB,
339 unsigned NumFCycles, unsigned ExtraFCycles,
340 const BranchProbability &Probability) const {
344 /// isProfitableToDupForIfCvt - Return true if it's profitable for
345 /// if-converter to duplicate instructions of specified accumulated
346 /// instruction latencies in the specified MBB to enable if-conversion.
347 /// The probability of the instructions being executed is given by
348 /// Probability, and Confidence is a measure of our confidence that it
349 /// will be properly predicted.
351 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
352 const BranchProbability &Probability) const {
356 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
357 virtual void copyPhysReg(MachineBasicBlock &MBB,
358 MachineBasicBlock::iterator MI, DebugLoc DL,
359 unsigned DestReg, unsigned SrcReg,
360 bool KillSrc) const {
361 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
364 /// storeRegToStackSlot - Store the specified register of the given register
365 /// class to the specified stack frame index. The store instruction is to be
366 /// added to the given machine basic block before the specified machine
367 /// instruction. If isKill is true, the register operand is the last use and
368 /// must be marked kill.
369 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
370 MachineBasicBlock::iterator MI,
371 unsigned SrcReg, bool isKill, int FrameIndex,
372 const TargetRegisterClass *RC,
373 const TargetRegisterInfo *TRI) const {
374 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
377 /// loadRegFromStackSlot - Load the specified register of the given register
378 /// class from the specified stack frame index. The load instruction is to be
379 /// added to the given machine basic block before the specified machine
381 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
382 MachineBasicBlock::iterator MI,
383 unsigned DestReg, int FrameIndex,
384 const TargetRegisterClass *RC,
385 const TargetRegisterInfo *TRI) const {
386 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
389 /// expandPostRAPseudo - This function is called for all pseudo instructions
390 /// that remain after register allocation. Many pseudo instructions are
391 /// created to help register allocation. This is the place to convert them
392 /// into real instructions. The target can edit MI in place, or it can insert
393 /// new instructions and erase MI. The function should return true if
394 /// anything was changed.
395 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
399 /// emitFrameIndexDebugValue - Emit a target-dependent form of
400 /// DBG_VALUE encoding the address of a frame index. Addresses would
401 /// normally be lowered the same way as other addresses on the target,
402 /// e.g. in load instructions. For targets that do not support this
403 /// the debug info is simply lost.
404 /// If you add this for a target you should handle this DBG_VALUE in the
405 /// target-specific AsmPrinter code as well; you will probably get invalid
406 /// assembly output if you don't.
407 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
415 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
416 /// slot into the specified machine instruction for the specified operand(s).
417 /// If this is possible, a new instruction is returned with the specified
418 /// operand folded, otherwise NULL is returned.
419 /// The new instruction is inserted before MI, and the client is responsible
420 /// for removing the old instruction.
421 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
422 const SmallVectorImpl<unsigned> &Ops,
423 int FrameIndex) const;
425 /// foldMemoryOperand - Same as the previous version except it allows folding
426 /// of any load and store from / to any address, not just from a specific
428 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
429 const SmallVectorImpl<unsigned> &Ops,
430 MachineInstr* LoadMI) const;
433 /// foldMemoryOperandImpl - Target-dependent implementation for
434 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
435 /// take care of adding a MachineMemOperand to the newly created instruction.
436 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
438 const SmallVectorImpl<unsigned> &Ops,
439 int FrameIndex) const {
443 /// foldMemoryOperandImpl - Target-dependent implementation for
444 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
445 /// take care of adding a MachineMemOperand to the newly created instruction.
446 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
448 const SmallVectorImpl<unsigned> &Ops,
449 MachineInstr* LoadMI) const {
454 /// canFoldMemoryOperand - Returns true for the specified load / store if
455 /// folding is possible.
457 bool canFoldMemoryOperand(const MachineInstr *MI,
458 const SmallVectorImpl<unsigned> &Ops) const =0;
460 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
461 /// a store or a load and a store into two or more instruction. If this is
462 /// possible, returns true as well as the new instructions by reference.
463 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
464 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
465 SmallVectorImpl<MachineInstr*> &NewMIs) const{
469 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
470 SmallVectorImpl<SDNode*> &NewNodes) const {
474 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
475 /// instruction after load / store are unfolded from an instruction of the
476 /// specified opcode. It returns zero if the specified unfolding is not
477 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
478 /// index of the operand which will hold the register holding the loaded
480 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
481 bool UnfoldLoad, bool UnfoldStore,
482 unsigned *LoadRegIndex = 0) const {
486 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
487 /// to determine if two loads are loading from the same base address. It
488 /// should only return true if the base pointers are the same and the
489 /// only differences between the two addresses are the offset. It also returns
490 /// the offsets by reference.
491 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
492 int64_t &Offset1, int64_t &Offset2) const {
496 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
497 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
498 /// be scheduled togther. On some targets if two loads are loading from
499 /// addresses in the same cache line, it's better if they are scheduled
500 /// together. This function takes two integers that represent the load offsets
501 /// from the common base address. It returns true if it decides it's desirable
502 /// to schedule the two loads together. "NumLoads" is the number of loads that
503 /// have already been scheduled after Load1.
504 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
505 int64_t Offset1, int64_t Offset2,
506 unsigned NumLoads) const {
510 /// ReverseBranchCondition - Reverses the branch condition of the specified
511 /// condition list, returning false on success and true if it cannot be
514 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
518 /// insertNoop - Insert a noop into the instruction stream at the specified
520 virtual void insertNoop(MachineBasicBlock &MBB,
521 MachineBasicBlock::iterator MI) const;
524 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
525 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
526 // Default to just using 'nop' string.
530 /// isPredicated - Returns true if the instruction is already predicated.
532 virtual bool isPredicated(const MachineInstr *MI) const {
536 /// isUnpredicatedTerminator - Returns true if the instruction is a
537 /// terminator instruction that has not been predicated.
538 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const = 0;
540 /// PredicateInstruction - Convert the instruction into a predicated
541 /// instruction. It returns true if the operation was successful.
543 bool PredicateInstruction(MachineInstr *MI,
544 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
546 /// SubsumesPredicate - Returns true if the first specified predicate
547 /// subsumes the second, e.g. GE subsumes GT.
549 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
550 const SmallVectorImpl<MachineOperand> &Pred2) const {
554 /// DefinesPredicate - If the specified instruction defines any predicate
555 /// or condition code register(s) used for predication, returns true as well
556 /// as the definition predicate(s) by reference.
557 virtual bool DefinesPredicate(MachineInstr *MI,
558 std::vector<MachineOperand> &Pred) const {
562 /// isPredicable - Return true if the specified instruction can be predicated.
563 /// By default, this returns true for every instruction with a
564 /// PredicateOperand.
565 virtual bool isPredicable(MachineInstr *MI) const {
566 return MI->getDesc().isPredicable();
569 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
570 /// instruction that defines the specified register class.
571 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
575 /// isSchedulingBoundary - Test if the given instruction should be
576 /// considered a scheduling boundary. This primarily includes labels and
578 virtual bool isSchedulingBoundary(const MachineInstr *MI,
579 const MachineBasicBlock *MBB,
580 const MachineFunction &MF) const = 0;
582 /// Measure the specified inline asm to determine an approximation of its
584 virtual unsigned getInlineAsmLength(const char *Str,
585 const MCAsmInfo &MAI) const;
587 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
588 /// use for this target when scheduling the machine instructions before
589 /// register allocation.
590 virtual ScheduleHazardRecognizer*
591 CreateTargetHazardRecognizer(const TargetMachine *TM,
592 const ScheduleDAG *DAG) const = 0;
594 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
595 /// recognizer to use for this target when scheduling the machine instructions
596 /// after register allocation.
597 virtual ScheduleHazardRecognizer*
598 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
599 const ScheduleDAG *DAG) const = 0;
601 /// AnalyzeCompare - For a comparison instruction, return the source register
602 /// in SrcReg and the value it compares against in CmpValue. Return true if
603 /// the comparison instruction can be analyzed.
604 virtual bool AnalyzeCompare(const MachineInstr *MI,
605 unsigned &SrcReg, int &Mask, int &Value) const {
609 /// OptimizeCompareInstr - See if the comparison instruction can be converted
610 /// into something more efficient. E.g., on ARM most instructions can set the
611 /// flags register, obviating the need for a separate CMP.
612 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
613 unsigned SrcReg, int Mask, int Value,
614 const MachineRegisterInfo *MRI) const {
618 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
619 /// instruction, try to fold the immediate into the use instruction.
620 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
621 unsigned Reg, MachineRegisterInfo *MRI) const {
625 /// getNumMicroOps - Return the number of u-operations the given machine
626 /// instruction will be decoded to on the target cpu.
627 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
628 const MachineInstr *MI) const;
630 /// isZeroCost - Return true for pseudo instructions that don't consume any
631 /// machine resources in their current form. These are common cases that the
632 /// scheduler should consider free, rather than conservatively handling them
633 /// as instructions with no itinerary.
634 bool isZeroCost(unsigned Opcode) const {
635 return Opcode <= TargetOpcode::COPY;
638 /// getOperandLatency - Compute and return the use operand latency of a given
639 /// pair of def and use.
640 /// In most cases, the static scheduling itinerary was enough to determine the
641 /// operand latency. But it may not be possible for instructions with variable
642 /// number of defs / uses.
643 virtual int getOperandLatency(const InstrItineraryData *ItinData,
644 const MachineInstr *DefMI, unsigned DefIdx,
645 const MachineInstr *UseMI, unsigned UseIdx) const;
647 virtual int getOperandLatency(const InstrItineraryData *ItinData,
648 SDNode *DefNode, unsigned DefIdx,
649 SDNode *UseNode, unsigned UseIdx) const = 0;
651 /// getOutputLatency - Compute and return the output dependency latency of a
652 /// a given pair of defs which both target the same register. This is usually
654 virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
655 const MachineInstr *DefMI, unsigned DefIdx,
656 const MachineInstr *DepMI) const {
660 /// getInstrLatency - Compute the instruction latency of a given instruction.
661 /// If the instruction has higher cost when predicated, it's returned via
663 virtual int getInstrLatency(const InstrItineraryData *ItinData,
664 const MachineInstr *MI,
665 unsigned *PredCost = 0) const;
667 virtual int getInstrLatency(const InstrItineraryData *ItinData,
668 SDNode *Node) const = 0;
670 /// isHighLatencyDef - Return true if this opcode has high latency to its
672 virtual bool isHighLatencyDef(int opc) const { return false; }
674 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
675 /// and an use in the current loop, return true if the target considered
676 /// it 'high'. This is used by optimization passes such as machine LICM to
677 /// determine whether it makes sense to hoist an instruction out even in
678 /// high register pressure situation.
680 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
681 const MachineRegisterInfo *MRI,
682 const MachineInstr *DefMI, unsigned DefIdx,
683 const MachineInstr *UseMI, unsigned UseIdx) const {
687 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
688 /// if the target considered it 'low'.
690 bool hasLowDefLatency(const InstrItineraryData *ItinData,
691 const MachineInstr *DefMI, unsigned DefIdx) const;
693 /// verifyInstruction - Perform target specific instruction verification.
695 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
699 /// getExecutionDomain - Return the current execution domain and bit mask of
700 /// possible domains for instruction.
702 /// Some micro-architectures have multiple execution domains, and multiple
703 /// opcodes that perform the same operation in different domains. For
704 /// example, the x86 architecture provides the por, orps, and orpd
705 /// instructions that all do the same thing. There is a latency penalty if a
706 /// register is written in one domain and read in another.
708 /// This function returns a pair (domain, mask) containing the execution
709 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
710 /// function can be used to change the opcode to one of the domains in the
711 /// bit mask. Instructions whose execution domain can't be changed should
714 /// The execution domain numbers don't have any special meaning except domain
715 /// 0 is used for instructions that are not associated with any interesting
716 /// execution domain.
718 virtual std::pair<uint16_t, uint16_t>
719 getExecutionDomain(const MachineInstr *MI) const {
720 return std::make_pair(0, 0);
723 /// setExecutionDomain - Change the opcode of MI to execute in Domain.
725 /// The bit (1 << Domain) must be set in the mask returned from
726 /// getExecutionDomain(MI).
728 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
731 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance
732 /// before an instruction with an unwanted partial register update.
734 /// Some instructions only write part of a register, and implicitly need to
735 /// read the other parts of the register. This may cause unwanted stalls
736 /// preventing otherwise unrelated instructions from executing in parallel in
737 /// an out-of-order CPU.
739 /// For example, the x86 instruction cvtsi2ss writes its result to bits
740 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
741 /// the instruction needs to wait for the old value of the register to become
744 /// addps %xmm1, %xmm0
745 /// movaps %xmm0, (%rax)
746 /// cvtsi2ss %rbx, %xmm0
748 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
749 /// instruction before it can issue, even though the high bits of %xmm0
750 /// probably aren't needed.
752 /// This hook returns the preferred clearance before MI, measured in
753 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
754 /// instructions before MI. It should only return a positive value for
755 /// unwanted dependencies. If the old bits of the defined register have
756 /// useful values, or if MI is determined to otherwise read the dependency,
757 /// the hook should return 0.
759 /// The unwanted dependency may be handled by:
761 /// 1. Allocating the same register for an MI def and use. That makes the
762 /// unwanted dependency identical to a required dependency.
764 /// 2. Allocating a register for the def that has no defs in the previous N
767 /// 3. Calling breakPartialRegDependency() with the same arguments. This
768 /// allows the target to insert a dependency breaking instruction.
771 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
772 const TargetRegisterInfo *TRI) const {
773 // The default implementation returns 0 for no partial register dependency.
777 /// breakPartialRegDependency - Insert a dependency-breaking instruction
778 /// before MI to eliminate an unwanted dependency on OpNum.
780 /// If it wasn't possible to avoid a def in the last N instructions before MI
781 /// (see getPartialRegUpdateClearance), this hook will be called to break the
782 /// unwanted dependency.
784 /// On x86, an xorps instruction can be used as a dependency breaker:
786 /// addps %xmm1, %xmm0
787 /// movaps %xmm0, (%rax)
788 /// xorps %xmm0, %xmm0
789 /// cvtsi2ss %rbx, %xmm0
791 /// An <imp-kill> operand should be added to MI if an instruction was
792 /// inserted. This ties the instructions together in the post-ra scheduler.
795 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
796 const TargetRegisterInfo *TRI) const {}
799 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
802 /// TargetInstrInfoImpl - This is the default implementation of
803 /// TargetInstrInfo, which just provides a couple of default implementations
804 /// for various methods. This separated out because it is implemented in
805 /// libcodegen, not in libtarget.
806 class TargetInstrInfoImpl : public TargetInstrInfo {
808 TargetInstrInfoImpl(int CallFrameSetupOpcode = -1,
809 int CallFrameDestroyOpcode = -1)
810 : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
812 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
813 MachineBasicBlock *NewDest) const;
814 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
815 bool NewMI = false) const;
816 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
817 unsigned &SrcOpIdx2) const;
818 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
819 const SmallVectorImpl<unsigned> &Ops) const;
820 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
821 const MachineMemOperand *&MMO,
822 int &FrameIndex) const;
823 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
824 const MachineMemOperand *&MMO,
825 int &FrameIndex) const;
826 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
827 virtual bool PredicateInstruction(MachineInstr *MI,
828 const SmallVectorImpl<MachineOperand> &Pred) const;
829 virtual void reMaterialize(MachineBasicBlock &MBB,
830 MachineBasicBlock::iterator MI,
831 unsigned DestReg, unsigned SubReg,
832 const MachineInstr *Orig,
833 const TargetRegisterInfo &TRI) const;
834 virtual MachineInstr *duplicate(MachineInstr *Orig,
835 MachineFunction &MF) const;
836 virtual bool produceSameValue(const MachineInstr *MI0,
837 const MachineInstr *MI1,
838 const MachineRegisterInfo *MRI) const;
839 virtual bool isSchedulingBoundary(const MachineInstr *MI,
840 const MachineBasicBlock *MBB,
841 const MachineFunction &MF) const;
842 using TargetInstrInfo::getOperandLatency;
843 virtual int getOperandLatency(const InstrItineraryData *ItinData,
844 SDNode *DefNode, unsigned DefIdx,
845 SDNode *UseNode, unsigned UseIdx) const;
846 using TargetInstrInfo::getInstrLatency;
847 virtual int getInstrLatency(const InstrItineraryData *ItinData,
850 bool usePreRAHazardRecognizer() const;
852 virtual ScheduleHazardRecognizer *
853 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const;
855 virtual ScheduleHazardRecognizer *
856 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
857 const ScheduleDAG*) const;
860 } // End llvm namespace