1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/CodeGen/DFAPacketizer.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/MC/MCInstrInfo.h"
24 class InstrItineraryData;
27 class MachineMemOperand;
28 class MachineRegisterInfo;
33 class ScheduleHazardRecognizer;
36 class TargetRegisterClass;
37 class TargetRegisterInfo;
38 class BranchProbability;
40 template<class T> class SmallVectorImpl;
43 //---------------------------------------------------------------------------
45 /// TargetInstrInfo - Interface to description of machine instruction set
47 class TargetInstrInfo : public MCInstrInfo {
48 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
49 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
51 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
52 : CallFrameSetupOpcode(CFSetupOpcode),
53 CallFrameDestroyOpcode(CFDestroyOpcode) {
56 virtual ~TargetInstrInfo();
58 /// getRegClass - Givem a machine instruction descriptor, returns the register
59 /// class constraint for OpNum, or NULL.
60 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
62 const TargetRegisterInfo *TRI,
63 const MachineFunction &MF) const;
65 /// isTriviallyReMaterializable - Return true if the instruction is trivially
66 /// rematerializable, meaning it has no side effects and requires no operands
67 /// that aren't always available.
68 bool isTriviallyReMaterializable(const MachineInstr *MI,
69 AliasAnalysis *AA = 0) const {
70 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
71 (MI->getDesc().isRematerializable() &&
72 (isReallyTriviallyReMaterializable(MI, AA) ||
73 isReallyTriviallyReMaterializableGeneric(MI, AA)));
77 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
78 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
79 /// specify whether the instruction is actually trivially rematerializable,
80 /// taking into consideration its operands. This predicate must return false
81 /// if the instruction has any side effects other than producing a value, or
82 /// if it requres any address registers that are not always available.
83 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
84 AliasAnalysis *AA) const {
89 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
90 /// for which the M_REMATERIALIZABLE flag is set and the target hook
91 /// isReallyTriviallyReMaterializable returns false, this function does
92 /// target-independent tests to determine if the instruction is really
93 /// trivially rematerializable.
94 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
95 AliasAnalysis *AA) const;
98 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
99 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
100 /// targets use pseudo instructions in order to abstract away the difference
101 /// between operating with a frame pointer and operating without, through the
102 /// use of these two instructions.
104 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
105 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
107 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
108 /// extension instruction. That is, it's like a copy where it's legal for the
109 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
110 /// true, then it's expected the pre-extension value is available as a subreg
111 /// of the result register. This also returns the sub-register index in
113 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
114 unsigned &SrcReg, unsigned &DstReg,
115 unsigned &SubIdx) const {
119 /// isLoadFromStackSlot - If the specified machine instruction is a direct
120 /// load from a stack slot, return the virtual or physical register number of
121 /// the destination along with the FrameIndex of the loaded stack slot. If
122 /// not, return 0. This predicate must return 0 if the instruction has
123 /// any side effects other than loading from the stack slot.
124 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
125 int &FrameIndex) const {
129 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
130 /// stack locations as well. This uses a heuristic so it isn't
131 /// reliable for correctness.
132 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
133 int &FrameIndex) const {
137 /// hasLoadFromStackSlot - If the specified machine instruction has
138 /// a load from a stack slot, return true along with the FrameIndex
139 /// of the loaded stack slot and the machine mem operand containing
140 /// the reference. If not, return false. Unlike
141 /// isLoadFromStackSlot, this returns true for any instructions that
142 /// loads from the stack. This is just a hint, as some cases may be
144 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
145 const MachineMemOperand *&MMO,
146 int &FrameIndex) const;
148 /// isStoreToStackSlot - If the specified machine instruction is a direct
149 /// store to a stack slot, return the virtual or physical register number of
150 /// the source reg along with the FrameIndex of the loaded stack slot. If
151 /// not, return 0. This predicate must return 0 if the instruction has
152 /// any side effects other than storing to the stack slot.
153 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
154 int &FrameIndex) const {
158 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
159 /// stack locations as well. This uses a heuristic so it isn't
160 /// reliable for correctness.
161 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
162 int &FrameIndex) const {
166 /// hasStoreToStackSlot - If the specified machine instruction has a
167 /// store to a stack slot, return true along with the FrameIndex of
168 /// the loaded stack slot and the machine mem operand containing the
169 /// reference. If not, return false. Unlike isStoreToStackSlot,
170 /// this returns true for any instructions that stores to the
171 /// stack. This is just a hint, as some cases may be missed.
172 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
173 const MachineMemOperand *&MMO,
174 int &FrameIndex) const;
176 /// isStackSlotCopy - Return true if the specified machine instruction
177 /// is a copy of one stack slot to another and has no other effect.
178 /// Provide the identity of the two frame indices.
179 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
180 int &SrcFrameIndex) const {
184 /// reMaterialize - Re-issue the specified 'original' instruction at the
185 /// specific location targeting a new destination register.
186 /// The register in Orig->getOperand(0).getReg() will be substituted by
187 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
189 virtual void reMaterialize(MachineBasicBlock &MBB,
190 MachineBasicBlock::iterator MI,
191 unsigned DestReg, unsigned SubIdx,
192 const MachineInstr *Orig,
193 const TargetRegisterInfo &TRI) const;
195 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
196 /// MachineFunction::CloneMachineInstr(), but the target may update operands
197 /// that are required to be unique.
199 /// The instruction must be duplicable as indicated by isNotDuplicable().
200 virtual MachineInstr *duplicate(MachineInstr *Orig,
201 MachineFunction &MF) const;
203 /// convertToThreeAddress - This method must be implemented by targets that
204 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
205 /// may be able to convert a two-address instruction into one or more true
206 /// three-address instructions on demand. This allows the X86 target (for
207 /// example) to convert ADD and SHL instructions into LEA instructions if they
208 /// would require register copies due to two-addressness.
210 /// This method returns a null pointer if the transformation cannot be
211 /// performed, otherwise it returns the last new instruction.
213 virtual MachineInstr *
214 convertToThreeAddress(MachineFunction::iterator &MFI,
215 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
219 /// commuteInstruction - If a target has any instructions that are
220 /// commutable but require converting to different instructions or making
221 /// non-trivial changes to commute them, this method can overloaded to do
222 /// that. The default implementation simply swaps the commutable operands.
223 /// If NewMI is false, MI is modified in place and returned; otherwise, a
224 /// new machine instruction is created and returned. Do not call this
225 /// method for a non-commutable instruction, but there may be some cases
226 /// where this method fails and returns null.
227 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
228 bool NewMI = false) const;
230 /// findCommutedOpIndices - If specified MI is commutable, return the two
231 /// operand indices that would swap value. Return false if the instruction
232 /// is not in a form which this routine understands.
233 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
234 unsigned &SrcOpIdx2) const;
236 /// produceSameValue - Return true if two machine instructions would produce
237 /// identical values. By default, this is only true when the two instructions
238 /// are deemed identical except for defs. If this function is called when the
239 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
240 /// aggressive checks.
241 virtual bool produceSameValue(const MachineInstr *MI0,
242 const MachineInstr *MI1,
243 const MachineRegisterInfo *MRI = 0) const;
245 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
246 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
247 /// implemented for a target). Upon success, this returns false and returns
248 /// with the following information in various cases:
250 /// 1. If this block ends with no branches (it just falls through to its succ)
251 /// just return false, leaving TBB/FBB null.
252 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
253 /// the destination block.
254 /// 3. If this block ends with a conditional branch and it falls through to a
255 /// successor block, it sets TBB to be the branch destination block and a
256 /// list of operands that evaluate the condition. These operands can be
257 /// passed to other TargetInstrInfo methods to create new branches.
258 /// 4. If this block ends with a conditional branch followed by an
259 /// unconditional branch, it returns the 'true' destination in TBB, the
260 /// 'false' destination in FBB, and a list of operands that evaluate the
261 /// condition. These operands can be passed to other TargetInstrInfo
262 /// methods to create new branches.
264 /// Note that RemoveBranch and InsertBranch must be implemented to support
265 /// cases where this method returns success.
267 /// If AllowModify is true, then this routine is allowed to modify the basic
268 /// block (e.g. delete instructions after the unconditional branch).
270 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
271 MachineBasicBlock *&FBB,
272 SmallVectorImpl<MachineOperand> &Cond,
273 bool AllowModify = false) const {
277 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
278 /// This is only invoked in cases where AnalyzeBranch returns success. It
279 /// returns the number of instructions that were removed.
280 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
281 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
284 /// InsertBranch - Insert branch code into the end of the specified
285 /// MachineBasicBlock. The operands to this method are the same as those
286 /// returned by AnalyzeBranch. This is only invoked in cases where
287 /// AnalyzeBranch returns success. It returns the number of instructions
290 /// It is also invoked by tail merging to add unconditional branches in
291 /// cases where AnalyzeBranch doesn't apply because there was no original
292 /// branch to analyze. At least this much must be implemented, else tail
293 /// merging needs to be disabled.
294 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
295 MachineBasicBlock *FBB,
296 const SmallVectorImpl<MachineOperand> &Cond,
298 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
301 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
302 /// after it, replacing it with an unconditional branch to NewDest. This is
303 /// used by the tail merging pass.
304 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
305 MachineBasicBlock *NewDest) const;
307 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
308 /// block at the specified instruction (i.e. instruction would be the start
309 /// of a new basic block).
310 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator MBBI) const {
315 /// isProfitableToIfCvt - Return true if it's profitable to predicate
316 /// instructions with accumulated instruction latency of "NumCycles"
317 /// of the specified basic block, where the probability of the instructions
318 /// being executed is given by Probability, and Confidence is a measure
319 /// of our confidence that it will be properly predicted.
321 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
322 unsigned ExtraPredCycles,
323 const BranchProbability &Probability) const {
327 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
328 /// checks for the case where two basic blocks from true and false path
329 /// of a if-then-else (diamond) are predicated on mutally exclusive
330 /// predicates, where the probability of the true path being taken is given
331 /// by Probability, and Confidence is a measure of our confidence that it
332 /// will be properly predicted.
334 isProfitableToIfCvt(MachineBasicBlock &TMBB,
335 unsigned NumTCycles, unsigned ExtraTCycles,
336 MachineBasicBlock &FMBB,
337 unsigned NumFCycles, unsigned ExtraFCycles,
338 const BranchProbability &Probability) const {
342 /// isProfitableToDupForIfCvt - Return true if it's profitable for
343 /// if-converter to duplicate instructions of specified accumulated
344 /// instruction latencies in the specified MBB to enable if-conversion.
345 /// The probability of the instructions being executed is given by
346 /// Probability, and Confidence is a measure of our confidence that it
347 /// will be properly predicted.
349 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
350 const BranchProbability &Probability) const {
354 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate
355 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
356 /// exclusive predicates.
364 /// This may be profitable is conditional instructions are always executed.
365 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
366 MachineBasicBlock &FMBB) const {
370 /// canInsertSelect - Return true if it is possible to insert a select
371 /// instruction that chooses between TrueReg and FalseReg based on the
372 /// condition code in Cond.
374 /// When successful, also return the latency in cycles from TrueReg,
375 /// FalseReg, and Cond to the destination register. In most cases, a select
376 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
378 /// Some x86 implementations have 2-cycle cmov instructions.
380 /// @param MBB Block where select instruction would be inserted.
381 /// @param Cond Condition returned by AnalyzeBranch.
382 /// @param TrueReg Virtual register to select when Cond is true.
383 /// @param FalseReg Virtual register to select when Cond is false.
384 /// @param CondCycles Latency from Cond+Branch to select output.
385 /// @param TrueCycles Latency from TrueReg to select output.
386 /// @param FalseCycles Latency from FalseReg to select output.
387 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
388 const SmallVectorImpl<MachineOperand> &Cond,
389 unsigned TrueReg, unsigned FalseReg,
391 int &TrueCycles, int &FalseCycles) const {
395 /// insertSelect - Insert a select instruction into MBB before I that will
396 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
399 /// This function can only be called after canInsertSelect() returned true.
400 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
401 /// that the same flags or registers required by Cond are available at the
404 /// @param MBB Block where select instruction should be inserted.
405 /// @param I Insertion point.
406 /// @param DL Source location for debugging.
407 /// @param DstReg Virtual register to be defined by select instruction.
408 /// @param Cond Condition as computed by AnalyzeBranch.
409 /// @param TrueReg Virtual register to copy when Cond is true.
410 /// @param FalseReg Virtual register to copy when Cons is false.
411 virtual void insertSelect(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I, DebugLoc DL,
414 const SmallVectorImpl<MachineOperand> &Cond,
415 unsigned TrueReg, unsigned FalseReg) const {
416 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
419 /// analyzeSelect - Analyze the given select instruction, returning true if
420 /// it cannot be understood. It is assumed that MI->isSelect() is true.
422 /// When successful, return the controlling condition and the operands that
423 /// determine the true and false result values.
425 /// Result = SELECT Cond, TrueOp, FalseOp
427 /// Some targets can optimize select instructions, for example by predicating
428 /// the instruction defining one of the operands. Such targets should set
431 /// @param MI Select instruction to analyze.
432 /// @param Cond Condition controlling the select.
433 /// @param TrueOp Operand number of the value selected when Cond is true.
434 /// @param FalseOp Operand number of the value selected when Cond is false.
435 /// @param Optimizable Returned as true if MI is optimizable.
436 /// @returns False on success.
437 virtual bool analyzeSelect(const MachineInstr *MI,
438 SmallVectorImpl<MachineOperand> &Cond,
439 unsigned &TrueOp, unsigned &FalseOp,
440 bool &Optimizable) const {
441 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
445 /// optimizeSelect - Given a select instruction that was understood by
446 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
447 /// merging it with one of its operands. Returns NULL on failure.
449 /// When successful, returns the new select instruction. The client is
450 /// responsible for deleting MI.
452 /// If both sides of the select can be optimized, PreferFalse is used to pick
455 /// @param MI Optimizable select instruction.
456 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
457 /// @returns Optimized instruction or NULL.
458 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
459 bool PreferFalse = false) const {
460 // This function must be implemented if Optimizable is ever set.
461 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
464 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
466 /// This function should support copies within any legal register class as
467 /// well as any cross-class copies created during instruction selection.
469 /// The source and destination registers may overlap, which may require a
470 /// careful implementation when multiple copy instructions are required for
471 /// large registers. See for example the ARM target.
472 virtual void copyPhysReg(MachineBasicBlock &MBB,
473 MachineBasicBlock::iterator MI, DebugLoc DL,
474 unsigned DestReg, unsigned SrcReg,
475 bool KillSrc) const {
476 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
479 /// storeRegToStackSlot - Store the specified register of the given register
480 /// class to the specified stack frame index. The store instruction is to be
481 /// added to the given machine basic block before the specified machine
482 /// instruction. If isKill is true, the register operand is the last use and
483 /// must be marked kill.
484 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
485 MachineBasicBlock::iterator MI,
486 unsigned SrcReg, bool isKill, int FrameIndex,
487 const TargetRegisterClass *RC,
488 const TargetRegisterInfo *TRI) const {
489 llvm_unreachable("Target didn't implement "
490 "TargetInstrInfo::storeRegToStackSlot!");
493 /// loadRegFromStackSlot - Load the specified register of the given register
494 /// class from the specified stack frame index. The load instruction is to be
495 /// added to the given machine basic block before the specified machine
497 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
498 MachineBasicBlock::iterator MI,
499 unsigned DestReg, int FrameIndex,
500 const TargetRegisterClass *RC,
501 const TargetRegisterInfo *TRI) const {
502 llvm_unreachable("Target didn't implement "
503 "TargetInstrInfo::loadRegFromStackSlot!");
506 /// expandPostRAPseudo - This function is called for all pseudo instructions
507 /// that remain after register allocation. Many pseudo instructions are
508 /// created to help register allocation. This is the place to convert them
509 /// into real instructions. The target can edit MI in place, or it can insert
510 /// new instructions and erase MI. The function should return true if
511 /// anything was changed.
512 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
516 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
517 /// slot into the specified machine instruction for the specified operand(s).
518 /// If this is possible, a new instruction is returned with the specified
519 /// operand folded, otherwise NULL is returned.
520 /// The new instruction is inserted before MI, and the client is responsible
521 /// for removing the old instruction.
522 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
523 const SmallVectorImpl<unsigned> &Ops,
524 int FrameIndex) const;
526 /// foldMemoryOperand - Same as the previous version except it allows folding
527 /// of any load and store from / to any address, not just from a specific
529 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
530 const SmallVectorImpl<unsigned> &Ops,
531 MachineInstr* LoadMI) const;
534 /// foldMemoryOperandImpl - Target-dependent implementation for
535 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
536 /// take care of adding a MachineMemOperand to the newly created instruction.
537 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
539 const SmallVectorImpl<unsigned> &Ops,
540 int FrameIndex) const {
544 /// foldMemoryOperandImpl - Target-dependent implementation for
545 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
546 /// take care of adding a MachineMemOperand to the newly created instruction.
547 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
549 const SmallVectorImpl<unsigned> &Ops,
550 MachineInstr* LoadMI) const {
555 /// canFoldMemoryOperand - Returns true for the specified load / store if
556 /// folding is possible.
558 bool canFoldMemoryOperand(const MachineInstr *MI,
559 const SmallVectorImpl<unsigned> &Ops) const;
561 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
562 /// a store or a load and a store into two or more instruction. If this is
563 /// possible, returns true as well as the new instructions by reference.
564 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
565 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
566 SmallVectorImpl<MachineInstr*> &NewMIs) const{
570 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
571 SmallVectorImpl<SDNode*> &NewNodes) const {
575 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
576 /// instruction after load / store are unfolded from an instruction of the
577 /// specified opcode. It returns zero if the specified unfolding is not
578 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
579 /// index of the operand which will hold the register holding the loaded
581 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
582 bool UnfoldLoad, bool UnfoldStore,
583 unsigned *LoadRegIndex = 0) const {
587 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
588 /// to determine if two loads are loading from the same base address. It
589 /// should only return true if the base pointers are the same and the
590 /// only differences between the two addresses are the offset. It also returns
591 /// the offsets by reference.
592 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
593 int64_t &Offset1, int64_t &Offset2) const {
597 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
598 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
599 /// be scheduled togther. On some targets if two loads are loading from
600 /// addresses in the same cache line, it's better if they are scheduled
601 /// together. This function takes two integers that represent the load offsets
602 /// from the common base address. It returns true if it decides it's desirable
603 /// to schedule the two loads together. "NumLoads" is the number of loads that
604 /// have already been scheduled after Load1.
605 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
606 int64_t Offset1, int64_t Offset2,
607 unsigned NumLoads) const {
611 /// \brief Get the base register and byte offset of a load/store instr.
612 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
613 unsigned &BaseReg, unsigned &Offset,
614 const TargetRegisterInfo *TRI) const {
618 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
619 MachineInstr *SecondLdSt,
620 unsigned NumLoads) const {
624 /// \brief Can this target fuse the given instructions if they are scheduled
626 virtual bool shouldScheduleAdjacent(MachineInstr* First,
627 MachineInstr *Second) const {
631 /// ReverseBranchCondition - Reverses the branch condition of the specified
632 /// condition list, returning false on success and true if it cannot be
635 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
639 /// insertNoop - Insert a noop into the instruction stream at the specified
641 virtual void insertNoop(MachineBasicBlock &MBB,
642 MachineBasicBlock::iterator MI) const;
645 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
646 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
647 // Default to just using 'nop' string.
651 /// isPredicated - Returns true if the instruction is already predicated.
653 virtual bool isPredicated(const MachineInstr *MI) const {
657 /// isUnpredicatedTerminator - Returns true if the instruction is a
658 /// terminator instruction that has not been predicated.
659 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
661 /// PredicateInstruction - Convert the instruction into a predicated
662 /// instruction. It returns true if the operation was successful.
664 bool PredicateInstruction(MachineInstr *MI,
665 const SmallVectorImpl<MachineOperand> &Pred) const;
667 /// SubsumesPredicate - Returns true if the first specified predicate
668 /// subsumes the second, e.g. GE subsumes GT.
670 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
671 const SmallVectorImpl<MachineOperand> &Pred2) const {
675 /// DefinesPredicate - If the specified instruction defines any predicate
676 /// or condition code register(s) used for predication, returns true as well
677 /// as the definition predicate(s) by reference.
678 virtual bool DefinesPredicate(MachineInstr *MI,
679 std::vector<MachineOperand> &Pred) const {
683 /// isPredicable - Return true if the specified instruction can be predicated.
684 /// By default, this returns true for every instruction with a
685 /// PredicateOperand.
686 virtual bool isPredicable(MachineInstr *MI) const {
687 return MI->getDesc().isPredicable();
690 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
691 /// instruction that defines the specified register class.
692 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
696 /// isSchedulingBoundary - Test if the given instruction should be
697 /// considered a scheduling boundary. This primarily includes labels and
699 virtual bool isSchedulingBoundary(const MachineInstr *MI,
700 const MachineBasicBlock *MBB,
701 const MachineFunction &MF) const;
703 /// Measure the specified inline asm to determine an approximation of its
705 virtual unsigned getInlineAsmLength(const char *Str,
706 const MCAsmInfo &MAI) const;
708 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
709 /// use for this target when scheduling the machine instructions before
710 /// register allocation.
711 virtual ScheduleHazardRecognizer*
712 CreateTargetHazardRecognizer(const TargetMachine *TM,
713 const ScheduleDAG *DAG) const;
715 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer
716 /// to use for this target when scheduling the machine instructions before
717 /// register allocation.
718 virtual ScheduleHazardRecognizer*
719 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
720 const ScheduleDAG *DAG) const;
722 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
723 /// recognizer to use for this target when scheduling the machine instructions
724 /// after register allocation.
725 virtual ScheduleHazardRecognizer*
726 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
727 const ScheduleDAG *DAG) const;
729 /// Provide a global flag for disabling the PreRA hazard recognizer that
730 /// targets may choose to honor.
731 bool usePreRAHazardRecognizer() const;
733 /// analyzeCompare - For a comparison instruction, return the source registers
734 /// in SrcReg and SrcReg2 if having two register operands, and the value it
735 /// compares against in CmpValue. Return true if the comparison instruction
737 virtual bool analyzeCompare(const MachineInstr *MI,
738 unsigned &SrcReg, unsigned &SrcReg2,
739 int &Mask, int &Value) const {
743 /// optimizeCompareInstr - See if the comparison instruction can be converted
744 /// into something more efficient. E.g., on ARM most instructions can set the
745 /// flags register, obviating the need for a separate CMP.
746 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
747 unsigned SrcReg, unsigned SrcReg2,
749 const MachineRegisterInfo *MRI) const {
753 /// optimizeLoadInstr - Try to remove the load by folding it to a register
754 /// operand at the use. We fold the load instructions if and only if the
755 /// def and use are in the same BB. We only look at one load and see
756 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
757 /// defined by the load we are trying to fold. DefMI returns the machine
758 /// instruction that defines FoldAsLoadDefReg, and the function returns
759 /// the machine instruction generated due to folding.
760 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
761 const MachineRegisterInfo *MRI,
762 unsigned &FoldAsLoadDefReg,
763 MachineInstr *&DefMI) const {
767 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
768 /// instruction, try to fold the immediate into the use instruction.
769 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
770 /// then the caller may assume that DefMI has been erased from its parent
771 /// block. The caller may assume that it will not be erased by this
772 /// function otherwise.
773 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
774 unsigned Reg, MachineRegisterInfo *MRI) const {
778 /// getNumMicroOps - Return the number of u-operations the given machine
779 /// instruction will be decoded to on the target cpu. The itinerary's
780 /// IssueWidth is the number of microops that can be dispatched each
781 /// cycle. An instruction with zero microops takes no dispatch resources.
782 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
783 const MachineInstr *MI) const;
785 /// isZeroCost - Return true for pseudo instructions that don't consume any
786 /// machine resources in their current form. These are common cases that the
787 /// scheduler should consider free, rather than conservatively handling them
788 /// as instructions with no itinerary.
789 bool isZeroCost(unsigned Opcode) const {
790 return Opcode <= TargetOpcode::COPY;
793 virtual int getOperandLatency(const InstrItineraryData *ItinData,
794 SDNode *DefNode, unsigned DefIdx,
795 SDNode *UseNode, unsigned UseIdx) const;
797 /// getOperandLatency - Compute and return the use operand latency of a given
798 /// pair of def and use.
799 /// In most cases, the static scheduling itinerary was enough to determine the
800 /// operand latency. But it may not be possible for instructions with variable
801 /// number of defs / uses.
803 /// This is a raw interface to the itinerary that may be directly overriden by
804 /// a target. Use computeOperandLatency to get the best estimate of latency.
805 virtual int getOperandLatency(const InstrItineraryData *ItinData,
806 const MachineInstr *DefMI, unsigned DefIdx,
807 const MachineInstr *UseMI,
808 unsigned UseIdx) const;
810 /// computeOperandLatency - Compute and return the latency of the given data
811 /// dependent def and use when the operand indices are already known.
812 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
813 const MachineInstr *DefMI, unsigned DefIdx,
814 const MachineInstr *UseMI, unsigned UseIdx)
817 /// getInstrLatency - Compute the instruction latency of a given instruction.
818 /// If the instruction has higher cost when predicated, it's returned via
820 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
821 const MachineInstr *MI,
822 unsigned *PredCost = 0) const;
824 virtual int getInstrLatency(const InstrItineraryData *ItinData,
827 /// Return the default expected latency for a def based on it's opcode.
828 unsigned defaultDefLatency(const MCSchedModel *SchedModel,
829 const MachineInstr *DefMI) const;
831 int computeDefOperandLatency(const InstrItineraryData *ItinData,
832 const MachineInstr *DefMI) const;
834 /// isHighLatencyDef - Return true if this opcode has high latency to its
836 virtual bool isHighLatencyDef(int opc) const { return false; }
838 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
839 /// and an use in the current loop, return true if the target considered
840 /// it 'high'. This is used by optimization passes such as machine LICM to
841 /// determine whether it makes sense to hoist an instruction out even in
842 /// high register pressure situation.
844 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
845 const MachineRegisterInfo *MRI,
846 const MachineInstr *DefMI, unsigned DefIdx,
847 const MachineInstr *UseMI, unsigned UseIdx) const {
851 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
852 /// if the target considered it 'low'.
854 bool hasLowDefLatency(const InstrItineraryData *ItinData,
855 const MachineInstr *DefMI, unsigned DefIdx) const;
857 /// verifyInstruction - Perform target specific instruction verification.
859 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
863 /// getExecutionDomain - Return the current execution domain and bit mask of
864 /// possible domains for instruction.
866 /// Some micro-architectures have multiple execution domains, and multiple
867 /// opcodes that perform the same operation in different domains. For
868 /// example, the x86 architecture provides the por, orps, and orpd
869 /// instructions that all do the same thing. There is a latency penalty if a
870 /// register is written in one domain and read in another.
872 /// This function returns a pair (domain, mask) containing the execution
873 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
874 /// function can be used to change the opcode to one of the domains in the
875 /// bit mask. Instructions whose execution domain can't be changed should
878 /// The execution domain numbers don't have any special meaning except domain
879 /// 0 is used for instructions that are not associated with any interesting
880 /// execution domain.
882 virtual std::pair<uint16_t, uint16_t>
883 getExecutionDomain(const MachineInstr *MI) const {
884 return std::make_pair(0, 0);
887 /// setExecutionDomain - Change the opcode of MI to execute in Domain.
889 /// The bit (1 << Domain) must be set in the mask returned from
890 /// getExecutionDomain(MI).
892 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
895 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance
896 /// before an instruction with an unwanted partial register update.
898 /// Some instructions only write part of a register, and implicitly need to
899 /// read the other parts of the register. This may cause unwanted stalls
900 /// preventing otherwise unrelated instructions from executing in parallel in
901 /// an out-of-order CPU.
903 /// For example, the x86 instruction cvtsi2ss writes its result to bits
904 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
905 /// the instruction needs to wait for the old value of the register to become
908 /// addps %xmm1, %xmm0
909 /// movaps %xmm0, (%rax)
910 /// cvtsi2ss %rbx, %xmm0
912 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
913 /// instruction before it can issue, even though the high bits of %xmm0
914 /// probably aren't needed.
916 /// This hook returns the preferred clearance before MI, measured in
917 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
918 /// instructions before MI. It should only return a positive value for
919 /// unwanted dependencies. If the old bits of the defined register have
920 /// useful values, or if MI is determined to otherwise read the dependency,
921 /// the hook should return 0.
923 /// The unwanted dependency may be handled by:
925 /// 1. Allocating the same register for an MI def and use. That makes the
926 /// unwanted dependency identical to a required dependency.
928 /// 2. Allocating a register for the def that has no defs in the previous N
931 /// 3. Calling breakPartialRegDependency() with the same arguments. This
932 /// allows the target to insert a dependency breaking instruction.
935 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
936 const TargetRegisterInfo *TRI) const {
937 // The default implementation returns 0 for no partial register dependency.
941 /// breakPartialRegDependency - Insert a dependency-breaking instruction
942 /// before MI to eliminate an unwanted dependency on OpNum.
944 /// If it wasn't possible to avoid a def in the last N instructions before MI
945 /// (see getPartialRegUpdateClearance), this hook will be called to break the
946 /// unwanted dependency.
948 /// On x86, an xorps instruction can be used as a dependency breaker:
950 /// addps %xmm1, %xmm0
951 /// movaps %xmm0, (%rax)
952 /// xorps %xmm0, %xmm0
953 /// cvtsi2ss %rbx, %xmm0
955 /// An <imp-kill> operand should be added to MI if an instruction was
956 /// inserted. This ties the instructions together in the post-ra scheduler.
959 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
960 const TargetRegisterInfo *TRI) const {}
962 /// Create machine specific model for scheduling.
963 virtual DFAPacketizer*
964 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const {
969 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
972 } // End llvm namespace