1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
23 class InstrItineraryData;
26 class MachineMemOperand;
30 class ScheduleHazardRecognizer;
32 class TargetRegisterClass;
33 class TargetRegisterInfo;
35 template<class T> class SmallVectorImpl;
38 //---------------------------------------------------------------------------
40 /// TargetInstrInfo - Interface to description of machine instruction set
42 class TargetInstrInfo {
43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
44 unsigned NumOpcodes; // Number of entries in the desc array
46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
50 virtual ~TargetInstrInfo();
52 unsigned getNumOpcodes() const { return NumOpcodes; }
54 /// get - Return the machine instruction descriptor that corresponds to the
55 /// specified instruction opcode.
57 const TargetInstrDesc &get(unsigned Opcode) const {
58 assert(Opcode < NumOpcodes && "Invalid opcode!");
59 return Descriptors[Opcode];
62 /// isTriviallyReMaterializable - Return true if the instruction is trivially
63 /// rematerializable, meaning it has no side effects and requires no operands
64 /// that aren't always available.
65 bool isTriviallyReMaterializable(const MachineInstr *MI,
66 AliasAnalysis *AA = 0) const {
67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
68 (MI->getDesc().isRematerializable() &&
69 (isReallyTriviallyReMaterializable(MI, AA) ||
70 isReallyTriviallyReMaterializableGeneric(MI, AA)));
74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
76 /// specify whether the instruction is actually trivially rematerializable,
77 /// taking into consideration its operands. This predicate must return false
78 /// if the instruction has any side effects other than producing a value, or
79 /// if it requres any address registers that are not always available.
80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
81 AliasAnalysis *AA) const {
86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
87 /// for which the M_REMATERIALIZABLE flag is set and the target hook
88 /// isReallyTriviallyReMaterializable returns false, this function does
89 /// target-independent tests to determine if the instruction is really
90 /// trivially rematerializable.
91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
92 AliasAnalysis *AA) const;
95 /// isMoveInstr - Return true if the instruction is a register to register
96 /// move and return the source and dest operands and their sub-register
97 /// indices by reference.
98 virtual bool isMoveInstr(const MachineInstr& MI,
99 unsigned& SrcReg, unsigned& DstReg,
100 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
104 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
105 /// extension instruction. That is, it's like a copy where it's legal for the
106 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
107 /// true, then it's expected the pre-extension value is available as a subreg
108 /// of the result register. This also returns the sub-register index in
110 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
111 unsigned &SrcReg, unsigned &DstReg,
112 unsigned &SubIdx) const {
116 /// isIdentityCopy - Return true if the instruction is a copy (or
117 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
118 /// destination registers are the same.
119 bool isIdentityCopy(const MachineInstr &MI) const {
120 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
121 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
125 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
126 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
127 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
132 /// isLoadFromStackSlot - If the specified machine instruction is a direct
133 /// load from a stack slot, return the virtual or physical register number of
134 /// the destination along with the FrameIndex of the loaded stack slot. If
135 /// not, return 0. This predicate must return 0 if the instruction has
136 /// any side effects other than loading from the stack slot.
137 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
138 int &FrameIndex) const {
142 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
143 /// stack locations as well. This uses a heuristic so it isn't
144 /// reliable for correctness.
145 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
146 int &FrameIndex) const {
150 /// hasLoadFromStackSlot - If the specified machine instruction has
151 /// a load from a stack slot, return true along with the FrameIndex
152 /// of the loaded stack slot and the machine mem operand containing
153 /// the reference. If not, return false. Unlike
154 /// isLoadFromStackSlot, this returns true for any instructions that
155 /// loads from the stack. This is just a hint, as some cases may be
157 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
158 const MachineMemOperand *&MMO,
159 int &FrameIndex) const {
163 /// isStoreToStackSlot - If the specified machine instruction is a direct
164 /// store to a stack slot, return the virtual or physical register number of
165 /// the source reg along with the FrameIndex of the loaded stack slot. If
166 /// not, return 0. This predicate must return 0 if the instruction has
167 /// any side effects other than storing to the stack slot.
168 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
169 int &FrameIndex) const {
173 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
174 /// stack locations as well. This uses a heuristic so it isn't
175 /// reliable for correctness.
176 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
177 int &FrameIndex) const {
181 /// hasStoreToStackSlot - If the specified machine instruction has a
182 /// store to a stack slot, return true along with the FrameIndex of
183 /// the loaded stack slot and the machine mem operand containing the
184 /// reference. If not, return false. Unlike isStoreToStackSlot,
185 /// this returns true for any instructions that stores to the
186 /// stack. This is just a hint, as some cases may be missed.
187 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
188 const MachineMemOperand *&MMO,
189 int &FrameIndex) const {
193 /// reMaterialize - Re-issue the specified 'original' instruction at the
194 /// specific location targeting a new destination register.
195 /// The register in Orig->getOperand(0).getReg() will be substituted by
196 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
198 virtual void reMaterialize(MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator MI,
200 unsigned DestReg, unsigned SubIdx,
201 const MachineInstr *Orig,
202 const TargetRegisterInfo &TRI) const = 0;
204 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
205 /// two-addrss instruction inserted by two-address pass.
206 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
208 const TargetRegisterInfo &TRI) const {
212 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
213 /// MachineFunction::CloneMachineInstr(), but the target may update operands
214 /// that are required to be unique.
216 /// The instruction must be duplicable as indicated by isNotDuplicable().
217 virtual MachineInstr *duplicate(MachineInstr *Orig,
218 MachineFunction &MF) const = 0;
220 /// convertToThreeAddress - This method must be implemented by targets that
221 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
222 /// may be able to convert a two-address instruction into one or more true
223 /// three-address instructions on demand. This allows the X86 target (for
224 /// example) to convert ADD and SHL instructions into LEA instructions if they
225 /// would require register copies due to two-addressness.
227 /// This method returns a null pointer if the transformation cannot be
228 /// performed, otherwise it returns the last new instruction.
230 virtual MachineInstr *
231 convertToThreeAddress(MachineFunction::iterator &MFI,
232 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
236 /// commuteInstruction - If a target has any instructions that are
237 /// commutable but require converting to different instructions or making
238 /// non-trivial changes to commute them, this method can overloaded to do
239 /// that. The default implementation simply swaps the commutable operands.
240 /// If NewMI is false, MI is modified in place and returned; otherwise, a
241 /// new machine instruction is created and returned. Do not call this
242 /// method for a non-commutable instruction, but there may be some cases
243 /// where this method fails and returns null.
244 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
245 bool NewMI = false) const = 0;
247 /// findCommutedOpIndices - If specified MI is commutable, return the two
248 /// operand indices that would swap value. Return false if the instruction
249 /// is not in a form which this routine understands.
250 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
251 unsigned &SrcOpIdx2) const = 0;
253 /// produceSameValue - Return true if two machine instructions would produce
254 /// identical values. By default, this is only true when the two instructions
255 /// are deemed identical except for defs.
256 virtual bool produceSameValue(const MachineInstr *MI0,
257 const MachineInstr *MI1) const = 0;
259 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
260 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
261 /// implemented for a target). Upon success, this returns false and returns
262 /// with the following information in various cases:
264 /// 1. If this block ends with no branches (it just falls through to its succ)
265 /// just return false, leaving TBB/FBB null.
266 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
267 /// the destination block.
268 /// 3. If this block ends with a conditional branch and it falls through to a
269 /// successor block, it sets TBB to be the branch destination block and a
270 /// list of operands that evaluate the condition. These operands can be
271 /// passed to other TargetInstrInfo methods to create new branches.
272 /// 4. If this block ends with a conditional branch followed by an
273 /// unconditional branch, it returns the 'true' destination in TBB, the
274 /// 'false' destination in FBB, and a list of operands that evaluate the
275 /// condition. These operands can be passed to other TargetInstrInfo
276 /// methods to create new branches.
278 /// Note that RemoveBranch and InsertBranch must be implemented to support
279 /// cases where this method returns success.
281 /// If AllowModify is true, then this routine is allowed to modify the basic
282 /// block (e.g. delete instructions after the unconditional branch).
284 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
285 MachineBasicBlock *&FBB,
286 SmallVectorImpl<MachineOperand> &Cond,
287 bool AllowModify = false) const {
291 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
292 /// This is only invoked in cases where AnalyzeBranch returns success. It
293 /// returns the number of instructions that were removed.
294 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
295 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
299 /// InsertBranch - Insert branch code into the end of the specified
300 /// MachineBasicBlock. The operands to this method are the same as those
301 /// returned by AnalyzeBranch. This is only invoked in cases where
302 /// AnalyzeBranch returns success. It returns the number of instructions
305 /// It is also invoked by tail merging to add unconditional branches in
306 /// cases where AnalyzeBranch doesn't apply because there was no original
307 /// branch to analyze. At least this much must be implemented, else tail
308 /// merging needs to be disabled.
309 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
310 MachineBasicBlock *FBB,
311 const SmallVectorImpl<MachineOperand> &Cond,
313 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
317 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
318 /// after it, replacing it with an unconditional branch to NewDest. This is
319 /// used by the tail merging pass.
320 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
321 MachineBasicBlock *NewDest) const = 0;
323 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
324 /// block at the specified instruction (i.e. instruction would be the start
325 /// of a new basic block).
326 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator MBBI) const {
331 /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs"
332 /// of the specified basic block.
334 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
338 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
339 /// checks for the case where two basic blocks from true and false path
340 /// of a if-then-else (diamond) are predicated on mutally exclusive
343 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs,
344 MachineBasicBlock &FMBB, unsigned NumFInstrs) const {
348 /// isProfitableToDupForIfCvt - Return true if it's profitable for
349 /// if-converter to duplicate a specific number of instructions in the
350 /// specified MBB to enable if-conversion.
352 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs) const {
356 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
357 /// returns false if the target does not how to copy between the specified
359 virtual bool copyRegToReg(MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator MI,
361 unsigned DestReg, unsigned SrcReg,
362 const TargetRegisterClass *DestRC,
363 const TargetRegisterClass *SrcRC,
365 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
369 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
370 virtual void copyPhysReg(MachineBasicBlock &MBB,
371 MachineBasicBlock::iterator MI, DebugLoc DL,
372 unsigned DestReg, unsigned SrcReg,
373 bool KillSrc) const =0;
375 /// storeRegToStackSlot - Store the specified register of the given register
376 /// class to the specified stack frame index. The store instruction is to be
377 /// added to the given machine basic block before the specified machine
378 /// instruction. If isKill is true, the register operand is the last use and
379 /// must be marked kill.
380 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator MI,
382 unsigned SrcReg, bool isKill, int FrameIndex,
383 const TargetRegisterClass *RC,
384 const TargetRegisterInfo *TRI) const {
385 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
388 /// loadRegFromStackSlot - Load the specified register of the given register
389 /// class from the specified stack frame index. The load instruction is to be
390 /// added to the given machine basic block before the specified machine
392 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MI,
394 unsigned DestReg, int FrameIndex,
395 const TargetRegisterClass *RC,
396 const TargetRegisterInfo *TRI) const {
397 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
400 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
401 /// saved registers and returns true if it isn't possible / profitable to do
402 /// so by issuing a series of store instructions via
403 /// storeRegToStackSlot(). Returns false otherwise.
404 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
405 MachineBasicBlock::iterator MI,
406 const std::vector<CalleeSavedInfo> &CSI,
407 const TargetRegisterInfo *TRI) const {
411 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
412 /// saved registers and returns true if it isn't possible / profitable to do
413 /// so by issuing a series of load instructions via loadRegToStackSlot().
414 /// Returns false otherwise.
415 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator MI,
417 const std::vector<CalleeSavedInfo> &CSI,
418 const TargetRegisterInfo *TRI) const {
422 /// emitFrameIndexDebugValue - Emit a target-dependent form of
423 /// DBG_VALUE encoding the address of a frame index. Addresses would
424 /// normally be lowered the same way as other addresses on the target,
425 /// e.g. in load instructions. For targets that do not support this
426 /// the debug info is simply lost.
427 /// If you add this for a target you should handle this DBG_VALUE in the
428 /// target-specific AsmPrinter code as well; you will probably get invalid
429 /// assembly output if you don't.
430 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
438 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
439 /// slot into the specified machine instruction for the specified operand(s).
440 /// If this is possible, a new instruction is returned with the specified
441 /// operand folded, otherwise NULL is returned. The client is responsible for
442 /// removing the old instruction and adding the new one in the instruction
444 MachineInstr* foldMemoryOperand(MachineFunction &MF,
446 const SmallVectorImpl<unsigned> &Ops,
447 int FrameIndex) const;
449 /// foldMemoryOperand - Same as the previous version except it allows folding
450 /// of any load and store from / to any address, not just from a specific
452 MachineInstr* foldMemoryOperand(MachineFunction &MF,
454 const SmallVectorImpl<unsigned> &Ops,
455 MachineInstr* LoadMI) const;
458 /// foldMemoryOperandImpl - Target-dependent implementation for
459 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
460 /// take care of adding a MachineMemOperand to the newly created instruction.
461 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
463 const SmallVectorImpl<unsigned> &Ops,
464 int FrameIndex) const {
468 /// foldMemoryOperandImpl - Target-dependent implementation for
469 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
470 /// take care of adding a MachineMemOperand to the newly created instruction.
471 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
473 const SmallVectorImpl<unsigned> &Ops,
474 MachineInstr* LoadMI) const {
479 /// canFoldMemoryOperand - Returns true for the specified load / store if
480 /// folding is possible.
482 bool canFoldMemoryOperand(const MachineInstr *MI,
483 const SmallVectorImpl<unsigned> &Ops) const {
487 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
488 /// a store or a load and a store into two or more instruction. If this is
489 /// possible, returns true as well as the new instructions by reference.
490 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
491 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
492 SmallVectorImpl<MachineInstr*> &NewMIs) const{
496 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
497 SmallVectorImpl<SDNode*> &NewNodes) const {
501 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
502 /// instruction after load / store are unfolded from an instruction of the
503 /// specified opcode. It returns zero if the specified unfolding is not
504 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
505 /// index of the operand which will hold the register holding the loaded
507 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
508 bool UnfoldLoad, bool UnfoldStore,
509 unsigned *LoadRegIndex = 0) const {
513 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
514 /// to determine if two loads are loading from the same base address. It
515 /// should only return true if the base pointers are the same and the
516 /// only differences between the two addresses are the offset. It also returns
517 /// the offsets by reference.
518 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
519 int64_t &Offset1, int64_t &Offset2) const {
523 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
524 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
525 /// be scheduled togther. On some targets if two loads are loading from
526 /// addresses in the same cache line, it's better if they are scheduled
527 /// together. This function takes two integers that represent the load offsets
528 /// from the common base address. It returns true if it decides it's desirable
529 /// to schedule the two loads together. "NumLoads" is the number of loads that
530 /// have already been scheduled after Load1.
531 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
532 int64_t Offset1, int64_t Offset2,
533 unsigned NumLoads) const {
537 /// ReverseBranchCondition - Reverses the branch condition of the specified
538 /// condition list, returning false on success and true if it cannot be
541 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
545 /// insertNoop - Insert a noop into the instruction stream at the specified
547 virtual void insertNoop(MachineBasicBlock &MBB,
548 MachineBasicBlock::iterator MI) const;
551 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
552 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
553 // Default to just using 'nop' string.
557 /// isPredicated - Returns true if the instruction is already predicated.
559 virtual bool isPredicated(const MachineInstr *MI) const {
563 /// isUnpredicatedTerminator - Returns true if the instruction is a
564 /// terminator instruction that has not been predicated.
565 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
567 /// PredicateInstruction - Convert the instruction into a predicated
568 /// instruction. It returns true if the operation was successful.
570 bool PredicateInstruction(MachineInstr *MI,
571 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
573 /// SubsumesPredicate - Returns true if the first specified predicate
574 /// subsumes the second, e.g. GE subsumes GT.
576 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
577 const SmallVectorImpl<MachineOperand> &Pred2) const {
581 /// DefinesPredicate - If the specified instruction defines any predicate
582 /// or condition code register(s) used for predication, returns true as well
583 /// as the definition predicate(s) by reference.
584 virtual bool DefinesPredicate(MachineInstr *MI,
585 std::vector<MachineOperand> &Pred) const {
589 /// isPredicable - Return true if the specified instruction can be predicated.
590 /// By default, this returns true for every instruction with a
591 /// PredicateOperand.
592 virtual bool isPredicable(MachineInstr *MI) const {
593 return MI->getDesc().isPredicable();
596 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
597 /// instruction that defines the specified register class.
598 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
602 /// isSchedulingBoundary - Test if the given instruction should be
603 /// considered a scheduling boundary. This primarily includes labels and
605 virtual bool isSchedulingBoundary(const MachineInstr *MI,
606 const MachineBasicBlock *MBB,
607 const MachineFunction &MF) const = 0;
609 /// GetInstSize - Returns the size of the specified Instruction.
611 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
612 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
616 /// GetFunctionSizeInBytes - Returns the size of the specified
619 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
621 /// Measure the specified inline asm to determine an approximation of its
623 virtual unsigned getInlineAsmLength(const char *Str,
624 const MCAsmInfo &MAI) const;
626 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer
627 /// to use for this target when scheduling the machine instructions after
628 /// register allocation.
629 virtual ScheduleHazardRecognizer*
630 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0;
633 /// TargetInstrInfoImpl - This is the default implementation of
634 /// TargetInstrInfo, which just provides a couple of default implementations
635 /// for various methods. This separated out because it is implemented in
636 /// libcodegen, not in libtarget.
637 class TargetInstrInfoImpl : public TargetInstrInfo {
639 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
640 : TargetInstrInfo(desc, NumOpcodes) {}
642 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
643 MachineBasicBlock *NewDest) const;
644 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
645 bool NewMI = false) const;
646 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
647 unsigned &SrcOpIdx2) const;
648 virtual bool PredicateInstruction(MachineInstr *MI,
649 const SmallVectorImpl<MachineOperand> &Pred) const;
650 virtual void reMaterialize(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator MI,
652 unsigned DestReg, unsigned SubReg,
653 const MachineInstr *Orig,
654 const TargetRegisterInfo &TRI) const;
655 virtual MachineInstr *duplicate(MachineInstr *Orig,
656 MachineFunction &MF) const;
657 virtual bool produceSameValue(const MachineInstr *MI0,
658 const MachineInstr *MI1) const;
659 virtual bool isSchedulingBoundary(const MachineInstr *MI,
660 const MachineBasicBlock *MBB,
661 const MachineFunction &MF) const;
662 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
664 virtual ScheduleHazardRecognizer *
665 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
666 virtual void copyPhysReg(MachineBasicBlock &MBB,
667 MachineBasicBlock::iterator MI, DebugLoc DL,
668 unsigned DestReg, unsigned SrcReg,
672 } // End llvm namespace