1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/Support/DataTypes.h"
31 class MachineCodeForInstruction;
32 class TargetRegisterClass;
34 //---------------------------------------------------------------------------
35 // Data types used to define information about a single machine instruction
36 //---------------------------------------------------------------------------
38 typedef short MachineOpCode;
39 typedef unsigned InstrSchedClass;
41 //---------------------------------------------------------------------------
42 // struct TargetInstrDescriptor:
43 // Predefined information about each machine instruction.
44 // Designed to initialized statically.
47 const unsigned M_BRANCH_FLAG = 1 << 0;
48 const unsigned M_CALL_FLAG = 1 << 1;
49 const unsigned M_RET_FLAG = 1 << 2;
50 const unsigned M_BARRIER_FLAG = 1 << 3;
51 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
52 const unsigned M_LOAD_FLAG = 1 << 5;
53 const unsigned M_STORE_FLAG = 1 << 6;
55 // M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
56 const unsigned M_2_ADDR_FLAG = 1 << 7;
58 // M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
59 // changed into a 3-address instruction if the first two operands cannot be
60 // assigned to the same register. The target must implement the
61 // TargetInstrInfo::convertToThreeAddress method for this instruction.
62 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8;
64 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
65 // Z), which produces the same result if Y and Z are exchanged.
66 const unsigned M_COMMUTABLE = 1 << 9;
68 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
69 // block? Typically this is things like return and branch instructions.
70 // Various passes use this to insert code into the bottom of a basic block, but
71 // before control flow occurs.
72 const unsigned M_TERMINATOR_FLAG = 1 << 10;
74 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
75 // insertion support when the DAG scheduler is inserting it into a machine basic
77 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11;
79 /// TargetOperandInfo - This holds information about one operand of a machine
80 /// instruction, indicating the register class for register operands, etc.
82 class TargetOperandInfo {
84 /// RegClass - This specifies the register class of the operand if the
85 /// operand is a register. If not, this contains null.
86 const TargetRegisterClass *RegClass;
88 /// Currently no other information.
92 class TargetInstrDescriptor {
94 const char * Name; // Assembly language mnemonic for the opcode.
95 int numOperands; // Number of args; -1 if variable #args
96 InstrSchedClass schedClass; // enum identifying instr sched class
97 unsigned Flags; // flags identifying machine instr class
98 unsigned TSFlags; // Target Specific Flag values
99 const unsigned *ImplicitUses; // Registers implicitly read by this instr
100 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
101 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
105 //---------------------------------------------------------------------------
107 /// TargetInstrInfo - Interface to description of machine instructions
109 class TargetInstrInfo {
110 const TargetInstrDescriptor* desc; // raw array to allow static init'n
111 unsigned NumOpcodes; // number of entries in the desc array
112 unsigned numRealOpCodes; // number of non-dummy op codes
114 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
115 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
117 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
118 virtual ~TargetInstrInfo();
120 // Invariant opcodes: All instruction sets have these as their low opcodes.
126 unsigned getNumOpcodes() const { return NumOpcodes; }
128 /// get - Return the machine instruction descriptor that corresponds to the
129 /// specified instruction opcode.
131 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
132 assert((unsigned)Opcode < NumOpcodes);
136 const char *getName(MachineOpCode Opcode) const {
137 return get(Opcode).Name;
140 int getNumOperands(MachineOpCode Opcode) const {
141 return get(Opcode).numOperands;
144 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
145 return get(Opcode).schedClass;
148 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
149 return get(Opcode).ImplicitUses;
152 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
153 return get(Opcode).ImplicitDefs;
158 // Query instruction class flags according to the machine-independent
159 // flags listed above.
161 bool isReturn(MachineOpCode Opcode) const {
162 return get(Opcode).Flags & M_RET_FLAG;
165 bool isTwoAddrInstr(MachineOpCode Opcode) const {
166 return get(Opcode).Flags & M_2_ADDR_FLAG;
168 bool isCommutableInstr(MachineOpCode Opcode) const {
169 return get(Opcode).Flags & M_COMMUTABLE;
171 bool isTerminatorInstr(unsigned Opcode) const {
172 return get(Opcode).Flags & M_TERMINATOR_FLAG;
175 bool isBranch(MachineOpCode Opcode) const {
176 return get(Opcode).Flags & M_BRANCH_FLAG;
179 /// isBarrier - Returns true if the specified instruction stops control flow
180 /// from executing the instruction immediately following it. Examples include
181 /// unconditional branches and return instructions.
182 bool isBarrier(MachineOpCode Opcode) const {
183 return get(Opcode).Flags & M_BARRIER_FLAG;
186 bool isCall(MachineOpCode Opcode) const {
187 return get(Opcode).Flags & M_CALL_FLAG;
189 bool isLoad(MachineOpCode Opcode) const {
190 return get(Opcode).Flags & M_LOAD_FLAG;
192 bool isStore(MachineOpCode Opcode) const {
193 return get(Opcode).Flags & M_STORE_FLAG;
196 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
197 /// custom insertion support when the DAG scheduler is inserting it into a
198 /// machine basic block.
199 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
200 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
203 /// Return true if the instruction is a register to register move
204 /// and leave the source and dest operands in the passed parameters.
205 virtual bool isMoveInstr(const MachineInstr& MI,
207 unsigned& destReg) const {
211 /// isLoadFromStackSlot - If the specified machine instruction is a direct
212 /// load from a stack slot, return the virtual or physical register number of
213 /// the destination along with the FrameIndex of the loaded stack slot. If
214 /// not, return 0. This predicate must return 0 if the instruction has
215 /// any side effects other than loading from the stack slot.
216 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
220 /// isStoreToStackSlot - If the specified machine instruction is a direct
221 /// store to a stack slot, return the virtual or physical register number of
222 /// the source reg along with the FrameIndex of the loaded stack slot. If
223 /// not, return 0. This predicate must return 0 if the instruction has
224 /// any side effects other than storing to the stack slot.
225 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
229 /// convertToThreeAddress - This method must be implemented by targets that
230 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
231 /// may be able to convert a two-address instruction into a true
232 /// three-address instruction on demand. This allows the X86 target (for
233 /// example) to convert ADD and SHL instructions into LEA instructions if they
234 /// would require register copies due to two-addressness.
236 /// This method returns a null pointer if the transformation cannot be
237 /// performed, otherwise it returns the new instruction.
239 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
243 /// commuteInstruction - If a target has any instructions that are commutable,
244 /// but require converting to a different instruction or making non-trivial
245 /// changes to commute them, this method can overloaded to do this. The
246 /// default implementation of this method simply swaps the first two operands
247 /// of MI and returns it.
249 /// If a target wants to make more aggressive changes, they can construct and
250 /// return a new machine instruction. If an instruction cannot commute, it
251 /// can also return null.
253 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
255 /// Insert a goto (unconditional branch) sequence to TMBB, at the
257 virtual void insertGoto(MachineBasicBlock& MBB,
258 MachineBasicBlock& TMBB) const {
259 assert(0 && "Target didn't implement insertGoto!");
262 /// Reverses the branch condition of the MachineInstr pointed by
263 /// MI. The instruction is replaced and the new MI is returned.
264 virtual MachineBasicBlock::iterator
265 reverseBranchCondition(MachineBasicBlock::iterator MI) const {
266 assert(0 && "Target didn't implement reverseBranchCondition!");
271 /// insertNoop - Insert a noop into the instruction stream at the specified
273 virtual void insertNoop(MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator MI) const {
275 assert(0 && "Target didn't implement insertNoop!");
279 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
280 /// which must be filled by the code generator.
281 bool hasDelaySlot(unsigned Opcode) const {
282 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
286 } // End llvm namespace