1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
25 class MachineMemOperand;
30 class TargetRegisterClass;
31 class TargetRegisterInfo;
33 template<class T> class SmallVectorImpl;
36 //---------------------------------------------------------------------------
38 /// TargetInstrInfo - Interface to description of machine instruction set
40 class TargetInstrInfo {
41 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
42 unsigned NumOpcodes; // Number of entries in the desc array
44 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
45 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
48 virtual ~TargetInstrInfo();
50 unsigned getNumOpcodes() const { return NumOpcodes; }
52 /// get - Return the machine instruction descriptor that corresponds to the
53 /// specified instruction opcode.
55 const TargetInstrDesc &get(unsigned Opcode) const {
56 assert(Opcode < NumOpcodes && "Invalid opcode!");
57 return Descriptors[Opcode];
60 /// isTriviallyReMaterializable - Return true if the instruction is trivially
61 /// rematerializable, meaning it has no side effects and requires no operands
62 /// that aren't always available.
63 bool isTriviallyReMaterializable(const MachineInstr *MI,
64 AliasAnalysis *AA = 0) const {
65 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
66 (MI->getDesc().isRematerializable() &&
67 (isReallyTriviallyReMaterializable(MI, AA) ||
68 isReallyTriviallyReMaterializableGeneric(MI, AA)));
72 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
73 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
74 /// specify whether the instruction is actually trivially rematerializable,
75 /// taking into consideration its operands. This predicate must return false
76 /// if the instruction has any side effects other than producing a value, or
77 /// if it requres any address registers that are not always available.
78 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
79 AliasAnalysis *AA) const {
84 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
85 /// for which the M_REMATERIALIZABLE flag is set and the target hook
86 /// isReallyTriviallyReMaterializable returns false, this function does
87 /// target-independent tests to determine if the instruction is really
88 /// trivially rematerializable.
89 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
90 AliasAnalysis *AA) const;
93 /// isMoveInstr - Return true if the instruction is a register to register
94 /// move and return the source and dest operands and their sub-register
95 /// indices by reference.
96 virtual bool isMoveInstr(const MachineInstr& MI,
97 unsigned& SrcReg, unsigned& DstReg,
98 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
102 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
103 /// extension instruction. That is, it's like a copy where it's legal for the
104 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
105 /// true, then it's expected the pre-extension value is available as a subreg
106 /// of the result register. This also returns the sub-register index in
108 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
109 unsigned &SrcReg, unsigned &DstReg,
110 unsigned &SubIdx) const {
114 /// isIdentityCopy - Return true if the instruction is a copy (or
115 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
116 /// destination registers are the same.
117 bool isIdentityCopy(const MachineInstr &MI) const {
118 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
119 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
123 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG &&
124 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
127 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
128 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
129 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
134 /// isLoadFromStackSlot - If the specified machine instruction is a direct
135 /// load from a stack slot, return the virtual or physical register number of
136 /// the destination along with the FrameIndex of the loaded stack slot. If
137 /// not, return 0. This predicate must return 0 if the instruction has
138 /// any side effects other than loading from the stack slot.
139 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
140 int &FrameIndex) const {
144 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
145 /// stack locations as well. This uses a heuristic so it isn't
146 /// reliable for correctness.
147 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
148 int &FrameIndex) const {
152 /// hasLoadFromStackSlot - If the specified machine instruction has
153 /// a load from a stack slot, return true along with the FrameIndex
154 /// of the loaded stack slot and the machine mem operand containing
155 /// the reference. If not, return false. Unlike
156 /// isLoadFromStackSlot, this returns true for any instructions that
157 /// loads from the stack. This is just a hint, as some cases may be
159 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
160 const MachineMemOperand *&MMO,
161 int &FrameIndex) const {
165 /// isStoreToStackSlot - If the specified machine instruction is a direct
166 /// store to a stack slot, return the virtual or physical register number of
167 /// the source reg along with the FrameIndex of the loaded stack slot. If
168 /// not, return 0. This predicate must return 0 if the instruction has
169 /// any side effects other than storing to the stack slot.
170 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
171 int &FrameIndex) const {
175 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
176 /// stack locations as well. This uses a heuristic so it isn't
177 /// reliable for correctness.
178 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
179 int &FrameIndex) const {
183 /// hasStoreToStackSlot - If the specified machine instruction has a
184 /// store to a stack slot, return true along with the FrameIndex of
185 /// the loaded stack slot and the machine mem operand containing the
186 /// reference. If not, return false. Unlike isStoreToStackSlot,
187 /// this returns true for any instructions that stores to the
188 /// stack. This is just a hint, as some cases may be missed.
189 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
190 const MachineMemOperand *&MMO,
191 int &FrameIndex) const {
195 /// reMaterialize - Re-issue the specified 'original' instruction at the
196 /// specific location targeting a new destination register.
197 virtual void reMaterialize(MachineBasicBlock &MBB,
198 MachineBasicBlock::iterator MI,
199 unsigned DestReg, unsigned SubIdx,
200 const MachineInstr *Orig,
201 const TargetRegisterInfo *TRI) const = 0;
203 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
204 /// MachineFunction::CloneMachineInstr(), but the target may update operands
205 /// that are required to be unique.
207 /// The instruction must be duplicable as indicated by isNotDuplicable().
208 virtual MachineInstr *duplicate(MachineInstr *Orig,
209 MachineFunction &MF) const = 0;
211 /// convertToThreeAddress - This method must be implemented by targets that
212 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
213 /// may be able to convert a two-address instruction into one or more true
214 /// three-address instructions on demand. This allows the X86 target (for
215 /// example) to convert ADD and SHL instructions into LEA instructions if they
216 /// would require register copies due to two-addressness.
218 /// This method returns a null pointer if the transformation cannot be
219 /// performed, otherwise it returns the last new instruction.
221 virtual MachineInstr *
222 convertToThreeAddress(MachineFunction::iterator &MFI,
223 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
227 /// commuteInstruction - If a target has any instructions that are commutable,
228 /// but require converting to a different instruction or making non-trivial
229 /// changes to commute them, this method can overloaded to do this. The
230 /// default implementation of this method simply swaps the first two operands
231 /// of MI and returns it.
233 /// If a target wants to make more aggressive changes, they can construct and
234 /// return a new machine instruction. If an instruction cannot commute, it
235 /// can also return null.
237 /// If NewMI is true, then a new machine instruction must be created.
239 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
240 bool NewMI = false) const = 0;
242 /// findCommutedOpIndices - If specified MI is commutable, return the two
243 /// operand indices that would swap value. Return true if the instruction
244 /// is not in a form which this routine understands.
245 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
246 unsigned &SrcOpIdx2) const = 0;
248 /// produceSameValue - Return true if two machine instructions would produce
249 /// identical values. By default, this is only true when the two instructions
250 /// are deemed identical except for defs.
251 virtual bool produceSameValue(const MachineInstr *MI0,
252 const MachineInstr *MI1) const = 0;
254 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
255 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
256 /// implemented for a target). Upon success, this returns false and returns
257 /// with the following information in various cases:
259 /// 1. If this block ends with no branches (it just falls through to its succ)
260 /// just return false, leaving TBB/FBB null.
261 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
262 /// the destination block.
263 /// 3. If this block ends with a conditional branch and it falls through to a
264 /// successor block, it sets TBB to be the branch destination block and a
265 /// list of operands that evaluate the condition. These operands can be
266 /// passed to other TargetInstrInfo methods to create new branches.
267 /// 4. If this block ends with a conditional branch followed by an
268 /// unconditional branch, it returns the 'true' destination in TBB, the
269 /// 'false' destination in FBB, and a list of operands that evaluate the
270 /// condition. These operands can be passed to other TargetInstrInfo
271 /// methods to create new branches.
273 /// Note that RemoveBranch and InsertBranch must be implemented to support
274 /// cases where this method returns success.
276 /// If AllowModify is true, then this routine is allowed to modify the basic
277 /// block (e.g. delete instructions after the unconditional branch).
279 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
280 MachineBasicBlock *&FBB,
281 SmallVectorImpl<MachineOperand> &Cond,
282 bool AllowModify = false) const {
286 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
287 /// This is only invoked in cases where AnalyzeBranch returns success. It
288 /// returns the number of instructions that were removed.
289 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
290 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
294 /// InsertBranch - Insert branch code into the end of the specified
295 /// MachineBasicBlock. The operands to this method are the same as those
296 /// returned by AnalyzeBranch. This is only invoked in cases where
297 /// AnalyzeBranch returns success. It returns the number of instructions
300 /// It is also invoked by tail merging to add unconditional branches in
301 /// cases where AnalyzeBranch doesn't apply because there was no original
302 /// branch to analyze. At least this much must be implemented, else tail
303 /// merging needs to be disabled.
304 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
305 MachineBasicBlock *FBB,
306 const SmallVectorImpl<MachineOperand> &Cond) const {
307 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
311 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
312 /// returns false if the target does not how to copy between the specified
314 virtual bool copyRegToReg(MachineBasicBlock &MBB,
315 MachineBasicBlock::iterator MI,
316 unsigned DestReg, unsigned SrcReg,
317 const TargetRegisterClass *DestRC,
318 const TargetRegisterClass *SrcRC,
320 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
324 /// storeRegToStackSlot - Store the specified register of the given register
325 /// class to the specified stack frame index. The store instruction is to be
326 /// added to the given machine basic block before the specified machine
327 /// instruction. If isKill is true, the register operand is the last use and
328 /// must be marked kill.
329 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator MI,
331 unsigned SrcReg, bool isKill, int FrameIndex,
332 const TargetRegisterClass *RC,
333 const TargetRegisterInfo *TRI) const {
334 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
337 /// loadRegFromStackSlot - Load the specified register of the given register
338 /// class from the specified stack frame index. The load instruction is to be
339 /// added to the given machine basic block before the specified machine
341 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
342 MachineBasicBlock::iterator MI,
343 unsigned DestReg, int FrameIndex,
344 const TargetRegisterClass *RC,
345 const TargetRegisterInfo *TRI) const {
346 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
349 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
350 /// saved registers and returns true if it isn't possible / profitable to do
351 /// so by issuing a series of store instructions via
352 /// storeRegToStackSlot(). Returns false otherwise.
353 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator MI,
355 const std::vector<CalleeSavedInfo> &CSI,
356 const TargetRegisterInfo *TRI) const {
360 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
361 /// saved registers and returns true if it isn't possible / profitable to do
362 /// so by issuing a series of load instructions via loadRegToStackSlot().
363 /// Returns false otherwise.
364 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
365 MachineBasicBlock::iterator MI,
366 const std::vector<CalleeSavedInfo> &CSI,
367 const TargetRegisterInfo *TRI) const {
371 /// emitFrameIndexDebugValue - Emit a target-dependent form of
372 /// DBG_VALUE encoding the address of a frame index. Addresses would
373 /// normally be lowered the same way as other addresses on the target,
374 /// e.g. in load instructions. For targets that do not support this
375 /// the debug info is simply lost.
376 /// If you add this for a target you should handle this DBG_VALUE in the
377 /// target-specific AsmPrinter code as well; you will probably get invalid
378 /// assembly output if you don't.
379 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
387 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
388 /// slot into the specified machine instruction for the specified operand(s).
389 /// If this is possible, a new instruction is returned with the specified
390 /// operand folded, otherwise NULL is returned. The client is responsible for
391 /// removing the old instruction and adding the new one in the instruction
393 MachineInstr* foldMemoryOperand(MachineFunction &MF,
395 const SmallVectorImpl<unsigned> &Ops,
396 int FrameIndex) const;
398 /// foldMemoryOperand - Same as the previous version except it allows folding
399 /// of any load and store from / to any address, not just from a specific
401 MachineInstr* foldMemoryOperand(MachineFunction &MF,
403 const SmallVectorImpl<unsigned> &Ops,
404 MachineInstr* LoadMI) const;
407 /// foldMemoryOperandImpl - Target-dependent implementation for
408 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
409 /// take care of adding a MachineMemOperand to the newly created instruction.
410 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
412 const SmallVectorImpl<unsigned> &Ops,
413 int FrameIndex) const {
417 /// foldMemoryOperandImpl - Target-dependent implementation for
418 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
419 /// take care of adding a MachineMemOperand to the newly created instruction.
420 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
422 const SmallVectorImpl<unsigned> &Ops,
423 MachineInstr* LoadMI) const {
428 /// canFoldMemoryOperand - Returns true for the specified load / store if
429 /// folding is possible.
431 bool canFoldMemoryOperand(const MachineInstr *MI,
432 const SmallVectorImpl<unsigned> &Ops) const {
436 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
437 /// a store or a load and a store into two or more instruction. If this is
438 /// possible, returns true as well as the new instructions by reference.
439 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
440 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
441 SmallVectorImpl<MachineInstr*> &NewMIs) const{
445 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
446 SmallVectorImpl<SDNode*> &NewNodes) const {
450 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
451 /// instruction after load / store are unfolded from an instruction of the
452 /// specified opcode. It returns zero if the specified unfolding is not
453 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
454 /// index of the operand which will hold the register holding the loaded
456 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
457 bool UnfoldLoad, bool UnfoldStore,
458 unsigned *LoadRegIndex = 0) const {
462 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
463 /// to determine if two loads are loading from the same base address. It
464 /// should only return true if the base pointers are the same and the
465 /// only differences between the two addresses are the offset. It also returns
466 /// the offsets by reference.
467 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
468 int64_t &Offset1, int64_t &Offset2) const {
472 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
473 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
474 /// be scheduled togther. On some targets if two loads are loading from
475 /// addresses in the same cache line, it's better if they are scheduled
476 /// together. This function takes two integers that represent the load offsets
477 /// from the common base address. It returns true if it decides it's desirable
478 /// to schedule the two loads together. "NumLoads" is the number of loads that
479 /// have already been scheduled after Load1.
480 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
481 int64_t Offset1, int64_t Offset2,
482 unsigned NumLoads) const {
486 /// ReverseBranchCondition - Reverses the branch condition of the specified
487 /// condition list, returning false on success and true if it cannot be
490 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
494 /// insertNoop - Insert a noop into the instruction stream at the specified
496 virtual void insertNoop(MachineBasicBlock &MBB,
497 MachineBasicBlock::iterator MI) const;
500 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
501 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
502 // Default to just using 'nop' string.
506 /// isPredicated - Returns true if the instruction is already predicated.
508 virtual bool isPredicated(const MachineInstr *MI) const {
512 /// isUnpredicatedTerminator - Returns true if the instruction is a
513 /// terminator instruction that has not been predicated.
514 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
516 /// PredicateInstruction - Convert the instruction into a predicated
517 /// instruction. It returns true if the operation was successful.
519 bool PredicateInstruction(MachineInstr *MI,
520 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
522 /// SubsumesPredicate - Returns true if the first specified predicate
523 /// subsumes the second, e.g. GE subsumes GT.
525 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
526 const SmallVectorImpl<MachineOperand> &Pred2) const {
530 /// DefinesPredicate - If the specified instruction defines any predicate
531 /// or condition code register(s) used for predication, returns true as well
532 /// as the definition predicate(s) by reference.
533 virtual bool DefinesPredicate(MachineInstr *MI,
534 std::vector<MachineOperand> &Pred) const {
538 /// isPredicable - Return true if the specified instruction can be predicated.
539 /// By default, this returns true for every instruction with a
540 /// PredicateOperand.
541 virtual bool isPredicable(MachineInstr *MI) const {
542 return MI->getDesc().isPredicable();
545 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
546 /// instruction that defines the specified register class.
547 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
551 /// GetInstSize - Returns the size of the specified Instruction.
553 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
554 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
558 /// GetFunctionSizeInBytes - Returns the size of the specified
561 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
563 /// Measure the specified inline asm to determine an approximation of its
565 virtual unsigned getInlineAsmLength(const char *Str,
566 const MCAsmInfo &MAI) const;
569 /// TargetInstrInfoImpl - This is the default implementation of
570 /// TargetInstrInfo, which just provides a couple of default implementations
571 /// for various methods. This separated out because it is implemented in
572 /// libcodegen, not in libtarget.
573 class TargetInstrInfoImpl : public TargetInstrInfo {
575 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
576 : TargetInstrInfo(desc, NumOpcodes) {}
578 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
579 bool NewMI = false) const;
580 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
581 unsigned &SrcOpIdx2) const;
582 virtual bool PredicateInstruction(MachineInstr *MI,
583 const SmallVectorImpl<MachineOperand> &Pred) const;
584 virtual void reMaterialize(MachineBasicBlock &MBB,
585 MachineBasicBlock::iterator MI,
586 unsigned DestReg, unsigned SubReg,
587 const MachineInstr *Orig,
588 const TargetRegisterInfo *TRI) const;
589 virtual MachineInstr *duplicate(MachineInstr *Orig,
590 MachineFunction &MF) const;
591 virtual bool produceSameValue(const MachineInstr *MI0,
592 const MachineInstr *MI1) const;
593 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
596 } // End llvm namespace