1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/Support/DataTypes.h"
31 class MachineCodeForInstruction;
33 //---------------------------------------------------------------------------
34 // Data types used to define information about a single machine instruction
35 //---------------------------------------------------------------------------
37 typedef short MachineOpCode;
38 typedef unsigned InstrSchedClass;
40 //---------------------------------------------------------------------------
41 // struct TargetInstrDescriptor:
42 // Predefined information about each machine instruction.
43 // Designed to initialized statically.
46 const unsigned M_NOP_FLAG = 1 << 0;
47 const unsigned M_BRANCH_FLAG = 1 << 1;
48 const unsigned M_CALL_FLAG = 1 << 2;
49 const unsigned M_RET_FLAG = 1 << 3;
50 const unsigned M_BARRIER_FLAG = 1 << 4;
51 const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
52 const unsigned M_CC_FLAG = 1 << 6;
53 const unsigned M_LOAD_FLAG = 1 << 7;
54 const unsigned M_STORE_FLAG = 1 << 8;
56 // M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
57 const unsigned M_2_ADDR_FLAG = 1 << 9;
59 // M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
60 // changed into a 3-address instruction if the first two operands cannot be
61 // assigned to the same register. The target must implement the
62 // TargetInstrInfo::convertToThreeAddress method for this instruction.
63 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10;
65 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
66 // Z), which produces the same result if Y and Z are exchanged.
67 const unsigned M_COMMUTABLE = 1 << 11;
69 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
70 // block? Typically this is things like return and branch instructions.
71 // Various passes use this to insert code into the bottom of a basic block, but
72 // before control flow occurs.
73 const unsigned M_TERMINATOR_FLAG = 1 << 12;
75 class TargetInstrDescriptor {
77 const char * Name; // Assembly language mnemonic for the opcode.
78 int numOperands; // Number of args; -1 if variable #args
79 int resultPos; // Position of the result; -1 if no result
80 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
81 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
82 // smallest -ve value is -(maxImmedConst+1).
83 unsigned numDelaySlots; // Number of delay slots after instruction
84 unsigned latency; // Latency in machine cycles
85 InstrSchedClass schedClass; // enum identifying instr sched class
86 unsigned Flags; // flags identifying machine instr class
87 unsigned TSFlags; // Target Specific Flag values
88 const unsigned *ImplicitUses; // Registers implicitly read by this instr
89 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
93 //---------------------------------------------------------------------------
95 /// TargetInstrInfo - Interface to description of machine instructions
97 class TargetInstrInfo {
98 const TargetInstrDescriptor* desc; // raw array to allow static init'n
99 unsigned NumOpcodes; // number of entries in the desc array
100 unsigned numRealOpCodes; // number of non-dummy op codes
102 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
103 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
105 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
106 virtual ~TargetInstrInfo();
108 // Invariant: All instruction sets use opcode #0 as the PHI instruction
111 unsigned getNumOpcodes() const { return NumOpcodes; }
113 /// get - Return the machine instruction descriptor that corresponds to the
114 /// specified instruction opcode.
116 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
117 assert((unsigned)Opcode < NumOpcodes);
121 const char *getName(MachineOpCode Opcode) const {
122 return get(Opcode).Name;
125 int getNumOperands(MachineOpCode Opcode) const {
126 return get(Opcode).numOperands;
130 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
131 return get(Opcode).schedClass;
134 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
135 return get(Opcode).ImplicitUses;
138 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
139 return get(Opcode).ImplicitDefs;
144 // Query instruction class flags according to the machine-independent
145 // flags listed above.
147 bool isReturn(MachineOpCode Opcode) const {
148 return get(Opcode).Flags & M_RET_FLAG;
151 bool isTwoAddrInstr(MachineOpCode Opcode) const {
152 return get(Opcode).Flags & M_2_ADDR_FLAG;
154 bool isTerminatorInstr(unsigned Opcode) const {
155 return get(Opcode).Flags & M_TERMINATOR_FLAG;
158 /// Return true if the instruction is a register to register move
159 /// and leave the source and dest operands in the passed parameters.
160 virtual bool isMoveInstr(const MachineInstr& MI,
162 unsigned& destReg) const {
166 /// convertToThreeAddress - This method must be implemented by targets that
167 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
168 /// may be able to convert a two-address instruction into a true
169 /// three-address instruction on demand. This allows the X86 target (for
170 /// example) to convert ADD and SHL instructions into LEA instructions if they
171 /// would require register copies due to two-addressness.
173 /// This method returns a null pointer if the transformation cannot be
174 /// performed, otherwise it returns the new instruction.
176 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
180 /// commuteInstruction - If a target has any instructions that are commutable,
181 /// but require converting to a different instruction or making non-trivial
182 /// changes to commute them, this method can overloaded to do this. The
183 /// default implementation of this method simply swaps the first two operands
184 /// of MI and returns it.
186 /// If a target wants to make more aggressive changes, they can construct and
187 /// return a new machine instruction. If an instruction cannot commute, it
188 /// can also return null.
190 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
192 /// Insert a goto (unconditional branch) sequence to TMBB, at the
194 virtual void insertGoto(MachineBasicBlock& MBB,
195 MachineBasicBlock& TMBB) const {
196 assert(0 && "Target didn't implement insertGoto!");
199 /// Reverses the branch condition of the MachineInstr pointed by
200 /// MI. The instruction is replaced and the new MI is returned.
201 virtual MachineBasicBlock::iterator
202 reverseBranchCondition(MachineBasicBlock::iterator MI) const {
203 assert(0 && "Target didn't implement reverseBranchCondition!");
208 //-------------------------------------------------------------------------
209 // Code generation support for creating individual machine instructions
211 // WARNING: These methods are Sparc specific
213 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
215 //-------------------------------------------------------------------------
217 unsigned getNumDelaySlots(MachineOpCode Opcode) const {
218 return get(Opcode).numDelaySlots;
220 bool isCCInstr(MachineOpCode Opcode) const {
221 return get(Opcode).Flags & M_CC_FLAG;
223 bool isNop(MachineOpCode Opcode) const {
224 return get(Opcode).Flags & M_NOP_FLAG;
226 bool isBranch(MachineOpCode Opcode) const {
227 return get(Opcode).Flags & M_BRANCH_FLAG;
229 /// isBarrier - Returns true if the specified instruction stops control flow
230 /// from executing the instruction immediately following it. Examples include
231 /// unconditional branches and return instructions.
232 bool isBarrier(MachineOpCode Opcode) const {
233 return get(Opcode).Flags & M_BARRIER_FLAG;
236 bool isCall(MachineOpCode Opcode) const {
237 return get(Opcode).Flags & M_CALL_FLAG;
239 bool isLoad(MachineOpCode Opcode) const {
240 return get(Opcode).Flags & M_LOAD_FLAG;
242 bool isStore(MachineOpCode Opcode) const {
243 return get(Opcode).Flags & M_STORE_FLAG;
246 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
247 /// which must be filled by the code generator.
248 bool hasDelaySlot(unsigned Opcode) const {
249 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
252 virtual bool hasResultInterlock(MachineOpCode Opcode) const {
257 // Latencies for individual instructions and instruction pairs
259 virtual int minLatency(MachineOpCode Opcode) const {
260 return get(Opcode).latency;
263 virtual int maxLatency(MachineOpCode Opcode) const {
264 return get(Opcode).latency;
268 // Which operand holds an immediate constant? Returns -1 if none
270 virtual int getImmedConstantPos(MachineOpCode Opcode) const {
271 return -1; // immediate position is machine specific, so say -1 == "none"
274 // Check if the specified constant fits in the immediate field
275 // of this machine instruction
277 virtual bool constantFitsInImmedField(MachineOpCode Opcode,
278 int64_t intValue) const;
280 // Return the largest positive constant that can be held in the IMMED field
281 // of this machine instruction.
282 // isSignExtended is set to true if the value is sign-extended before use
283 // (this is true for all immediate fields in SPARC instructions).
284 // Return 0 if the instruction has no IMMED field.
286 virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
287 bool &isSignExtended) const {
288 isSignExtended = get(Opcode).immedIsSignExtended;
289 return get(Opcode).maxImmedConst;
293 } // End llvm namespace