1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
23 class TargetRegisterClass;
24 class TargetRegisterInfo;
26 class CalleeSavedInfo;
30 template<class T> class SmallVectorImpl;
33 //---------------------------------------------------------------------------
35 /// TargetInstrInfo - Interface to description of machine instruction set
37 class TargetInstrInfo {
38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
39 unsigned NumOpcodes; // Number of entries in the desc array
41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
45 virtual ~TargetInstrInfo();
47 // Invariant opcodes: All instruction sets have these as their low opcodes.
55 /// KILL - This instruction is a noop that is used only to adjust the liveness
56 /// of registers. This can be useful when dealing with sub-registers.
59 /// EXTRACT_SUBREG - This instruction takes two operands: a register
60 /// that has subregisters, and a subregister index. It returns the
61 /// extracted subregister value. This is commonly used to implement
62 /// truncation operations on target architectures which support it.
65 /// INSERT_SUBREG - This instruction takes three operands: a register
66 /// that has subregisters, a register providing an insert value, and a
67 /// subregister index. It returns the value of the first register with
68 /// the value of the second register inserted. The first register is
69 /// often defined by an IMPLICIT_DEF, as is commonly used to implement
70 /// anyext operations on target architectures which support it.
73 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
76 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
77 /// that the first operand is an immediate integer constant. This constant
78 /// is often zero, as is commonly used to implement zext operations on
79 /// target architectures which support it, such as with x86-64 (with
80 /// zext from i32 to i64 via implicit zero-extension).
83 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
84 /// register-to-register copy into a specific register class. This is only
85 /// used between instruction selection and MachineInstr creation, before
86 /// virtual registers have been created for all the instructions, and it's
87 /// only needed in cases where the register classes implied by the
88 /// instructions are insufficient. The actual MachineInstrs to perform
89 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
93 unsigned getNumOpcodes() const { return NumOpcodes; }
95 /// get - Return the machine instruction descriptor that corresponds to the
96 /// specified instruction opcode.
98 const TargetInstrDesc &get(unsigned Opcode) const {
99 assert(Opcode < NumOpcodes && "Invalid opcode!");
100 return Descriptors[Opcode];
103 /// isTriviallyReMaterializable - Return true if the instruction is trivially
104 /// rematerializable, meaning it has no side effects and requires no operands
105 /// that aren't always available.
106 bool isTriviallyReMaterializable(const MachineInstr *MI,
107 AliasAnalysis *AA = 0) const {
108 return MI->getOpcode() == IMPLICIT_DEF ||
109 (MI->getDesc().isRematerializable() &&
110 (isReallyTriviallyReMaterializable(MI, AA) ||
111 isReallyTriviallyReMaterializableGeneric(MI, AA)));
115 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
116 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
117 /// specify whether the instruction is actually trivially rematerializable,
118 /// taking into consideration its operands. This predicate must return false
119 /// if the instruction has any side effects other than producing a value, or
120 /// if it requres any address registers that are not always available.
121 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
122 AliasAnalysis *AA) const {
127 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
128 /// for which the M_REMATERIALIZABLE flag is set and the target hook
129 /// isReallyTriviallyReMaterializable returns false, this function does
130 /// target-independent tests to determine if the instruction is really
131 /// trivially rematerializable.
132 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
133 AliasAnalysis *AA) const;
136 /// Return true if the instruction is a register to register move and return
137 /// the source and dest operands and their sub-register indices by reference.
138 virtual bool isMoveInstr(const MachineInstr& MI,
139 unsigned& SrcReg, unsigned& DstReg,
140 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
144 /// isLoadFromStackSlot - If the specified machine instruction is a direct
145 /// load from a stack slot, return the virtual or physical register number of
146 /// the destination along with the FrameIndex of the loaded stack slot. If
147 /// not, return 0. This predicate must return 0 if the instruction has
148 /// any side effects other than loading from the stack slot.
149 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
150 int &FrameIndex) const {
154 /// isStoreToStackSlot - If the specified machine instruction is a direct
155 /// store to a stack slot, return the virtual or physical register number of
156 /// the source reg along with the FrameIndex of the loaded stack slot. If
157 /// not, return 0. This predicate must return 0 if the instruction has
158 /// any side effects other than storing to the stack slot.
159 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
160 int &FrameIndex) const {
164 /// reMaterialize - Re-issue the specified 'original' instruction at the
165 /// specific location targeting a new destination register.
166 virtual void reMaterialize(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MI,
168 unsigned DestReg, unsigned SubIdx,
169 const MachineInstr *Orig) const = 0;
171 /// convertToThreeAddress - This method must be implemented by targets that
172 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
173 /// may be able to convert a two-address instruction into one or more true
174 /// three-address instructions on demand. This allows the X86 target (for
175 /// example) to convert ADD and SHL instructions into LEA instructions if they
176 /// would require register copies due to two-addressness.
178 /// This method returns a null pointer if the transformation cannot be
179 /// performed, otherwise it returns the last new instruction.
181 virtual MachineInstr *
182 convertToThreeAddress(MachineFunction::iterator &MFI,
183 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
187 /// commuteInstruction - If a target has any instructions that are commutable,
188 /// but require converting to a different instruction or making non-trivial
189 /// changes to commute them, this method can overloaded to do this. The
190 /// default implementation of this method simply swaps the first two operands
191 /// of MI and returns it.
193 /// If a target wants to make more aggressive changes, they can construct and
194 /// return a new machine instruction. If an instruction cannot commute, it
195 /// can also return null.
197 /// If NewMI is true, then a new machine instruction must be created.
199 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
200 bool NewMI = false) const = 0;
202 /// findCommutedOpIndices - If specified MI is commutable, return the two
203 /// operand indices that would swap value. Return true if the instruction
204 /// is not in a form which this routine understands.
205 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
206 unsigned &SrcOpIdx2) const = 0;
208 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
209 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
210 /// implemented for a target). Upon success, this returns false and returns
211 /// with the following information in various cases:
213 /// 1. If this block ends with no branches (it just falls through to its succ)
214 /// just return false, leaving TBB/FBB null.
215 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
216 /// the destination block.
217 /// 3. If this block ends with an conditional branch and it falls through to
218 /// a successor block, it sets TBB to be the branch destination block and
219 /// a list of operands that evaluate the condition. These
220 /// operands can be passed to other TargetInstrInfo methods to create new
222 /// 4. If this block ends with a conditional branch followed by an
223 /// unconditional branch, it returns the 'true' destination in TBB, the
224 /// 'false' destination in FBB, and a list of operands that evaluate the
225 /// condition. These operands can be passed to other TargetInstrInfo
226 /// methods to create new branches.
228 /// Note that RemoveBranch and InsertBranch must be implemented to support
229 /// cases where this method returns success.
231 /// If AllowModify is true, then this routine is allowed to modify the basic
232 /// block (e.g. delete instructions after the unconditional branch).
234 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
235 MachineBasicBlock *&FBB,
236 SmallVectorImpl<MachineOperand> &Cond,
237 bool AllowModify = false) const {
241 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
242 /// This is only invoked in cases where AnalyzeBranch returns success. It
243 /// returns the number of instructions that were removed.
244 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
245 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
249 /// InsertBranch - Insert branch code into the end of the specified
250 /// MachineBasicBlock. The operands to this method are the same as those
251 /// returned by AnalyzeBranch. This is only invoked in cases where
252 /// AnalyzeBranch returns success. It returns the number of instructions
255 /// It is also invoked by tail merging to add unconditional branches in
256 /// cases where AnalyzeBranch doesn't apply because there was no original
257 /// branch to analyze. At least this much must be implemented, else tail
258 /// merging needs to be disabled.
259 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
260 MachineBasicBlock *FBB,
261 const SmallVectorImpl<MachineOperand> &Cond) const {
262 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
266 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
267 /// returns false if the target does not how to copy between the specified
269 virtual bool copyRegToReg(MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator MI,
271 unsigned DestReg, unsigned SrcReg,
272 const TargetRegisterClass *DestRC,
273 const TargetRegisterClass *SrcRC) const {
274 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
278 /// storeRegToStackSlot - Store the specified register of the given register
279 /// class to the specified stack frame index. The store instruction is to be
280 /// added to the given machine basic block before the specified machine
281 /// instruction. If isKill is true, the register operand is the last use and
282 /// must be marked kill.
283 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
284 MachineBasicBlock::iterator MI,
285 unsigned SrcReg, bool isKill, int FrameIndex,
286 const TargetRegisterClass *RC) const {
287 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
290 /// loadRegFromStackSlot - Load the specified register of the given register
291 /// class from the specified stack frame index. The load instruction is to be
292 /// added to the given machine basic block before the specified machine
294 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
295 MachineBasicBlock::iterator MI,
296 unsigned DestReg, int FrameIndex,
297 const TargetRegisterClass *RC) const {
298 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
301 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
302 /// saved registers and returns true if it isn't possible / profitable to do
303 /// so by issuing a series of store instructions via
304 /// storeRegToStackSlot(). Returns false otherwise.
305 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
306 MachineBasicBlock::iterator MI,
307 const std::vector<CalleeSavedInfo> &CSI) const {
311 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
312 /// saved registers and returns true if it isn't possible / profitable to do
313 /// so by issuing a series of load instructions via loadRegToStackSlot().
314 /// Returns false otherwise.
315 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
316 MachineBasicBlock::iterator MI,
317 const std::vector<CalleeSavedInfo> &CSI) const {
321 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
322 /// slot into the specified machine instruction for the specified operand(s).
323 /// If this is possible, a new instruction is returned with the specified
324 /// operand folded, otherwise NULL is returned. The client is responsible for
325 /// removing the old instruction and adding the new one in the instruction
327 MachineInstr* foldMemoryOperand(MachineFunction &MF,
329 const SmallVectorImpl<unsigned> &Ops,
330 int FrameIndex) const;
332 /// foldMemoryOperand - Same as the previous version except it allows folding
333 /// of any load and store from / to any address, not just from a specific
335 MachineInstr* foldMemoryOperand(MachineFunction &MF,
337 const SmallVectorImpl<unsigned> &Ops,
338 MachineInstr* LoadMI) const;
341 /// foldMemoryOperandImpl - Target-dependent implementation for
342 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
343 /// take care of adding a MachineMemOperand to the newly created instruction.
344 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
346 const SmallVectorImpl<unsigned> &Ops,
347 int FrameIndex) const {
351 /// foldMemoryOperandImpl - Target-dependent implementation for
352 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
353 /// take care of adding a MachineMemOperand to the newly created instruction.
354 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
356 const SmallVectorImpl<unsigned> &Ops,
357 MachineInstr* LoadMI) const {
362 /// canFoldMemoryOperand - Returns true for the specified load / store if
363 /// folding is possible.
365 bool canFoldMemoryOperand(const MachineInstr *MI,
366 const SmallVectorImpl<unsigned> &Ops) const {
370 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
371 /// a store or a load and a store into two or more instruction. If this is
372 /// possible, returns true as well as the new instructions by reference.
373 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
374 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
375 SmallVectorImpl<MachineInstr*> &NewMIs) const{
379 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
380 SmallVectorImpl<SDNode*> &NewNodes) const {
384 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
385 /// instruction after load / store are unfolded from an instruction of the
386 /// specified opcode. It returns zero if the specified unfolding is not
388 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
389 bool UnfoldLoad, bool UnfoldStore) const {
393 /// BlockHasNoFallThrough - Return true if the specified block does not
394 /// fall-through into its successor block. This is primarily used when a
395 /// branch is unanalyzable. It is useful for things like unconditional
396 /// indirect branches (jump tables).
397 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
401 /// ReverseBranchCondition - Reverses the branch condition of the specified
402 /// condition list, returning false on success and true if it cannot be
405 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
409 /// insertNoop - Insert a noop into the instruction stream at the specified
411 virtual void insertNoop(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator MI) const;
414 /// isPredicated - Returns true if the instruction is already predicated.
416 virtual bool isPredicated(const MachineInstr *MI) const {
420 /// isUnpredicatedTerminator - Returns true if the instruction is a
421 /// terminator instruction that has not been predicated.
422 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
424 /// PredicateInstruction - Convert the instruction into a predicated
425 /// instruction. It returns true if the operation was successful.
427 bool PredicateInstruction(MachineInstr *MI,
428 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
430 /// SubsumesPredicate - Returns true if the first specified predicate
431 /// subsumes the second, e.g. GE subsumes GT.
433 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
434 const SmallVectorImpl<MachineOperand> &Pred2) const {
438 /// DefinesPredicate - If the specified instruction defines any predicate
439 /// or condition code register(s) used for predication, returns true as well
440 /// as the definition predicate(s) by reference.
441 virtual bool DefinesPredicate(MachineInstr *MI,
442 std::vector<MachineOperand> &Pred) const {
446 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
447 /// instruction that defines the specified register class.
448 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
452 /// isDeadInstruction - Return true if the instruction is considered dead.
453 /// This allows some late codegen passes to delete them.
454 virtual bool isDeadInstruction(const MachineInstr *MI) const = 0;
456 /// GetInstSize - Returns the size of the specified Instruction.
458 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
459 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
463 /// GetFunctionSizeInBytes - Returns the size of the specified
466 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
468 /// Measure the specified inline asm to determine an approximation of its
470 virtual unsigned getInlineAsmLength(const char *Str,
471 const MCAsmInfo &MAI) const;
474 /// TargetInstrInfoImpl - This is the default implementation of
475 /// TargetInstrInfo, which just provides a couple of default implementations
476 /// for various methods. This separated out because it is implemented in
477 /// libcodegen, not in libtarget.
478 class TargetInstrInfoImpl : public TargetInstrInfo {
480 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
481 : TargetInstrInfo(desc, NumOpcodes) {}
483 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
484 bool NewMI = false) const;
485 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
486 unsigned &SrcOpIdx2) const;
487 virtual bool PredicateInstruction(MachineInstr *MI,
488 const SmallVectorImpl<MachineOperand> &Pred) const;
489 virtual void reMaterialize(MachineBasicBlock &MBB,
490 MachineBasicBlock::iterator MI,
491 unsigned DestReg, unsigned SubReg,
492 const MachineInstr *Orig) const;
493 virtual bool isDeadInstruction(const MachineInstr *MI) const;
495 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
498 } // End llvm namespace